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406 lines
11 KiB
VHDL
406 lines
11 KiB
VHDL
------------------------------------------------------------------------
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-- RS232RefCom.vhd
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------------------------------------------------------------------------
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-- Author: Dan Pederson
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-- Copyright 2004 Digilent, Inc.
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------------------------------------------------------------------------
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-- Description: This file defines a UART which tranfers data from
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-- serial form to parallel form and vice versa.
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------------------------------------------------------------------------
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-- Revision History:
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-- 07/15/04 (Created) DanP
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-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
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-- in the Clock Dividing Processes
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------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Rs232RefComp is
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Port (
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TXD : out std_logic := '1';
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RXD : in std_logic;
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CLK : in std_logic; --Master Clock
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DBIN : in std_logic_vector (7 downto 0); --Data Bus in
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DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
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RDA : inout std_logic; --Read Data Available
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TBE : inout std_logic := '1'; --Transfer Bus Empty
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RD : in std_logic; --Read Strobe
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WR : in std_logic; --Write Strobe
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PE : out std_logic; --Parity Error Flag
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FE : out std_logic; --Frame Error Flag
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OE : out std_logic; --Overwrite Error Flag
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RST : in std_logic := '0'); --Master Reset
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end Rs232RefComp;
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architecture Behavioral of Rs232RefComp is
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------------------------------------------------------------------------
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-- Component Declarations
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Local Type Declarations
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------------------------------------------------------------------------
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--Receive state machine
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type rstate is (
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strIdle, --Idle state
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strEightDelay, --Delays for 8 clock cycles
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strGetData, --Shifts in the 8 data bits, and checks parity
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strCheckStop --Sets framing error flag if Stop bit is wrong
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);
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type tstate is (
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sttIdle, --Idle state
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sttTransfer, --Move data into shift register
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sttShift --Shift out data
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);
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type TBEstate is (
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stbeIdle,
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stbeSetTBE,
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stbeWaitLoad,
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stbeWaitWrite
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);
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------------------------------------------------------------------------
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-- Signal Declarations
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------------------------------------------------------------------------
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constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
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--Found by dividing 50MHz by 9600 and 16.
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signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
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signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
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signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
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signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
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signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
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signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
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signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
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signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
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signal rClk : std_logic := '0'; --Receiving Clock
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signal tClk : std_logic; --Transfering Clock
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signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
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signal parError: std_logic; --Parity error bit
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signal frameError: std_logic; --Frame error bit
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signal CE : std_logic; --Clock enable for the latch
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signal ctRst : std_logic := '0';
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signal load : std_logic := '0';
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signal shift : std_logic := '0';
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signal par : std_logic;
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signal tClkRST : std_logic := '0';
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signal rShift : std_logic := '0';
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signal dataRST : std_logic := '0';
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signal dataIncr: std_logic := '0';
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signal strCur : rstate := strIdle; --Current state in the Receive state machine
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signal strNext : rstate; --Next state in the Receive state machine
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signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
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signal sttNext : tstate; --Next state in the Transfer staet machine
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signal stbeCur : TBEstate := stbeIdle;
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signal stbeNext: TBEstate;
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------------------------------------------------------------------------
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-- Module Implementation
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------------------------------------------------------------------------
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begin
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frameError <= not rdSReg(9);
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parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
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DBOUT <= rdReg;
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tfReg <= DBIN;
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par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
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--Clock Dividing Functions--
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process (CLK, clkDiv) --set up clock divide for rClk
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begin
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if (Clk = '1' and Clk'event) then
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if (clkDiv = baudDivide) then
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clkDiv <= "000000000";
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else
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clkDiv <= clkDiv +1;
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end if;
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end if;
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end process;
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process (clkDiv, rClk, CLK) --Define rClk
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begin
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if CLK = '1' and CLK'Event then
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if clkDiv = baudDivide then
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rClk <= not rClk;
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else
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rClk <= rClk;
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end if;
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end if;
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end process;
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process (rClk) --set up clock divide for tClk
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begin
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if (rClk = '1' and rClk'event) then
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rClkDiv <= rClkDiv +1;
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end if;
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end process;
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tClk <= rClkDiv(3); --define tClk
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process (rClk, ctRst) --set up a counter based on rClk
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begin
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if rClk = '1' and rClk'Event then
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if ctRst = '1' then
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ctr <= "0000";
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else
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ctr <= ctr +1;
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end if;
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end if;
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end process;
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process (tClk, tClkRST) --set up a counter based on tClk
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begin
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if (tClk = '1' and tClk'event) then
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if tClkRST = '1' then
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tfCtr <= "0000";
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else
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tfCtr <= tfCtr +1;
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end if;
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end if;
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end process;
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--This process controls the error flags--
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process (rClk, RST, RD, CE)
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begin
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if RD = '1' or RST = '1' then
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FE <= '0';
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OE <= '0';
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RDA <= '0';
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PE <= '0';
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elsif rClk = '1' and rClk'event then
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if CE = '1' then
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FE <= frameError;
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OE <= RDA;
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RDA <= '1';
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PE <= parError;
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rdReg(7 downto 0) <= rdSReg (7 downto 0);
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end if;
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end if;
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end process;
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--This process controls the receiving shift register--
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process (rClk, rShift)
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begin
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if rClk = '1' and rClk'Event then
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if rShift = '1' then
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rdSReg <= (RXD & rdSReg(9 downto 1));
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end if;
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end if;
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end process;
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--This process controls the dataCtr to keep track of shifted values--
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process (rClk, dataRST)
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begin
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if (rClk = '1' and rClk'event) then
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if dataRST = '1' then
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dataCtr <= "0000";
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elsif dataIncr = '1' then
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dataCtr <= dataCtr +1;
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end if;
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end if;
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end process;
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--Receiving State Machine--
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process (rClk, RST)
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begin
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if rClk = '1' and rClk'Event then
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if RST = '1' then
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strCur <= strIdle;
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else
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strCur <= strNext;
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end if;
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end if;
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end process;
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--This process generates the sequence of steps needed receive the data
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process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
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begin
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case strCur is
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when strIdle =>
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dataIncr <= '0';
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rShift <= '0';
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dataRst <= '0';
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CE <= '0';
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if RXD = '0' then
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ctRst <= '1';
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strNext <= strEightDelay;
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else
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ctRst <= '0';
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strNext <= strIdle;
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end if;
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when strEightDelay =>
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dataIncr <= '0';
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rShift <= '0';
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CE <= '0';
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if ctr(2 downto 0) = "111" then
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ctRst <= '1';
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dataRST <= '1';
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strNext <= strGetData;
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else
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ctRst <= '0';
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dataRST <= '0';
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strNext <= strEightDelay;
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end if;
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when strGetData =>
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CE <= '0';
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dataRst <= '0';
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if ctr(3 downto 0) = "1111" then
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ctRst <= '1';
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dataIncr <= '1';
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rShift <= '1';
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else
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ctRst <= '0';
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dataIncr <= '0';
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rShift <= '0';
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end if;
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if dataCtr = "1010" then
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strNext <= strCheckStop;
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else
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strNext <= strGetData;
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end if;
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when strCheckStop =>
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dataIncr <= '0';
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rShift <= '0';
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dataRst <= '0';
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ctRst <= '0';
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CE <= '1';
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strNext <= strIdle;
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end case;
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end process;
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--TBE State Machine--
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process (CLK, RST)
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begin
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if CLK = '1' and CLK'Event then
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if RST = '1' then
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stbeCur <= stbeIdle;
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else
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stbeCur <= stbeNext;
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end if;
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end if;
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end process;
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--This process gererates the sequence of events needed to control the TBE flag--
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process (stbeCur, CLK, WR, DBIN, load)
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begin
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case stbeCur is
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when stbeIdle =>
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TBE <= '1';
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if WR = '1' then
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stbeNext <= stbeSetTBE;
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else
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stbeNext <= stbeIdle;
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end if;
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when stbeSetTBE =>
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TBE <= '0';
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if load = '1' then
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stbeNext <= stbeWaitLoad;
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else
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stbeNext <= stbeSetTBE;
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end if;
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when stbeWaitLoad =>
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if load = '0' then
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stbeNext <= stbeWaitWrite;
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else
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stbeNext <= stbeWaitLoad;
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end if;
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when stbeWaitWrite =>
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if WR = '0' then
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stbeNext <= stbeIdle;
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else
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stbeNext <= stbeWaitWrite;
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end if;
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end case;
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end process;
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--This process loads and shifts out the transfer shift register--
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process (load, shift, tClk, tfSReg)
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begin
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TXD <= tfsReg(0);
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if tClk = '1' and tClk'Event then
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if load = '1' then
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tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
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end if;
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if shift = '1' then
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tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
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end if;
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end if;
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end process;
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-- Transfer State Machine--
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process (tClk, RST)
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begin
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if (tClk = '1' and tClk'Event) then
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if RST = '1' then
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sttCur <= sttIdle;
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else
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sttCur <= sttNext;
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end if;
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end if;
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end process;
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-- This process generates the sequence of steps needed transfer the data--
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process (sttCur, tfCtr, tfReg, TBE, tclk)
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begin
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case sttCur is
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when sttIdle =>
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tClkRST <= '0';
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shift <= '0';
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load <= '0';
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if TBE = '1' then
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sttNext <= sttIdle;
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else
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sttNext <= sttTransfer;
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end if;
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when sttTransfer =>
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shift <= '0';
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load <= '1';
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tClkRST <= '1';
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sttNext <= sttShift;
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when sttShift =>
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shift <= '1';
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load <= '0';
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tClkRST <= '0';
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if tfCtr = "1100" then
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sttNext <= sttIdle;
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else
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sttNext <= sttShift;
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end if;
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end case;
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end process;
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end Behavioral; |