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159 lines
7.0 KiB
VHDL
159 lines
7.0 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-05B.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- M & N register (MSAR) assembly
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY MNAssem IS
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port
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(
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-- Inputs
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MAIN_STORAGE_CP : IN STD_LOGIC; -- 04D
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SX_2_BUMP_SW_GT : IN STD_LOGIC; -- 13C
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USE_CPU_DECODER : IN STD_LOGIC; -- 05C
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E_SEL_SW_BUS : IN E_SW_BUS_Type; -- 04C
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SALS : IN SALS_Bus; -- 01C
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MEM_SEL : IN STD_LOGIC; -- 03D
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USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
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N1401_MODE : IN STD_LOGIC; -- 05A
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USE_MANUAL_DECODER : IN STD_LOGIC; -- 03D
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SX_2_R_W_CTRL : IN STD_LOGIC; -- 14D
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SX_2_SHARE_CYCLE : IN STD_LOGIC; -- 14D
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SX_2_GATE : IN STD_LOGIC; -- 13C
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SX_1_R_W_CTRL : IN STD_LOGIC; -- 12D
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SX_1_SHARE_CYCLE : IN STD_LOGIC; -- 12D
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SX_1_GATE : IN STD_LOGIC; -- 13C
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XXH : IN STD_LOGIC; -- 08C
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CU_DECODE_UCW : IN STD_LOGIC; -- 04D
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FORCE_M_REG_123 : IN STD_LOGIC; -- 04D
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XH,XL : IN STD_LOGIC; -- 08C
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CU_SAL_0_BIT : IN STD_LOGIC; -- 01C
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MACH_RST_2A : IN STD_LOGIC; -- 06B
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ABCD_SW_BUS : IN STD_LOGIC_VECTOR(0 to 15); -- 04B
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AB_SW_P,CD_SW_P : IN STD_LOGIC; -- 04B
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I,U,T,V,J,L,GU,GV,HU,HV : IN STD_LOGIC_VECTOR(0 to 7);
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I_P,U_P,T_P,V_P,J_P,L_P,GU_P,GV_P,HU_P,HV_P : IN STD_LOGIC;
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IJ_SEL, UV_SEL : IN STD_LOGIC; -- 04C
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-- Outputs
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GT_T_TO_MN_REG : OUT STD_LOGIC; -- 08B
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GT_CK_TO_MN_REG : OUT STD_LOGIC; -- 08B
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GT_V_TO_N_REG : OUT STD_LOGIC; -- 03B
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GT_J_TO_N_REG : OUT STD_LOGIC; -- 03B
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M_BUS,N_BUS : OUT STD_LOGIC_VECTOR(0 to 7);
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M_BUS_P,N_BUS_P : OUT STD_LOGIC
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);
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END MNAssem;
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ARCHITECTURE FMD OF MNAssem IS
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signal GT_ABCD_SWS_TO_MN : STD_LOGIC;
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signal GT_I_TO_M_REG,GT_U_TO_M_REG : STD_LOGIC;
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signal CK_BUS : STD_LOGIC_VECTOR(0 to 7);
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signal CK_BUS_P : STD_LOGIC;
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signal GATE_L_REG_TO_M_BUS : STD_LOGIC;
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signal GT_GUV_OR_HUV_TO_MN : STD_LOGIC;
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signal GT_HUV_TO_MN,GT_GUV_TO_MN : STD_LOGIC;
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signal M_BUSP,N_BUSP : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
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signal sGT_T_TO_MN_REG : STD_LOGIC;
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signal sGT_CK_TO_MN_REG : STD_LOGIC;
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signal sGT_V_TO_N_REG : STD_LOGIC;
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signal sGT_J_TO_N_REG : STD_LOGIC;
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BEGIN
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-- Fig 5-05B
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GT_ABCD_SWS_TO_MN <= MEM_SEL and USE_MAN_DECODER_PWR; -- AC1F3
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GT_I_TO_M_REG <= IJ_SEL or (MAIN_STORAGE_CP and USE_CPU_DECODER and not SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2)); -- AA1H2,AA1H7,AA1J7 CM=011
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GT_U_TO_M_REG <= (MAIN_STORAGE_CP and USE_CPU_DECODER and SALS.SALS_CM(0) and not SALS.SALS_CM(1) and not SALS.SALS_CM(2)) or UV_SEL; -- AA1H7,AA1H2,AA1J7 CM=100
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sGT_T_TO_MN_REG <= USE_CPU_DECODER and SALS.SALS_CM(0) and not SALS.SALS_CM(1) and SALS.SALS_CM(2); -- AB3E2,AB3F7-removed?? CM=101
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GT_T_TO_MN_REG <= sGT_T_TO_MN_REG;
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sGT_CK_TO_MN_REG <= USE_CPU_DECODER and SALS.SALS_CM(0) and SALS.SALS_CM(1) and not SALS.SALS_CM(2); -- AB3E2,AB3F7-removed?? CM=110
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GT_CK_TO_MN_REG <= sGT_CK_TO_MN_REG;
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CK_BUS(0) <= '1';
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CK_BUS(1) <= '0';
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CK_BUS(2) <= SALS.SALS_CN(0) or SX_2_BUMP_SW_GT; -- AB1C6
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CK_BUS(3) <= SALS.SALS_CK(0);
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CK_BUS(4) <= '1';
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CK_BUS(5) <= SALS.SALS_CK(1);
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CK_BUS(6) <= SALS.SALS_CK(2);
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CK_BUS(7) <= SALS.SALS_CK(3);
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CK_BUS_P <= (not SALS.SALS_PK or SALS.SALS_CM(0) or not CK_BUS(2)) and (not SALS.SALS_PK or SX_2_BUMP_SW_GT); -- AB1C6
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sGT_V_TO_N_REG <= UV_SEL or (SALS.SALS_CM(0) and not SALS.SALS_CM(1) and not SALS.SALS_CM(2) and USE_CPU_DECODER); -- AB3C2 CM=100
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GT_V_TO_N_REG <= sGT_V_TO_N_REG;
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sGT_J_TO_N_REG <= (not SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2) and USE_CPU_DECODER) or IJ_SEL; -- AB3C2 CM=011
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GT_J_TO_N_REG <= sGT_J_TO_N_REG;
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GT_GUV_OR_HUV_TO_MN <= USE_CPU_DECODER and SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2); -- AB3C2 CM=111
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GT_HUV_TO_MN <= (USE_MANUAL_DECODER and E_SEL_SW_BUS.E_SEL_SW_HUV_HCD) or (not SX_2_R_W_CTRL and SX_2_SHARE_CYCLE) or (SX_2_GATE and GT_GUV_OR_HUV_TO_MN); -- AE1D5
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GT_GUV_TO_MN <= (USE_MANUAL_DECODER and E_SEL_SW_BUS.E_SEL_SW_GUV_GCD) or (not SX_1_R_W_CTRL and SX_1_SHARE_CYCLE) or (GT_GUV_OR_HUV_TO_MN and SX_1_GATE); -- AD1H6
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GATE_L_REG_TO_M_BUS <= N1401_MODE and MAIN_STORAGE_CP and sGT_T_TO_MN_REG; -- AB2B3
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M_BUSP <= ((0 to 8 => GT_HUV_TO_MN) and HU & HU_P) or -- AB1D2
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((0 to 8 => GT_ABCD_SWS_TO_MN) and ABCD_SW_BUS(0 to 7) & AB_SW_P) or -- AB1D2
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((0 to 8 => GATE_L_REG_TO_M_BUS) and L & L_P) or -- AB1D2
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((0 to 8 => GT_GUV_TO_MN) and GU & GU_P) or -- AB1C2
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((0 to 8 => GT_I_TO_M_REG) and I & I_P) or -- AB1C2
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((0 to 8 => GT_U_TO_M_REG) and U & U_P) or -- AB1C2
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(0 => '0', 1 => (XXH and CU_DECODE_UCW) or (CU_DECODE_UCW and N1401_MODE) or FORCE_M_REG_123, 2 to 8 => '0') or -- AA1B4
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(0 to 1 => '0', 2 => (CU_DECODE_UCW and XH and not N1401_MODE) or FORCE_M_REG_123, 3 to 8 => '0') or -- AB1B3,AA1J4
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(0 to 2 => '0', 3 => (CU_DECODE_UCW and XL) or (FORCE_M_REG_123 and not N1401_MODE) or (N1401_MODE and CU_SAL_0_BIT and USE_CPU_DECODER), 4 to 8 => '0') or -- AA1B4
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(0 to 7 => '0', 8 => (not N1401_MODE and sGT_T_TO_MN_REG) or MACH_RST_2A or sGT_CK_TO_MN_REG); -- AB1G2
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M_BUS <= M_BUSP(0 to 7);
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M_BUS_P <= M_BUSP(8);
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N_BUSP <= ((0 to 8 => GT_ABCD_SWS_TO_MN) and ABCD_SW_BUS(8 to 15) & CD_SW_P) or -- AB1D4
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((0 to 8 => sGT_CK_TO_MN_REG) and CK_BUS & CK_BUS_P) or -- AB1D4
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(0 to 7 => '0', 8 => MACH_RST_2A) or -- AB1D4
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((0 to 8 => sGT_T_TO_MN_REG) and T & T_P) or -- AB1C4
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((0 to 8 => sGT_V_TO_N_REG) and V & V_P) or -- AB1C4
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((0 to 8 => sGT_J_TO_N_REG) and J & J_P) or -- AB1C4
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((0 to 8 => GT_HUV_TO_MN) and HV & HV_P) or -- AB1E4
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((0 to 8 => GT_GUV_TO_MN) and GV & GV_P); -- AB1E4
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N_BUS <= N_BUSP(0 to 7);
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N_BUS_P <= N_BUSP(8);
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END FMD;
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