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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: buses2030.vhd
-- Creation Date:
-- Description:
-- This file defines various system-wide buses
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This package defines various common buses and structures
package Buses_package is
-- SALS Bus is the microcode word
type SALS_Bus is record
SALS_PN : STD_LOGIC;
SALS_CN : STD_LOGIC_VECTOR(0 to 5);
SALS_PS : STD_LOGIC;
SALS_PA : STD_LOGIC;
SALS_CH : STD_LOGIC_VECTOR(0 to 3);
SALS_CL : STD_LOGIC_VECTOR(0 to 3);
SALS_CM : STD_LOGIC_VECTOR(0 to 2);
SALS_CU : STD_LOGIC_VECTOR(0 to 1);
SALS_CA : STD_LOGIC_VECTOR(0 to 3);
SALS_CB : STD_LOGIC_VECTOR(0 to 1);
SALS_CK : STD_LOGIC_VECTOR(0 to 3);
SALS_PK : STD_LOGIC;
SALS_PC : STD_LOGIC;
SALS_CD : STD_LOGIC_VECTOR(0 to 3);
SALS_CF : STD_LOGIC_VECTOR(0 to 2);
SALS_CG : STD_LOGIC_VECTOR(0 to 1);
SALS_CV : STD_LOGIC_VECTOR(0 to 1);
SALS_CC : STD_LOGIC_VECTOR(0 to 2);
SALS_CS : STD_LOGIC_VECTOR(0 to 3);
SALS_AA : STD_LOGIC;
SALS_SA : STD_LOGIC;
SALS_AK : STD_LOGIC;
end record SALS_Bus;
-- The CTRL register is a subset of the SALS which is maintained
-- after the rest of the SALS is cleared as the next word is read
type CTRL_REG is record
CTRL_CD : STD_LOGIC_VECTOR(0 to 3); -- 05C
STRAIGHT : STD_LOGIC; -- Similar to CF(0) inverted
CROSSED : STD_LOGIC; -- Same as CF(0)
CTRL_CC : STD_LOGIC_VECTOR(0 to 2); -- CTRL REG BUS
GT_A_REG_HI : STD_LOGIC; -- Same as CF(1)
GT_A_REG_LO : STD_LOGIC; -- Same as CF(2)
COMPUTE_CY_LCH : STD_LOGIC; -- 06C & CTRL REG BUS
CTRL_CG : STD_LOGIC_VECTOR(0 to 1); -- 03B,06B & CTRL_REG_BUS
GT_B_REG_HI : STD_LOGIC; -- 06B, same as CG(0)
GT_B_REG_LO : STD_LOGIC; -- 06B, same as CG(1)
CTRL_CV : STD_LOGIC_VECTOR(0 to 1); -- CTRL REG BUS
CTRL_CS : STD_LOGIC_VECTOR(0 to 3); -- CTRL REG BUS
end record CTRL_REG;
-- The Priority bus is used to vector the microcode address when an external
-- interrupt occurs
type PRIORITY_BUS_Type is record
STOP_PULSE : STD_LOGIC; -- X0
PROTECT_PULSE : STD_LOGIC; -- X1
WRAP_PULSE : STD_LOGIC; -- X2
MPX_SHARE_PULSE : STD_LOGIC; -- X3
SX_CHAIN_PULSE : STD_LOGIC; -- X4
MACH_CHK_PULSE : STD_LOGIC; -- X5
IPL_PULSE : STD_LOGIC; -- X6
FORCE_IJ_PULSE : STD_LOGIC; -- X7
PRIORITY_PULSE : STD_LOGIC; -- XP
end record PRIORITY_BUS_Type;
-- The E Switch bus contains the various signals corresponding to the legends on the
-- selector switch. Only one of these signals will be true.
type E_SW_BUS_Type is record
-- Inner ring
I_SEL,J_SEL,U_SEL,V_SEL,L_SEL,T_SEL,D_SEL,R_SEL,S_SEL,G_SEL,H_SEL,FI_SEL,FT_SEL : STD_LOGIC;
-- Mid ring
MS_SEL, LS_SEL : STD_LOGIC; -- LS marked as AS on dial
-- Outer ring
Q_SEL,C_SEL,F_SEL,TT_SEL,TI_SEL,JI_SEL,
E_SEL_SW_GS,E_SEL_SW_GT,E_SEL_SW_GUV_GCD,
E_SEL_SW_HS,E_SEL_SW_HT,E_SEL_SW_HUV_HCD : STD_LOGIC;
end record E_SW_BUS_Type;
-- Mpx Tags Out are the tag signals from the CPU to a peripheral
type MPX_TAGS_OUT is record
OPL_OUT,
ADR_OUT,
ADR_OUT2, -- What is this?
CMD_OUT,
STA_OUT,
SRV_OUT,
HLD_OUT,
SEL_OUT,
SUP_OUT,
MTR_OUT,
CLK_OUT : STD_LOGIC;
end record MPX_TAGS_OUT;
-- Mpx Tags In are the tag signals from a peripheral to the CPU
type MPX_TAGS_IN is record
OPL_IN,
ADR_IN,
STA_IN,
SRV_IN,
SEL_IN,
REQ_IN,
MTR_IN : STD_LOGIC;
end record MPX_TAGS_IN;
-- List of front panel indicators
subtype IndicatorRange is integer range 0 to 249; -- 218 through 249 are temp debug items
end package Buses_package;

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Also add information on how to contact you by electronic and paper mail.
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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-01A-B.vhd
-- Creation Date:
-- Description:
-- WX register & indicators, CCROS parity check (5-01A), WX assembly (5-01B)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
USE work.Gates_package.all;
USE work.Buses_package.all;
-- This package implements the WX register and associated logic
-- Fig 5-01A, 5-01B
entity WX_Regs is
port (
-- Indicators
W_IND_P : OUT STD_LOGIC;
X_IND_P : OUT STD_LOGIC;
WX_IND : OUT STD_LOGIC_VECTOR(0 to 12);
-- CCROS interface
WX : OUT STD_LOGIC_VECTOR(0 to 12); -- 01BA5 01BA6 to 01CC1 04BD3
CROS_STROBE : OUT STD_LOGIC; -- 01BD2 to 01CC1
CROS_GO_PULSE : OUT STD_LOGIC; -- 01BD2 to 01CC1
SALS : IN SALS_Bus; -- 01C
-- Clock inputs
T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
clk : IN STD_LOGIC;
-- Switch inputs
SWS_FGP,SWS_HJP : IN STD_LOGIC; -- 04CA3
SWS_F3: IN STD_LOGIC; -- 04CA3
SWS_G,SWS_H,SWS_J : IN STD_LOGIC_VECTOR(0 to 3); -- 04CA3
-- UV bus input
U_P : IN STD_LOGIC; -- 05CC3
U3_7: IN STD_LOGIC_VECTOR(3 to 7); -- 05CC3
V_P : IN STD_LOGIC; -- 05CC4
V : IN STD_LOGIC_VECTOR(0 to 7); -- 05CC4
-- Priority bus input
PRIORITY_BUS_P : IN STD_LOGIC; -- 03AE6
PRIORITY_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 03AE6
-- X6,7 inputs
X6,X7 : IN STD_LOGIC; -- 02AE6
-- Status inputs
ANY_MACH_CHK : IN STD_LOGIC; -- 07AD6
CHK_OR_DIAG_STOP_SW : IN STD_LOGIC; -- 04AE3
EARLY_ROAR_STOP : IN STD_LOGIC; -- 03CC6
MACH_START_RST : IN STD_LOGIC; -- 04AD3
ALU_CHK : IN STD_LOGIC; -- 06AE6
ALU_CHK_LCH : IN STD_LOGIC; -- 06BE6
MACH_RST_SET_LCH : IN STD_LOGIC; -- 04BB2
MACH_RST_SET_LCH_DLY : IN STD_LOGIC; -- 04BB2
USE_ALT_CU_DECODER : IN STD_LOGIC; -- 04DC2
USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02AE6
GT_UV_TO_WX_REG : IN STD_LOGIC; -- 02BA2
GT_CA_TO_W_REG : IN STD_LOGIC; -- 02BA2
GT_FWX_TO_WX_REG,GT_GWX_TO_WX_REG : IN STD_LOGIC; -- 02AE4
GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04AD6
GT_SWS_TO_WX_LCH : IN STD_LOGIC; -- 03AB2
ANY_PRIORITY_PULSE : IN STD_LOGIC; -- 03AD6
ANY_PRIORITY_PULSE_PWR : IN STD_LOGIC; -- 03AD6
INH_ROSAR_SET : IN STD_LOGIC; -- 03CD3
CHK_SW_PROC_SW : IN STD_LOGIC; -- 04AE2
ROS_SCAN : IN STD_LOGIC; -- 03CE2
MACH_RST_2A : IN STD_LOGIC; -- 06BC6
MACH_RST_4,MACH_RST_5 : IN STD_LOGIC; -- 03DD2
N1401_MODE : IN STD_LOGIC; -- 05AD5
CARRY_0_LCHD : IN STD_LOGIC; -- 06AE3
HSMPX_TRAP : IN STD_LOGIC; -- XXXXX
SX_CHAIN_PULSE : IN STD_LOGIC; -- 03AC6
SEL_CC_ROS_REQ : IN STD_LOGIC; -- 12CA6
MPX_SHARE_PULSE : IN STD_LOGIC; -- 03AC6
ALLOW_PC_SALS : IN STD_LOGIC; -- 07AC4
TEST_LAMP : IN STD_LOGIC; -- ?????
-- Debug
DEBUG : OUT STD_LOGIC;
-- Outputs
SET_IND_ROSAR : OUT STD_LOGIC; --- 01AB2 to 07AB3
CTRL_REG_CHK : OUT STD_LOGIC; -- 01AD5 to 01BD1,07AC4
WX_CHK : OUT STD_LOGIC; -- 01AB5 to 07AC3
SAL_PC : OUT STD_LOGIC; -- 01AC5 to 01BD1,07AC4
GT_BU_ROSAR_TO_WX_REG : OUT STD_LOGIC; -- 01BA2 to 02AE2
SET_FW : OUT STD_LOGIC -- 01BE3 to 08CA1
);
end WX_Regs;
architecture FMD of WX_Regs is
signal SET_IND : STD_LOGIC;
signal FL_ROSAR_IND : STD_LOGIC;
signal GT_CK_TO_W_REG : STD_LOGIC;
signal sGT_BU_ROSAR_TO_WX_REG : STD_LOGIC;
signal NORMAL_ENTRY : STD_LOGIC;
signal SET_W2,SET_W2A,SET_W2B,SET_W_REG : STD_LOGIC;
signal SET_X_REG : STD_LOGIC;
signal W_P : STD_LOGIC;
signal X_P : STD_LOGIC;
signal sSET_IND_ROSAR : STD_LOGIC;
signal sWX : STD_LOGIC_VECTOR(0 to 12);
signal sINH_NORM_ENTRY : STD_LOGIC;
signal sCTRL_REG_CHK : STD_LOGIC;
signal sSAL_PC : STD_LOGIC;
-- WX display
signal WX_IND_X : STD_LOGIC_VECTOR(0 to 12);
signal W_IND_P_X, X_IND_P_X : STD_LOGIC;
-- New WX value
signal W_ASSM : STD_LOGIC_VECTOR(3 to 8); -- 8 is P
signal X_ASSM : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
-- Multiplexor backup ROSAR
signal FWX : STD_LOGIC_VECTOR(0 to 12);
alias FW : STD_LOGIC_VECTOR(3 to 7) is FWX(0 to 4);
alias FX : STD_LOGIC_VECTOR(0 to 7) is FWX(5 to 12);
signal FW_P : STD_LOGIC;
signal FX_P : STD_LOGIC;
signal SET_F : STD_LOGIC;
-- Selector backup ROSAR
signal GWX : STD_LOGIC_VECTOR(0 to 12);
alias GW : STD_LOGIC_VECTOR(3 to 7) is GWX(0 to 4);
alias GX : STD_LOGIC_VECTOR(0 to 7) is GWX(5 to 12);
signal GW_P : STD_LOGIC;
signal GX_P : STD_LOGIC;
signal SET_G : STD_LOGIC;
signal ROSAR_IND_LATCH_Set : STD_LOGIC;
signal PRIORITY_PARITY : STD_LOGIC;
BEGIN
-- Fig 5-01A
-- ROS Indicator register
ROSAR_IND_LATCH_Set <= (ANY_MACH_CHK and CHK_OR_DIAG_STOP_SW) or EARLY_ROAR_STOP;
ROSAR_IND_LATCH: FLL port map(ROSAR_IND_LATCH_Set,MACH_START_RST,FL_ROSAR_IND); -- AA3G4,AA3H4
-- sSET_IND_ROSAR <= (not ALU_CHK or not CHK_OR_DIAG_STOP_SW) and not FL_ROSAR_IND; -- AA3H4
sSET_IND_ROSAR <= '1'; -- Debug
SET_IND_ROSAR <= sSET_IND_ROSAR;
DEBUG <= FL_ROSAR_IND;
SET_IND <= (T4 and sSET_IND_ROSAR) or MACH_RST_SET_LCH; -- AA3J4
WINDP: PH port map(W_P,SET_IND,W_IND_P_X); -- AA3J2
W_IND_P <= W_IND_P_X or TEST_LAMP;
XINDP: PH port map(X_P,SET_IND,X_IND_P_X); -- AA3J3
X_IND_P <= X_IND_P_X or TEST_LAMP;
WXIND: PHV13 port map(sWX,SET_IND,WX_IND_X); -- AA3J2,AA3J3
WX_IND <= WX_IND_X or (WX_IND'range=>TEST_LAMP);
-- SALS parity checking
WX_CHK <= not(SALS.SALS_PA xor W_IND_P_X xor X_IND_P_X); -- AA2J4 ?? Inverted ??
-- WX_CHK <= not(SALS.SALS_PA xor W_P xor X_P); -- AA2J4 ?? or W_IND_P_X, X_IND_P_X as shown in diagram ??
sSAL_PC <= not EvenParity(USE_BASIC_CA_DECODER & SALS.SALS_AK & SALS.SALS_PK & SALS.SALS_CH & SALS.SALS_CL &
SALS.SALS_CM & SALS.SALS_CU & SALS.SALS_CA & SALS.SALS_CB & SALS.SALS_CK & SALS.SALS_PA & SALS.SALS_PS)
or
EvenParity(SALS.SALS_PN & SALS.SALS_CN);
SAL_PC <= sSAL_PC;
sCTRL_REG_CHK <= EvenParity(SALS.SALS_CD & SALS.SALS_SA & SALS.SALS_CS & SALS.SALS_CV & SALS.SALS_CC & SALS.SALS_CF & SALS.SALS_CG & SALS.SALS_PC);
CTRL_REG_CHK <= sCTRL_REG_CHK;
-- Fig 5-01B
-- W Reg assembly
PRIORITY_PARITY <= not N1401_MODE and not GT_SWS_TO_WX_LCH;
W_ASSM <= (
mux(GT_GWX_TO_WX_REG, GW & GW_P) or -- AA2G2
-- mux(ANY_PRIORITY_PULSE_PWR, (N1401_MODE & ROS_SCAN & '0' & (not GT_SWS_TO_WX_LCH and not N1401_MODE) & '0' & ROS_SCAN)) or -- AA2J2,AA2E3 ?? Sets W6 on restart ??
mux(ANY_PRIORITY_PULSE_PWR, (N1401_MODE & '0' & '0' & ROS_SCAN & ROS_SCAN & PRIORITY_PARITY)) or -- AA2J2,AA2E3 ?? See above for original version
mux(MACH_RST_2A,"00000" & not GT_SWS_TO_WX_LCH) or -- AA2F2,AA2E7 ?? See above
mux(GT_SWS_TO_WX_PWR, (SWS_F3 & SWS_G & SWS_FGP)) or -- AA2J2,AA2F2,AA2E3,AA2E2
mux(GT_UV_TO_WX_REG, U3_7 & U_P) or -- AA2J2,AA2F2,AA2E3,AA2E2
mux(GT_CK_TO_W_REG, (N1401_MODE & SALS.SALS_CK & SALS.SALS_PK)) or -- AA2J2,AA2F2,AA2E3,AA2E2
mux(GT_CA_TO_W_REG, (SALS.SALS_AA & SALS.SALS_CA & SALS.SALS_PK)) or -- AA2H2,AA2J2,AA2F2
mux(GT_FWX_TO_WX_REG, FW & FW_P)); -- AA2H2,AA2J2,AA2F2
-- X Reg assembly
sINH_NORM_ENTRY <= '1' when SALS.SALS_CK="0101" and SALS.SALS_AK='1' and CARRY_0_LCHD='1' else '0'; -- AB3H7,AA2F5
X_ASSM <= (
mux(GT_FWX_TO_WX_REG, FX & FX_P) or -- AA2G3
mux(ANY_PRIORITY_PULSE_PWR, PRIORITY_BUS & PRIORITY_BUS_P) or -- AA2G3
mux(GT_GWX_TO_WX_REG, GX & GX_P) or -- AA2G3
mux(GT_SWS_TO_WX_PWR, SWS_H & SWS_J & SWS_HJP) or -- AA2F3
mux(GT_UV_TO_WX_REG, V & V_P) or -- AA2F3
mux(NORMAL_ENTRY and not sINH_NORM_ENTRY, (SALS.SALS_CN & X6 & X7 & (SALS.SALS_PN xor X6 xor X7))) or -- AA2F3
mux(not SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3) and SALS.SALS_AK and CARRY_0_LCHD ,"000000001") or -- AA2H5
mux(ANY_PRIORITY_PULSE_PWR and SEL_CC_ROS_REQ and SX_CHAIN_PULSE, "000000110") or -- AA2H3
mux(HSMPX_TRAP and SX_CHAIN_PULSE, "000001001") -- AA2E7
);
-- WX Reg loading
GT_CK_TO_W_REG <= '1' when USE_ALT_CU_DECODER='1' and SALS.SALS_CU="10" else '0'; -- AB3D6
sGT_BU_ROSAR_TO_WX_REG <= '1' when USE_ALT_CU_DECODER='1' and SALS.SALS_CU="11" else '0'; -- AB3D6
GT_BU_ROSAR_TO_WX_REG <= sGT_BU_ROSAR_TO_WX_REG;
NORMAL_ENTRY <= not sGT_BU_ROSAR_TO_WX_REG and not GT_UV_TO_WX_REG and not ANY_PRIORITY_PULSE; -- AA2C7
-- W_LATCH:
SET_W2A <= not ANY_PRIORITY_PULSE_PWR or not ALU_CHK_LCH or not CHK_SW_PROC_SW; -- AA2H5 ?? What does this do?
-- SET_W2A <= '1';
SET_W2B <= sGT_BU_ROSAR_TO_WX_REG or not NORMAL_ENTRY; -- AA2F2
SET_W2 <= SET_W2A and SET_W2B; -- AA2H5,AA2F2 Wired-AND
SET_W_REG <= ((GT_CA_TO_W_REG or GT_CK_TO_W_REG or SET_W2) and P1) or MACH_RST_SET_LCH_DLY; -- AA2D2
REG_W: PHV5 port map(W_ASSM(3 to 7),SET_W_REG,sWX(0 to 4)); -- AA2D2
REG_WP: PH port map(W_ASSM(8),SET_W_REG,W_P); -- AA2D2
-- X_LATCH:
SET_X_REG <= (not INH_ROSAR_SET and P1) or MACH_RST_SET_LCH_DLY; -- AA2D2
REG_X: PHV8 port map(X_ASSM(0 to 7),SET_X_REG,sWX(5 to 12)); -- AA2D3
REG_XP: PH port map(X_ASSM(8),SET_X_REG,X_P); -- AA2D3
WX <= sWX;
-- Backup ROSAR regs
SET_F <= (MPX_SHARE_PULSE and T4) or MACH_RST_4; -- AA3G3
FWX_LCH: PHV13 port map(sWX,SET_F,FWX); -- AA3H2,AA3H3
FWP_LCH: PH port map(W_P,SET_F,FW_P); -- AA3H2
FXP_LCH: PH port map(X_P,SET_F,FX_P); -- AA3H3
SET_G <= (SX_CHAIN_PULSE and T4) or MACH_RST_5; -- AA3K2
GWX_LCH: PHV13 port map(sWX,SET_G,GWX); -- AA2K5,AA2L2
GWP_LCH: PH port map(W_P,SET_G,GW_P); -- AA2K5
GXP_LCH: PH port map(X_P,SET_G,GX_P); -- AA2L2
-- CROS triggering
-- This is what the ALD shows:
-- CROS_GO_PULSE <= not (T2 and CHK_OR_DIAG_STOP_SW and ALLOW_PC_SALS and (sSAL_PC or sCTRL_REG_CHK)); -- AA2E7,AA2E2,AA2C2
-- This is what I think it should be
CROS_GO_PULSE <= T2 and not (CHK_OR_DIAG_STOP_SW and ALLOW_PC_SALS and (sSAL_PC or sCTRL_REG_CHK)); -- AA2E7,AA2E2,AA2C2 ??
CROS_STROBE <= T3; -- AA3L6
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-01C-D.vhd
-- Creation Date:
-- Description:
-- CCROS storage, SALS (Sense Amplifier Latches), CTRL register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE std.textio.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY CCROS IS
port
(
-- Inputs
WX : IN STD_LOGIC_VECTOR(0 to 12); -- 01B
MACH_RST_SW : IN STD_LOGIC; -- 03D
MANUAL_STORE : IN STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
COMPUTE : IN STD_LOGIC; -- 04D
MACH_RST_MPX : IN STD_LOGIC; -- 08C
CROS_STROBE : IN STD_LOGIC; -- 01B
CROS_GO_PULSE : IN STD_LOGIC; -- 01B
-- Outputs
SALS: OUT SALS_Bus;
CTRL : OUT CTRL_REG;
CTRL_REG_RST : OUT STD_LOGIC; -- 07B
CK_SAL_P_BIT_TO_MPX : OUT STD_LOGIC; -- ?
-- Clocks
T1 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END CCROS;
ARCHITECTURE FMD OF CCROS IS
subtype CCROS_Address_Type is integer range 0 to 4095;
subtype CCROS_Word_Type is std_logic_vector(0 to 54);
type CCROS_Type is array(CCROS_Address_Type) of CCROS_Word_Type;
impure function readCCROS return CCROS_Type is
variable fileCCROS : CCROS_Type := (others => (others => '0'));
variable Cline : line;
variable addr : natural;
variable CCROSaddr : CCROS_Address_Type;
file CCROS_lines : text open read_mode is "ccros20100715.txt";
function fmHex(c : in character) return integer is
begin
if (c>='0') and (c<='9') then return character'pos(c)-character'pos('0');
elsif (c>='A') and (c<='F') then return character'pos(c)-character'pos('A')+10;
elsif (c>='a') and (c<='f') then return character'pos(c)-character'pos('a')+10;
else
report "Invalid hex address:" & c severity note;
return 0;
end if;
end;
function fmBin(c : in character) return STD_LOGIC is
begin
if c='0' then return '0';
elsif c='1' then return '1';
elsif c='?' then return '0';
else
report "Invalid bit:" & c severity note;
return '0';
end if;
end;
-- parity() function returns 1 if the vector has even parity
function parity(v : STD_LOGIC_VECTOR) return STD_LOGIC is
variable p : STD_LOGIC;
begin
p := '1';
for i in v'range loop
p := p xor v(i);
end loop;
return p;
end;
function toString(v : STD_LOGIC_VECTOR) return string is
variable s : string(1 to 55);
begin
for i in v'range loop
if v(i)='1' then s(i+1):='1';
else s(i+1):='0'; end if;
end loop;
return s;
end;
variable char : character;
variable field : integer;
variable newC : CCROS_Word_Type;
variable version : string(1 to 3);
variable eol : boolean;
variable cstr3 : string(1 to 3);
variable cstr8 : string(1 to 8);
variable cstr55 : string(1 to 55);
begin
for i in 1 to 8192 loop
exit when endfile(CCROS_lines);
readline(CCROS_lines,Cline);
exit when endfile(CCROS_lines);
-- 1-3 = address (hex)
-- 5-6 = CN hex (ignore 2 lower bits)
-- 8-11 = CH
-- 13-16 = CL
-- 18-20 = CM
-- 22-23 = CU
-- 25-28 = CA
-- 30-31 = CB
-- 33-36 = CK
-- 38-41 = CD
-- 43-45 = CF
-- 47-48 = CG
-- 50-51 = CV
-- 53-55 = CC
-- 57-60 = CS
-- 62 = AA
-- 64 = AS
-- 66 = AK
-- 68 = PK
-- File layout:
-- #AAA CN CH CL CM CU CA CB CK CD CF CG CV CC CS AAASAKPK
read(Cline,char);
if char='#' then next; end if;
addr := fmHex(char);
cstr3(1) := char;
read(Cline,char); addr := addr*16+fmhex(char);
cstr3(2) := char;
read(Cline,char); addr := addr*16+fmhex(char);
cstr3(3) := char;
CCROSaddr := CCROS_Address_Type(addr);
-- report "Addr: " & cstr3 severity note;
-- PN (0) omitted for now
-- CN
-- read(Cline,char); -- 4
read(Cline,char); field := fmHex(char);
read(Cline,char); field := field*16+fmhex(char);
field := field / 4;
newC(1 to 6) := conv_std_logic_vector(field,6);
-- PS (7) and PA (8) omitted for now
-- CH
-- read(Cline,char);
read(Cline,char); newc( 9) := fmBin(char);
read(Cline,char); newc(10) := fmBin(char);
read(Cline,char); newc(11) := fmBin(char);
read(Cline,char); newc(12) := fmBin(char);
-- CL
-- read(Cline,char);
read(Cline,char); newc(13) := fmBin(char);
read(Cline,char); newc(14) := fmBin(char);
read(Cline,char); newc(15) := fmBin(char);
read(Cline,char); newc(16) := fmBin(char);
-- CM
-- read(Cline,char);
read(Cline,char); newc(17) := fmBin(char);
read(Cline,char); newc(18) := fmBin(char);
read(Cline,char); newc(19) := fmBin(char);
-- CU
-- read(Cline,char);
read(Cline,char); newc(20) := fmBin(char);
read(Cline,char); newc(21) := fmBin(char);
-- CA
-- read(Cline,char);
read(Cline,char); newc(22) := fmBin(char);
read(Cline,char); newc(23) := fmBin(char);
read(Cline,char); newc(24) := fmBin(char);
read(Cline,char); newc(25) := fmBin(char);
-- CB
-- read(Cline,char);
read(Cline,char); newc(26) := fmBin(char);
read(Cline,char); newc(27) := fmBin(char);
-- CK
-- read(Cline,char);
read(Cline,char); newc(28) := fmBin(char);
read(Cline,char); newc(29) := fmBin(char);
read(Cline,char); newc(30) := fmBin(char);
read(Cline,char); newc(31) := fmBin(char);
-- PK (32) and PC (33) omitted for now
-- CD
-- read(Cline,char);
read(Cline,char); newc(34) := fmBin(char);
read(Cline,char); newc(35) := fmBin(char);
read(Cline,char); newc(36) := fmBin(char);
read(Cline,char); newc(37) := fmBin(char);
-- CF
-- read(Cline,char);
read(Cline,char); newc(38) := fmBin(char);
read(Cline,char); newc(39) := fmBin(char);
read(Cline,char); newc(40) := fmBin(char);
-- CG
-- read(Cline,char);
read(Cline,char); newc(41) := fmBin(char);
read(Cline,char); newc(42) := fmBin(char);
-- CV
-- read(Cline,char);
read(Cline,char); newc(43) := fmBin(char);
read(Cline,char); newc(44) := fmBin(char);
-- CC
-- read(Cline,char);
read(Cline,char); newc(45) := fmBin(char);
read(Cline,char); newc(46) := fmBin(char);
read(Cline,char); newc(47) := fmBin(char);
-- CS
-- read(Cline,char);
read(Cline,char); newc(48) := fmBin(char);
read(Cline,char); newc(49) := fmBin(char);
read(Cline,char); newc(50) := fmBin(char);
read(Cline,char); newc(51) := fmBin(char);
-- AA
-- read(Cline,char);
read(Cline,char); newc(52) := fmBin(char);
-- AS
-- read(Cline,char);
read(Cline,char); newc(53) := fmBin(char);
-- AK
-- read(Cline,char);
read(Cline,char); newc(54) := fmBin(char);
-- PK
-- read(Cline,char);
read(Cline,char); newc(32) := fmBin(char);
-- Now fill in PN,PA,PS,PC
newc(0) := parity(newc(1 to 6)); -- PN = CN
newc(8) := parity(CONV_STD_LOGIC_VECTOR(CCROSAddr,13)); -- PA = ADDR
-- if (newc(13 to 16)="0010") then
-- newc(32) := parity(newc(22 to 25)); -- PK = CA
-- else
-- newc(32) := parity(newc(28 to 31)); -- PK = CK
-- end if;
newc(7) := parity(newc(8 to 32) & newc(52) & newc(54)); -- PS = PA CH CL CM CU CA CB CK PK AA AK
newc(33) := parity(newc(34 to 51) & newc(53)); -- PC = CD CF CG CV CC CS AS
-- Bodge to generate incorrect parity for some locations
if addr=unsigned'(x"BA0") then -- BA0 has parity change "7" = PS PA PC
-- newc(7) := not newc(7); -- Already doing PA so no need to flip PS
newc(8) := not newc(8); -- PA
newc(33) := not newc(33); -- PC
end if;
if addr=unsigned'(x"B60") then -- B60 has parity change "B" = PN PA PC
newc(0) := not newc(0); -- PN
newc(7) := not newc(7); -- Need to flip PS to keep it correct when PA is flipped
newc(8) := not newc(8); -- PA
newc(33) := not newc(33); -- PC
end if;
-- Skip over page/location
read(Cline,char);read(Cline,cstr8);
-- report "Loc: " & cstr8 severity note;
-- for i in newC'range loop
-- if newC(i)='1' then
-- report "1" severity note;
-- else
-- report "0" severity note;
-- end if;
-- end loop;
-- See if there is a version
read(Cline,char,eol);
read(Cline,version,eol);
if char='-' then
-- report "Version: "&version severity note;
else
version := " ";
end if;
-- Check for acceptable versions
-- 000/Blank = Basic
-- 004 = 64k
-- 005 = 224UCWs
-- 006 = Storage Protect
-- 007 = Decimal Option
-- 010 = 1050 Console
-- 014 = Selector Channel #1
-- 025 = 50Hz timer
-- A20 = 64k + Storage Protect
-- Omitted:
-- 015 = Selector Channel 2
-- 031 = ??
-- 906 = Storage Protect Diagnostic
-- 914 = Selector Channel Diagnostic
-- 994 = ??
-- 995 = Local Storage Dump
-- 996 = Storage Diagnostic
-- 997 = Mpx Diagnostic
if version=" " or version="000" or version="004" or version="005" or version="006" or
version="007" or version="010" or version="014" or version="025" or version="A20" then
if fileCCROS(CCROSaddr) = (newC'range => '0') then
fileCCROS(CCROSaddr) := newC;
else
report "Duplicate CCROS " & integer'image(CCROSAddr) & " Ver " & version severity note;
end if;
else
report "CCROS " & integer'image(CCROSAddr) & " Ver " & version & " skipped" severity note;
end if;
-- report "CCROS " & integer'image(CCROSAddr) & ": " & toString(newC);
end loop;
return fileCCROS;
end;
signal SALS_Word : STD_LOGIC_VECTOR(0 to 54) := (others=>'1');
alias SALS_PN : STD_LOGIC is SALS_Word(0);
alias SALS_CN : STD_LOGIC_VECTOR(0 to 5) is SALS_Word(1 to 6);
alias SALS_PS : STD_LOGIC is SALS_Word(7);
alias SALS_PA : STD_LOGIC is SALS_Word(8);
alias SALS_CH : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(9 to 12);
alias SALS_CL : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(13 to 16);
alias SALS_CM : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(17 to 19);
alias SALS_CU : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(20 to 21);
alias SALS_CA : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(22 to 25);
alias SALS_CB : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(26 to 27);
alias SALS_CK : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(28 to 31);
alias SALS_PK : STD_LOGIC is SALS_Word(32);
alias SALS_PC : STD_LOGIC is SALS_Word(33);
alias SALS_CD : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(34 to 37);
alias SALS_CF : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(38 to 40);
alias SALS_CG : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(41 to 42);
alias SALS_CV : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(43 to 44);
alias SALS_CC : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(45 to 47);
alias SALS_CS : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(48 to 51);
alias SALS_AA : STD_LOGIC is SALS_Word(52);
alias SALS_SA : STD_LOGIC is SALS_Word(53);
alias SALS_AK : STD_LOGIC is SALS_Word(54);
constant CCROS : CCROS_Type := readCCROS;
signal AUX_CTRL_REG_RST : STD_LOGIC;
signal SET_CTRL_REG : STD_LOGIC;
signal sCTRL : CTRL_REG;
signal sCTRL_REG_RST : STD_LOGIC;
signal CD_LCH_Set,CD_LCH_Reset,CS_LCH_Set,CS_LCH_Reset : STD_LOGIC_VECTOR(0 to 3);
signal STRAIGHT_LCH_Set,CROSSED_LCH_Set,CC2_LCH_Set,CC2_LCH_Reset,GTAHI_LCH_Set,GTAHI_LCH_Reset,
GTALO_LCH_Set,GTALO_LCH_Reset,COMPCY_LCH_Set,COMPCY_LCH_Reset,CG0_Set,CG1_Set,CG_Reset : STD_LOGIC;
signal CV_LCH_Set,CV_LCH_Reset,CC01_LCH_Set,CC01_LCH_Reset : STD_LOGIC_VECTOR(0 to 1);
signal CROS_STROBE_DELAY : STD_LOGIC_VECTOR(1 to 5) := "00000";
BEGIN
-- Page 5-01C
sCTRL_REG_RST <= MACH_RST_SW or MANUAL_STORE or ANY_PRIORITY_LCH;
CTRL_REG_RST <= sCTRL_REG_RST;
AUX_CTRL_REG_RST <= T1 or sCTRL_REG_RST;
SET_CTRL_REG <= not ANY_PRIORITY_LCH and P1;
CD_LCH_Set <= SALS_CD and (0 to 3 => SET_CTRL_REG);
CD_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST);
CD_LCH: FLVL port map(CD_LCH_Set,CD_LCH_Reset,sCTRL.CTRL_CD); -- AA2C6
STRAIGHT_LCH_Set <= sCTRL_REG_RST or (SET_CTRL_REG and not SALS_CF(0));
STRAIGHT_LCH: FLL port map(STRAIGHT_LCH_Set, T1, sCTRL.STRAIGHT);
CROSSED_LCH_Set <= SET_CTRL_REG and SALS_CF(0);
CROSSED_LCH: FLL port map(CROSSED_LCH_Set, AUX_CTRL_REG_RST, sCTRL.CROSSED);
CC2_LCH_Set <= SET_CTRL_REG and SALS_CC(2);
CC2_LCH_Reset <= T1 or sCTRL_REG_RST;
CC2_LCH: FLL port map(CC2_LCH_Set, CC2_LCH_Reset, sCTRL.CTRL_CC(2));
GTAHI_LCH_Set <= SET_CTRL_REG and SALS_CF(1);
GTAHI_LCH_Reset <= T1 or sCTRL_REG_RST;
GTAHI_LCH: FLL port map(GTAHI_LCH_Set, GTAHI_LCH_Reset, sCTRL.GT_A_REG_HI);
GTALO_LCH_Set <= SET_CTRL_REG and SALS_CF(2);
GTALO_LCH_Reset <= T1 or sCTRL_REG_RST;
GTALO_LCH: FLL port map(GTALO_LCH_Set, GTALO_LCH_Reset, sCTRL.GT_A_REG_LO);
COMPCY_LCH_Set <= SET_CTRL_REG and COMPUTE;
COMPCY_LCH_Reset <= T1 or sCTRL_REG_RST;
COMPCY_LCH: FLL port map(COMPCY_LCH_Set, COMPCY_LCH_Reset, sCTRL.COMPUTE_CY_LCH);
CG0_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(0));
CG_Reset <= T1 or (MACH_RST_SW or ANY_PRIORITY_LCH); -- ?? Required to prevent simultaneous Set & Reset of CG by MANUAL_STORE
CG0: FLL port map(CG0_Set, CG_Reset, sCTRL.CTRL_CG(0)); sCTRL.GT_B_REG_HI <= sCTRL.CTRL_CG(0);
CG1_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(1));
CG1: FLL port map(CG1_Set, CG_Reset, sCTRL.CTRL_CG(1)); sCTRL.GT_B_REG_LO <= sCTRL.CTRL_CG(1);
CV_LCH_Set <= SALS_CV and (0 to 1 => SET_CTRL_REG);
CV_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST);
CV_LCH: FLVL port map(CV_LCH_Set,CV_LCH_Reset,sCTRL.CTRL_CV); -- AA2D6
CC01_LCH_Set <= SALS_CC(0 to 1) and (0 to 1 => SET_CTRL_REG);
CC01_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST);
CC01_LCH: FLVL port map(CC01_LCH_Set,CC01_LCH_Reset,sCTRL.CTRL_CC(0 to 1)); -- AA2D6
CS_LCH_Set <= SALS_CS and (0 to 3 => SET_CTRL_REG);
CS_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST);
CS_LCH: FLVL port map(CS_LCH_Set,CS_LCH_Reset,sCTRL.CTRL_CS); -- AA2D7
CTRL <= sCTRL;
CK_SAL_P_BIT_TO_MPX <= SALS_PK and not MACH_RST_MPX;
-- Page 5-01D
-- CCROS microcode storage
-- Start of read is CROS_GO_PULSE
-- End of read is CCROS_STROBE
-- Should use falling edge of CCROS_STROBE to gate data from CCROS into SALS (actually happens earlier)
CCROS_RESET_SET: process (Clk,CROS_STROBE,CROS_GO_PULSE,WX)
begin
-- Reset SALS when CROS_GO_PULSE goes Low
-- Set SALS 100ns after CROS_STROBE goes High (start of T3)
-- ROAR should have been set during T1 so we have a 1.5 minor cycle (~280ns) access time
if (Clk'Event and Clk='1') then
-- if (CROS_STROBE='1' and CROS_STROBE_DELAY="10000") then
--SALS_Word <= (others => '0');
-- else
if (CROS_STROBE='1' and CROS_STROBE_DELAY="11110") then
SALS_Word <= CCROS(CCROS_Address_Type(conv_integer(unsigned(WX(1 to 12)))));
-- end if;
end if;
CROS_STROBE_DELAY <= CROS_STROBE & CROS_STROBE_DELAY(1 to 4);
end if;
end process;
SALS.SALS_PN <= SALS_PN;
SALS.SALS_CN <= SALS_CN;
SALS.SALS_PS <= SALS_PS;
SALS.SALS_PA <= SALS_PA;
SALS.SALS_CH <= SALS_CH;
SALS.SALS_CL <= SALS_CL;
SALS.SALS_CM <= SALS_CM;
SALS.SALS_CU <= SALS_CU;
SALS.SALS_CA <= SALS_CA;
SALS.SALS_CB <= SALS_CB;
SALS.SALS_CK <= SALS_CK;
SALS.SALS_PK <= SALS_PK;
SALS.SALS_PC <= SALS_PC;
SALS.SALS_CD <= SALS_CD;
SALS.SALS_CF <= SALS_CF;
SALS.SALS_CG <= SALS_CG;
SALS.SALS_CV <= SALS_CV;
SALS.SALS_CC <= SALS_CC;
SALS.SALS_CS <= SALS_CS;
SALS.SALS_AA <= SALS_AA;
SALS.SALS_SA <= SALS_SA;
SALS.SALS_AK <= SALS_AK;
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-02A-B.vhd
-- Creation Date:
-- Description:
-- X6,X7 assembly, ASCII latch, X6,X7 backup (5-02A), WX reg gating (5-02B)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY X6X7 IS
port
(
SALS : IN SALS_Bus; -- 01C
DECIMAL : IN STD_LOGIC; -- 06B
CONNECT : IN STD_LOGIC; -- 06B
N_CTRL_LM : IN STD_LOGIC; -- 06B
CTRL_N : IN STD_LOGIC; -- 06B
R_REG_0_BIT : IN STD_LOGIC; -- 06C
V67_00_OR_GM_WM : IN STD_LOGIC; -- 05A
STATUS_IN_LCHD : IN STD_LOGIC; -- 06A
OPNL_IN_LCHD : IN STD_LOGIC; -- 06A
CARRY_0_LCHD : IN STD_LOGIC; -- 06A
S_REG_1_OR_R_REG_2 : IN STD_LOGIC; -- 05A
S : IN STD_LOGIC_VECTOR(0 to 7); -- 07B
G : IN STD_LOGIC_VECTOR(0 to 7); -- 05C
TIMER_UPDATE : IN STD_LOGIC; -- 04C
EXTERNAL_INT : IN STD_LOGIC; -- 04C
MPX_INTERRUPT : IN STD_LOGIC; -- 08C
SX1_INTERRUPT : IN STD_LOGIC; -- 12D
SX2_INTERRUPT : IN STD_LOGIC; -- 14D
-- HSMPX : IN STD_LOGIC; -- XXXXX
I_WRAPPED_CPU : IN STD_LOGIC; -- 03B
TIMER_UPDATE_OR_EXT_INT : IN STD_LOGIC; -- 04C
U_WRAPPED_MPX : IN STD_LOGIC; -- 03B
H_REG_6_BIT : IN STD_LOGIC; -- 04C
ADDR_IN_LCHD : IN STD_LOGIC; -- 06A
SERV_IN_LCHD : IN STD_LOGIC; -- 06A
R_REG_VAL_DEC_DIG : IN STD_LOGIC; -- 05A
N1BC_OR_R1 : IN STD_LOGIC; -- 05A
Z_BUS_0 : IN STD_LOGIC; -- 06B
G_REG_1_OR_R_REG_3 : IN STD_LOGIC; -- 05A
GT_BU_ROSAR_TO_WX_REG : IN STD_LOGIC; -- 01B
H_REG_5_PWR : IN STD_LOGIC; -- 04C
MPX_SHARE_PULSE : IN STD_LOGIC; -- 03A
SX_CHAIN_PULSE : IN STD_LOGIC; -- 03A
MACH_RST_SW : IN STD_LOGIC; -- 03D
R_REG_4_BIT : IN STD_LOGIC; -- 06C
ANY_PRIORITY_PULSE : IN STD_LOGIC; -- 03A
-- Outputs
XOR_OR_OR : OUT STD_LOGIC; -- 03A,04A
INTERRUPT : OUT STD_LOGIC; -- 01B
GT_GWX_TO_WX_REG : OUT STD_LOGIC; -- 01B
GT_FWX_TO_WX_REG : OUT STD_LOGIC; -- 01B
USE_CA_BASIC_DECODER : OUT STD_LOGIC; -- 02B,01A,03C,04C,05C,07A,07C,10C
MPX_ROS_LCH : OUT STD_LOGIC; -- 08C
X6 : OUT STD_LOGIC;
X7 : OUT STD_LOGIC;
USE_ALT_CA_DECODER : OUT STD_LOGIC; -- 07C,04C,10C,07A,11C
GT_CA_TO_W_REG : OUT STD_LOGIC; -- 01B,07A
GT_UV_TO_WX_REG : OUT STD_LOGIC; -- 01B
DIAG_LATCH_RST : OUT STD_LOGIC; -- NEW
-- Debug
DEBUG : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END X6X7;
ARCHITECTURE FMD OF X6X7 IS
signal TEST_ASCII : STD_LOGIC;
signal TEST_INTRP : STD_LOGIC;
signal TEST_WRAP : STD_LOGIC;
signal GT_ASCII_LCH : STD_LOGIC;
signal GT_MPX_LCH : STD_LOGIC; -- Output of AA3E3
signal GT_SX_LCH : STD_LOGIC; -- Output of AA3L6
signal X6_MUX,X7_MUX : STD_LOGIC;
signal CA_TO_X7_DECO : STD_LOGIC;
signal X6_BRANCH,X7_BRANCH : STD_LOGIC;
signal SX_CH_ROAR_RESTORE : STD_LOGIC;
signal MPX_CH_ROAR_RESTORE : STD_LOGIC;
signal RESTORE_0 : STD_LOGIC; -- Output of AA3K5,FL0
signal ASCII_LCH : STD_LOGIC;
signal MPX_CH_X6,MPX_CH_X7 : STD_LOGIC;
signal SX_CH_X6,SX_CH_X7 : STD_LOGIC;
signal X6_DATA,X7_DATA : STD_LOGIC;
signal STORED_X6,STORED_X7 : STD_LOGIC;
signal sXOR_OR_OR : STD_LOGIC;
signal sINTERRUPT : STD_LOGIC;
signal sGT_GWX_TO_WX_REG : STD_LOGIC;
signal sGT_FWX_TO_WX_REG : STD_LOGIC;
signal sUSE_CA_BASIC_DECODER : STD_LOGIC;
signal sMPX_ROS_LCH : STD_LOGIC;
signal REST0_LCH_Set,REST0_LCH_Reset,SXREST_LCH_Set,SXREST_LCH_Reset,
MPXROS_LCH_Reset,MPXROS_LCH_Set,MPXREST_LCH_Set,MPXREST_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-02A
TEST_ASCII <= '1' when SALS.SALS_CK="1001" and SALS.SALS_AK='1' else '0'; -- AB3E7
TEST_INTRP <= '1' when SALS.SALS_CK="1010" and SALS.SALS_AK='1' else '0'; -- AB3E7
TEST_WRAP <= '1' when SALS.SALS_CK="0011" and SALS.SALS_AK='1' else '0'; -- AB3E6
DIAG_LATCH_RST <= '1' when SALS.SALS_CK="0000" and SALS.SALS_AK='1' and T1='1' else '0'; -- NEW!
sXOR_OR_OR <= DECIMAL and CONNECT and N_CTRL_LM; -- AB3D2
XOR_OR_OR <= sXOR_OR_OR;
GT_ASCII_LCH <= sXOR_OR_OR and CTRL_N and T2; -- AB3D2
DEBUG <= ASCII_LCH;
-- ?? Debug remove other interrupt sources
-- sINTERRUPT <= TIMER_UPDATE or EXTERNAL_INT or MPX_INTERRUPT or SX1_INTERRUPT or SX2_INTERRUPT; -- AA3K4
sINTERRUPT <= EXTERNAL_INT;
INTERRUPT <= sINTERRUPT;
with (SALS.SALS_CH) select X6_MUX <= -- AA3G5
'1' when "0001",
R_REG_0_BIT when "0010",
V67_00_OR_GM_WM when "0011",
STATUS_IN_LCHD when "0100",
OPNL_IN_LCHD when "0101",
CARRY_0_LCHD when "0110",
S(0) when "0111",
S_REG_1_OR_R_REG_2 when "1000",
S(2) when "1001",
S(4) when "1010",
S(6) when "1011",
G(0) when "1100",
G(2) when "1101",
G(4) when "1110",
G(6) when "1111",
'0' when others; -- 0000
with (SALS.SALS_CL) select X7_MUX <= -- AA3H5
'1' when "0001",
'1' when "0010", -- CL=0010 is CA>W ?? Needed otherwise CA>W always forces X7 to 0 ??
ADDR_IN_LCHD when "0011",
SERV_IN_LCHD when "0100",
R_REG_VAL_DEC_DIG when "0101",
N1BC_OR_R1 when "0110",
Z_BUS_0 when "0111",
G(7) when "1000",
S(3) when "1001",
S(5) when "1010",
S(7) when "1011",
G_REG_1_OR_R_REG_3 when "1100",
G(3) when "1101",
G(5) when "1110",
sINTERRUPT when "1111",
'0' when others; -- 0000
X6_BRANCH <= (not ASCII_LCH or not TEST_ASCII) and -- AA3K3
(not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3
(not SX2_INTERRUPT or SX1_INTERRUPT or not TEST_INTRP) and -- AA3K4
(not I_WRAPPED_CPU or not TEST_WRAP) and -- AA3K3
X6_MUX;
X7_BRANCH <= (not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3
(not SX1_INTERRUPT or not TEST_INTRP) and -- AA3B7
(not TEST_WRAP or not U_WRAPPED_MPX or not H_REG_6_BIT) and -- AA3J5
X7_MUX ;
-- and CA_TO_X7_DECO; ?? Removed as it forced X7 to 0 on CA>W ??
sGT_GWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and H_REG_5_PWR; -- AA3L5
GT_GWX_TO_WX_REG <= sGT_GWX_TO_WX_REG;
sGT_FWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and not H_REG_5_PWR; -- AA3C2
GT_FWX_TO_WX_REG <= sGT_FWX_TO_WX_REG;
sUSE_CA_BASIC_DECODER <= not SALS.SALS_AA;
USE_CA_BASIC_DECODER <= sUSE_CA_BASIC_DECODER;
REST0_LCH_Set <= T2 and sGT_GWX_TO_WX_REG;
REST0_LCH_Reset <= MACH_RST_SW or T1;
REST0_LCH: FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0
SXREST_LCH_Set <= T4 and RESTORE_0;
SXREST_LCH_Reset <= MACH_RST_SW or T3;
SXREST_LCH: FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1
MPXROS_LCH_Set <= T2 and sGT_FWX_TO_WX_REG;
MPXROS_LCH_Reset <= MACH_RST_SW or T1;
MPXROS_LCH: FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2
MPX_ROS_LCH <= sMPX_ROS_LCH;
MPXREST_LCH_Set <= T4 and sMPX_ROS_LCH;
MPXREST_LCH_Reset <= MACH_RST_SW or T3;
MPXREST_LCH: FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3
X6_DATA <= X6_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
X7_DATA <= X7_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
GT_MPX_LCH <= (MPX_SHARE_PULSE and T1) or MACH_RST_SW; -- AA3L4,AA3E3
GT_SX_LCH <= (SX_CHAIN_PULSE and T1) or MACH_RST_SW; -- AA3F3,AA3L6
-- ASCII latch plus X6,X7 storage for
ASC_LCH: PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3
M7_LCH: PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3
S7_LCH: PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3
M6_LCH: PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3
S6_LCH: PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3
STORED_X6 <= (SX_CH_ROAR_RESTORE and SX_CH_X6) or (MPX_CH_ROAR_RESTORE and MPX_CH_X6); -- AA3K6
STORED_X7 <= (SX_CH_ROAR_RESTORE and SX_CH_X7) or (MPX_CH_ROAR_RESTORE and MPX_CH_X7); -- AA3K6
X6 <= X6_DATA or STORED_X6; -- Wire-AND of negated signals
X7 <= X7_DATA or STORED_X7; -- Wire-AND of negated signals
-- Page 5-02B
USE_ALT_CA_DECODER <= not sUSE_CA_BASIC_DECODER and not ANY_PRIORITY_PULSE; -- AB2F7 ??
CA_TO_X7_DECO <= '0' when SALS.SALS_CL="0010" else '1'; -- AA3H5
GT_CA_TO_W_REG <= not CA_TO_X7_DECO and not ANY_PRIORITY_PULSE; -- AA3L4,AA3G4
GT_UV_TO_WX_REG <= '1' when SALS.SALS_CK="0001" and SALS.SALS_AK='1' and ANY_PRIORITY_PULSE='0' else '0'; -- AB3E6,AB3B3
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03A.vhd
-- Creation Date:
-- Description:
-- Priority (microcode interruptions)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY Priority IS
port
(
-- Inputs
RECYCLE_RST : IN STD_LOGIC; -- 04A
S_REG_1_BIT : IN STD_LOGIC; -- 07B
SALS_CDREG : IN STD_LOGIC_VECTOR(0 to 3); -- 01A?
MACH_RST_SW : IN STD_LOGIC; -- 03D
DATA_READY_1 : IN STD_LOGIC; -- 05D
DATA_READY_2 : IN STD_LOGIC; -- ???
MEM_WRAP_REQ : IN STD_LOGIC; -- 03B
ALLOW_PROTECT : IN STD_LOGIC; -- 06C
PROT_LOC_CPU_OR_MPX : IN STD_LOGIC; -- 08B
READ_CALL : IN STD_LOGIC; -- 05D
XOR_OR_OR : IN STD_LOGIC; -- 02A
CTRL_N : IN STD_LOGIC; -- 06B
STOP_REQ : IN STD_LOGIC; -- 03C
SUPPR_A_REG_CHK : IN STD_LOGIC; -- 07A
H_REG_5_PWR : IN STD_LOGIC; -- 04C
SEL_ROS_REQ : IN STD_LOGIC; -- 12C
FT_3_MPX_SHARE_REQ : IN STD_LOGIC; -- 08D
H_REG_6 : IN STD_LOGIC; -- 04C
P_8F_DETECTED : IN STD_LOGIC; -- 06C
LOAD_IND : IN STD_LOGIC; -- 03C
FORCE_IJ_REQ : IN STD_LOGIC; -- 04A
FIRST_MACH_CHK_REQ : IN STD_LOGIC; -- 07A
MACH_RST_6 : IN STD_LOGIC; -- 03D
ALLOW_WRITE : IN STD_LOGIC; -- 03D
GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04A
DIAGNOSTIC_SW : IN STD_LOGIC; -- 04A
MACH_RST_LCH : IN STD_LOGIC; -- 04A
HARD_STOP_LCH : IN STD_LOGIC; -- 03C
R_REG_5 : IN STD_LOGIC; -- 06C
H : IN STD_LOGIC_VECTOR(0 to 7); -- 04C
FORCE_DEAD_CY_LCH : IN STD_LOGIC; -- 04A
-- Outputs
SUPPR_MACH_CHK_TRAP : OUT STD_LOGIC; -- 03C,04A,07A
ANY_PRIORITY_PULSE_2 : OUT STD_LOGIC; -- 03B,04D
ANY_PRIORITY_LCH : OUT STD_LOGIC; -- 04A,07A
S_REG_1_DLYD : OUT STD_LOGIC; -- 03C
GT_SW_TO_WX_LCH : OUT STD_LOGIC; -- 04A
DATA_READY : OUT STD_LOGIC; -- 06C
MEM_PROTECT_REQ : OUT STD_LOGIC; -- 07A
HZ_DEST_RST : OUT STD_LOGIC; -- 03C,04A
GT_SW_MACH_RST : OUT STD_LOGIC; -- 05A
GT_SWS_TO_WX_LCH : OUT STD_LOGIC; -- 01B
FORCE_IJ_REQ_LCH : OUT STD_LOGIC; -- 03C,04A,04B
SYS_RST_PRIORITY_LCH :OUT STD_LOGIC; -- 06B
MACH_CHK_PULSE : OUT STD_LOGIC; -- 03C,07A
FORCE_IJ_PULSE : OUT STD_LOGIC; -- 04A
SX_CHAIN_PULSE_1 : OUT STD_LOGIC; -- 12C
ANY_PRIORITY_PULSE : OUT STD_LOGIC; -- 01C,01B,02B,04C,11C
ANY_PRIORITY_PULSE_PWR : OUT STD_LOGIC; -- 01B,03C
PRIORITY_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 01B
PRIORITY_BUS_P : OUT STD_LOGIC;
-- Clocks
T1 : IN STD_LOGIC;
T3 : IN STD_LOGIC;
T4 : IN STD_LOGIC;
P4 : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END Priority;
ARCHITECTURE FMD OF Priority IS
-- Priority Bus assignments
signal sPRIORITY_BUS : STD_LOGIC_VECTOR(0 to 7);
alias STOP_PULSE : STD_LOGIC is sPRIORITY_BUS(0);
alias PROTECT_PULSE : STD_LOGIC is sPRIORITY_BUS(1);
alias WRAP_PULSE : STD_LOGIC is sPRIORITY_BUS(2);
alias MPX_SHARE_PULSE : STD_LOGIC is sPRIORITY_BUS(3);
alias SX_CHAIN_PULSE : STD_LOGIC is sPRIORITY_BUS(4);
alias PB_MACH_CHK_PULSE : STD_LOGIC is sPRIORITY_BUS(5);
alias IPL_PULSE : STD_LOGIC is sPRIORITY_BUS(6);
alias PB_FORCE_IJ_PULSE : STD_LOGIC is sPRIORITY_BUS(7);
signal CD0101 : STD_LOGIC;
signal PRIOR_RST_CTRL : STD_LOGIC;
signal PRIORITY_LCH : STD_LOGIC;
signal FIRST_MACH_CHK_LCH : STD_LOGIC;
signal LOAD_REQ_LCH : STD_LOGIC;
signal MEM_WRAP_REQ_LCH : STD_LOGIC;
signal MEM_PROTECT_LCH : STD_LOGIC;
signal STOP_REQ_LCH : STD_LOGIC;
signal SEL_CHAIN_REQ_LCH : STD_LOGIC;
signal MPX_SHARE_REQ_LCH : STD_LOGIC;
signal HI_PRIORITY : STD_LOGIC;
signal PRIORITY_STACK_IN, PRIORITY_STACK_OUT : STD_LOGIC_VECTOR(0 to 8);
signal sSUPPR_MACH_CHK_TRAP : STD_LOGIC;
signal sANY_PRIORITY_PULSE_2 : STD_LOGIC;
signal sANY_PRIORITY_LCH : STD_LOGIC;
signal sGT_SW_TO_WX_LCH : STD_LOGIC;
signal sDATA_READY : STD_LOGIC;
signal sMEM_PROTECT_REQ : STD_LOGIC;
signal sHZ_DEST_RST : STD_LOGIC;
signal sGT_SW_MACH_RST : STD_LOGIC;
signal sGT_SWS_TO_WX_LCH : STD_LOGIC;
signal sFORCE_IJ_REQ_LCH : STD_LOGIC;
signal sSYS_RST_PRIORITY_LCH : STD_LOGIC;
signal sMACH_CHK_PULSE : STD_LOGIC;
signal sFORCE_IJ_PULSE : STD_LOGIC;
signal sANY_PRIORITY_PULSE : STD_LOGIC;
signal sMPX_SHARE_PULSE : STD_LOGIC;
signal SUPPR_MACH_TRAP_L,PRIOR_RST_Reset,MEMP_LCH_Set,MEMP_LCH_Reset,PRI_LCH_Set,
PRI_LCH_Reset,PRISTK_LCH_Latch : STD_LOGIC;
BEGIN
-- Fig 5-03A
SUPPR_MACH_TRAP_L <= XOR_OR_OR and CTRL_N and T3;
SUPPR_MALF_TRAP_LCH: PHR port map(not R_REG_5,SUPPR_MACH_TRAP_L,RECYCLE_RST,sSUPPR_MACH_CHK_TRAP); -- AB3D2,AB3J2
-- ?? SUPPR_MACH_CHK_TRAP is from the output of the PH and not from its reset input ??
SUPPR_MACH_CHK_TRAP <= sSUPPR_MACH_CHK_TRAP; -- ??
-- SUPPR_MACH_CHK_TRAP <= not RECYCLE_RST; -- ??
sANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE; -- AB3D7
ANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE_2;
ANY_PRIORITY: PH port map(sANY_PRIORITY_PULSE_2,T1,sANY_PRIORITY_LCH); -- AB3D7,AB3J2
ANY_PRIORITY_LCH <= sANY_PRIORITY_LCH;
S1_DLYD: PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2
WX_SABC: PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2
GT_SW_TO_WX_LCH <= sGT_SW_TO_WX_LCH;
CD0101 <= '1' when SALS_CDREG="0101" else '0';
PRIOR_RST_Reset <= T4 or MACH_RST_SW;
PRIOR_RST_CTRL_PH: PHR port map(CD0101,PRIOR_RST_Reset,sANY_PRIORITY_PULSE,PRIOR_RST_CTRL); -- AB3J2
MEMP_LCH_Set <= sDATA_READY and ALLOW_PROTECT and PROT_LOC_CPU_OR_MPX;
MEMP_LCH_Reset <= READ_CALL or RECYCLE_RST;
STG_PROT_REQ: FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7
MEM_PROTECT_REQ <= sMEM_PROTECT_REQ;
sHZ_DEST_RST <= (P4 and sGT_SW_TO_WX_LCH) or (T3 and PRIOR_RST_CTRL); -- AB3K5,AB3J4
HZ_DEST_RST <= sHZ_DEST_RST;
sGT_SW_MACH_RST <= MACH_RST_6 or GT_SWS_TO_WX_PWR; -- AB3J3 ??
GT_SW_MACH_RST <= sGT_SW_MACH_RST;
sDATA_READY <= (DATA_READY_1 or DATA_READY_2) and not MEM_WRAP_REQ; -- AA1J6 AA1J4
DATA_READY <= sDATA_READY;
PRI_LCH_Set <= (T1 and DIAGNOSTIC_SW) or MACH_RST_LCH or (not HARD_STOP_LCH and T3 and sANY_PRIORITY_LCH);
PRI_LCH_Reset <= sHZ_DEST_RST or sGT_SW_MACH_RST;
PRIORITY: FLL port map(PRI_LCH_Set,PRI_LCH_Reset,PRIORITY_LCH); -- AB3J4,AB3L4
-- Priority stack register - all inputs are inverted AB3L2
PRIORITY_STACK_IN(0) <= GT_SWS_TO_WX_PWR;
PRIORITY_STACK_IN(1) <= FIRST_MACH_CHK_REQ;
PRIORITY_STACK_IN(2) <= P_8F_DETECTED or LOAD_IND;
PRIORITY_STACK_IN(3) <= FORCE_IJ_REQ;
PRIORITY_STACK_IN(4) <= MEM_WRAP_REQ;
PRIORITY_STACK_IN(5) <= sMEM_PROTECT_REQ;
PRIORITY_STACK_IN(6) <= STOP_REQ;
PRIORITY_STACK_IN(7) <= SUPPR_A_REG_CHK and not H_REG_5_PWR and SEL_ROS_REQ;
PRIORITY_STACK_IN(8) <= FT_3_MPX_SHARE_REQ and not H_REG_6 and not H_REG_5_PWR;
PRISTK_LCH_Latch <= MACH_RST_6 or (not ALLOW_WRITE and T3) or (P4 and GT_SWS_TO_WX_PWR);
PRISTK_LCH: PHV9 port map( D => PRIORITY_STACK_IN,
L => PRISTK_LCH_Latch,
Q => PRIORITY_STACK_OUT);
sGT_SWS_TO_WX_LCH <= PRIORITY_STACK_OUT(0);
GT_SWS_TO_WX_LCH <= sGT_SWS_TO_WX_LCH;
FIRST_MACH_CHK_LCH <= PRIORITY_STACK_OUT(1);
LOAD_REQ_LCH <= PRIORITY_STACK_OUT(2);
sFORCE_IJ_REQ_LCH <= PRIORITY_STACK_OUT(3);
FORCE_IJ_REQ_LCH <= sFORCE_IJ_REQ_LCH;
MEM_WRAP_REQ_LCH <= PRIORITY_STACK_OUT(4);
MEM_PROTECT_LCH <= PRIORITY_STACK_OUT(5);
STOP_REQ_LCH <= PRIORITY_STACK_OUT(6);
SEL_CHAIN_REQ_LCH <= PRIORITY_STACK_OUT(7);
MPX_SHARE_REQ_LCH <= PRIORITY_STACK_OUT(8);
-- HI priorities AB3K3
sMACH_CHK_PULSE <= not sSUPPR_MACH_CHK_TRAP and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and FIRST_MACH_CHK_LCH; -- ?? SUPPRESS_MACH_CHECK_TRAP should be inverted ??
MACH_CHK_PULSE <= sMACH_CHK_PULSE;
PB_MACH_CHK_PULSE <= sMACH_CHK_PULSE;
IPL_PULSE <= not sMACH_CHK_PULSE and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and LOAD_REQ_LCH and not H(0);
sFORCE_IJ_PULSE <= not IPL_PULSE and not sMACH_CHK_PULSE and not sGT_SWS_TO_WX_LCH and not PRIORITY_LCH and sFORCE_IJ_REQ_LCH and not H(4);
FORCE_IJ_PULSE <= sFORCE_IJ_PULSE;
PB_FORCE_IJ_PULSE <= sFORCE_IJ_PULSE;
WRAP_PULSE <= not sFORCE_IJ_PULSE and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and not IPL_PULSE and not sMACH_CHK_PULSE and MEM_WRAP_REQ_LCH and not H(2);
HI_PRIORITY <= FORCE_DEAD_CY_LCH or sGT_SWS_TO_WX_LCH or sMACH_CHK_PULSE or IPL_PULSE or sFORCE_IJ_PULSE or WRAP_PULSE; -- AB3K3
PRIORITY_BUS <= sPRIORITY_BUS;
-- LO priorities AB3K4
PROTECT_PULSE <= not HI_PRIORITY and not PRIORITY_LCH and MEM_PROTECT_LCH and not H(3);
STOP_PULSE <= not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and STOP_REQ_LCH;
SX_CHAIN_PULSE <= not STOP_PULSE and not PROTECT_PULSE and not HI_PRIORITY and not PRIORITY_LCH and SEL_CHAIN_REQ_LCH and not H(5);
SX_CHAIN_PULSE_1 <= SX_CHAIN_PULSE;
sMPX_SHARE_PULSE <= not SX_CHAIN_PULSE and not STOP_PULSE and not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and MPX_SHARE_REQ_LCH and not (H(5) or H(6)); -- ??
MPX_SHARE_PULSE <= sMPX_SHARE_PULSE;
SRP_LCH: FLL port map(MACH_RST_SW,T4,sSYS_RST_PRIORITY_LCH); -- AB3L3
SYS_RST_PRIORITY_LCH <= sSYS_RST_PRIORITY_LCH;
sANY_PRIORITY_PULSE <= sMPX_SHARE_PULSE or SX_CHAIN_PULSE or STOP_PULSE or PROTECT_PULSE or HI_PRIORITY or sSYS_RST_PRIORITY_LCH; -- AB3K4 ??
ANY_PRIORITY_PULSE <= sANY_PRIORITY_PULSE;
ANY_PRIORITY_PULSE_PWR <= sANY_PRIORITY_PULSE and not MACH_RST_SW; -- AB3D4
PRIORITY_BUS_P <= (sSYS_RST_PRIORITY_LCH or FORCE_DEAD_CY_LCH) and not GT_SWS_TO_WX_PWR; -- AB3H5 ??
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Storage Wrap (references >8k, >16k, >32k or wrapping over 64k)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY StorageWrap IS
port
(
-- Inputs
SALS : IN SALS_Bus;
CTRL : IN CTRL_REG;
ANY_PRIORITY_PULSE_2 : IN STD_LOGIC; -- 03A
H_REG_5_PWR,H_REG_6 : IN STD_LOGIC; -- 04C
NTRUE : IN STD_LOGIC; -- 06B
CARRY_0 : IN STD_LOGIC; -- 06B
COMPLEMENT : IN STD_LOGIC; -- 06B
GT_J_TO_N_REG,GT_V_TO_N_REG : IN STD_LOGIC; -- 05B
M012 : IN STD_LOGIC_VECTOR(0 to 2); -- 07B
RECYCLE_RST : IN STD_LOGIC; -- 04A
ALLOW_WRITE : IN STD_LOGIC; -- 03D
READ_CALL : IN STD_LOGIC; -- 05D
MAIN_STORAGE : IN STD_LOGIC; -- 04D
DATA_READY_1,DATA_READY_2 : IN STD_LOGIC; -- 05D
-- Outputs
GT_CK_DECO : OUT STD_LOGIC; -- 03C,04C
SEL_DATA_READY : OUT STD_LOGIC; -- 11C,13C,06C
MEM_WRAP_REQ : OUT STD_LOGIC; -- 03A
MEM_WRAP : OUT STD_LOGIC; -- 06C,11A,13A
I_WRAPPED_CPU,U_WRAPPED_MPX : OUT STD_LOGIC; -- 02A
-- Clocks
T1,T2,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END StorageWrap;
ARCHITECTURE FMD OF StorageWrap IS
signal RESTORE_WRAP,STORE_WRAP : STD_LOGIC;
signal U_WRAP_CPU,WRAP_BUFF : STD_LOGIC; -- PH outputs
signal NOT_MPX_OR_SEL,ALL_B_GATED,DEST_U,DEST_I_OR_RESTORE,CARRY_OUT_TRUE,CARRY_OUT_COMP,WRAP_TRUE,RESET_WRAP,CHECK_U_WRAP,CHECK_I_WRAP,CHECK_MPX_WRAP,CARRY_OUT : STD_LOGIC;
signal WRAP64 : STD_LOGIC;
signal sGT_CK_DECO : STD_LOGIC;
signal sMEM_WRAP_REQ : STD_LOGIC;
signal sMEM_WRAP : STD_LOGIC;
signal sI_WRAPPED_CPU, sU_WRAPPED_MPX : STD_LOGIC;
signal UWRAP_LCH_Reset,MWR_LCH_Set,MWR_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-03B
sGT_CK_DECO <= not ANY_PRIORITY_PULSE_2 and SALS.SALS_AK and P1; -- AB3B3,AB3F6 ??
GT_CK_DECO <= sGT_CK_DECO;
RESTORE_WRAP <= '1' when SALS.SALS_AK='1' and SALS.SALS_CK="0010" else '0'; -- AB3E6
STORE_WRAP <= '1' when not (sGT_CK_DECO='1' and SALS.SALS_CK="1100") else '0'; -- AB3E6,AB3L6
-- The Wrap latches remember whether a carry was associated with values stored in the U or I registers
-- If so that means we wrapped around from 64k to 0. The Wrap latches are only used if the UV/IJ value is
-- subsequently moved into MN
NOT_MPX_OR_SEL <= not(H_REG_5_PWR or H_REG_6); -- AB2L4
-- "ALL_B_GATED" means reset U wrap ??
-- "not ALL_B_GATED" means check U wrap ??
-- The FMD doesn't seem to show this way around, but microcode (e.g. QA781:C3) implies it
ALL_B_GATED <= not (not CTRL.GT_B_REG_HI or not CTRL.GT_B_REG_LO); -- AB2M3
DEST_U <= '1' when CTRL.CTRL_CD="1101" and T4='1' else '0'; -- AB2M3
DEST_I_OR_RESTORE <= '1' when (T4='1' and CTRL.CTRL_CD="1111") or (T1='1' and RESTORE_WRAP='1') else '0'; -- AB2M2 AB2M5
CARRY_OUT_TRUE <= not RESTORE_WRAP and NTRUE and CARRY_0; -- AB2M3 AB2L3
CARRY_OUT_COMP <= COMPLEMENT and not CARRY_0; -- AB2M3
WRAP_TRUE <= CARRY_OUT_TRUE or (RESTORE_WRAP and WRAP_BUFF); -- AB2L3
RESET_WRAP <= NOT_MPX_OR_SEL and ALL_B_GATED and DEST_U; -- AB2M3
CHECK_U_WRAP <= NOT_MPX_OR_SEL and DEST_U and not ALL_B_GATED; -- AB2L4
CHECK_I_WRAP <= NOT_MPX_OR_SEL and DEST_I_OR_RESTORE; -- AB2L4
CHECK_MPX_WRAP <= H_REG_6 and not H_REG_5_PWR; -- AB2L4
CARRY_OUT <= CARRY_OUT_TRUE or CARRY_OUT_COMP; -- AB2L3
UWRAP_LCH_Reset <= RECYCLE_RST or RESET_WRAP;
UWRAP_LCH: PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4
IWRAP_LCH: PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4
I_WRAPPED_CPU <= sI_WRAPPED_CPU;
UMPX_LCH: PH port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,Q=>sU_WRAPPED_MPX); -- AB2M4
U_WRAPPED_MPX <= sU_WRAPPED_MPX;
WBUFF_LCH: PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ??
WRAP64 <= (not H_REG_6 and GT_V_TO_N_REG and U_WRAP_CPU) or
(GT_J_TO_N_REG and not H_REG_6 and sI_WRAPPED_CPU) or
(GT_V_TO_N_REG and H_REG_6 and sU_WRAPPED_MPX);
-- Select the appropriate wrap condition based on storage size:
sMEM_WRAP <= M012(0) or M012(1) or M012(2); -- 8k
-- sMEM_WRAP <= M012(0) or M012(1); -- 16k
-- sMEM_WRAP <= M012(0); -- 32k
-- sMEM_WRAP <= WRAP64; -- 64k
MEM_WRAP <= sMEM_WRAP;
MWR_LCH_Set <= MAIN_STORAGE and T2 and (sMEM_WRAP and not ALLOW_WRITE); -- ?? ALLOW_WRITE use unclear - dot logic
MWR_LCH_Reset <= READ_CALL or RECYCLE_RST;
MWR_LCH: FLL port map(MWR_LCH_Set,MWR_LCH_Reset,sMEM_WRAP_REQ);
MEM_WRAP_REQ <= sMEM_WRAP_REQ;
SEL_DATA_READY <= (DATA_READY_1 or DATA_READY_2) and not sMEM_WRAP_REQ;
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Clock Start & Stop control
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ClockStartStop IS
port
(
-- Switches
SW_START,SW_LOAD,SW_SET_IC,SW_STOP : IN std_logic;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
SW_PWR_OFF : IN std_logic;
-- Other inputs
ALLOW_MAN_OPER : IN std_logic;
FT3_MPX_SHARE_REQ : IN std_logic;
M_CONV_OSC : IN std_logic;
SEL_ROS_REQ : IN std_logic;
MACH_RST_3 : IN std_logic;
CLOCK_ON : IN std_logic;
SAR_DLYD_STOP_SW : IN std_logic;
MATCH : IN std_logic;
SALS : IN SALS_Bus;
FORCE_IJ_REQ : IN std_logic;
MACH_START_RST : IN std_logic;
MACH_RST_SW : IN std_logic;
USE_BASIC_CA_DECO : IN std_logic;
S_REG_1_DLYD : IN std_logic;
INTERRUPT : IN std_logic;
END_OF_E_CY_LCH : IN std_logic;
ANY_PRIORITY_PULSE : IN std_logic;
FORCE_IJ_REQ_LCH : IN std_logic;
P_CONV_OSC : IN std_logic;
MAN_OPERATION : IN std_logic;
ALLOW_WRITE : IN std_logic;
MACH_CHK_PULSE : IN std_logic;
MACH_CHK_RST : IN std_logic;
HZ_DEST_RST : IN std_logic;
FIRST_MACH_CHK : IN std_logic;
CHK_OR_DIAG_STOP_SW : IN std_logic;
ANY_MACH_CHK : IN std_logic;
MATCH_LCH : IN std_logic;
EARLY_ROAR_STOP_SW : IN std_logic;
ALU_CHK : IN std_logic;
DIAGNOSTIC_SW : IN std_logic;
CS_DECODE_X001 : IN std_logic;
BASIC_CS0 : IN std_logic;
SUPPR_MACH_CHK_TRAP : IN std_logic;
Z_BUS_0 : IN std_logic;
SAR_STOP_SW : IN std_logic;
ROAR_STOP_SW : IN std_logic;
ANY_PRIORITY_PULSE_PWR : IN std_logic;
GT_CK_DECODE : IN std_logic;
SX1_SHARE_CYCLE,SX2_SHARE_CYCLE : IN std_logic;
SEL_T4 : IN std_logic;
SEL_SHARE_HOLD : IN std_logic;
SEL_CONV_OSC : IN std_logic;
SEL_BASIC_CLOCK_OFF : IN std_logic;
GT_J_REG_TO_A_BUS : IN std_logic;
M_CONV_OSC_2 : IN std_logic;
MPX_SHARE_REQ : IN std_logic;
SYSTEM_RESET_SW : IN std_logic;
-- Outputs
START_SW_RST : OUT std_logic;
E_CY_STOP_SAMPLE : OUT std_logic;
LOAD_KEY_SW : OUT std_logic;
LOAD_KEY_INLK : OUT std_logic;
SET_IC_ALLOWED : OUT std_logic;
INH_ROSAR_SET : OUT std_logic;
STOP_REQ : OUT std_logic;
ROS_SCAN : OUT std_logic;
ROS_CTRL_PROC_SW : OUT std_logic;
FT_4_LD_IND : OUT std_logic;
LOAD_REQ_LCH : OUT std_logic;
LOAD_IND : OUT std_logic;
RST_SEL_CHNL_DIAG_LCHS : OUT std_logic;
RST_LOAD : OUT std_logic;
CLOCK_START_LCH : OUT std_logic;
PWR_OFF_SW : OUT std_logic;
N2ND_ERROR_STOP : OUT std_logic;
SEL_CHNL_CPU_CLOCK_STOP : OUT std_logic;
CLOCK_START : OUT std_logic;
EARLY_ROAR_STOP : OUT std_logic;
HARD_STOP_LCH : OUT std_logic;
-- CLOCK_RST : OUT std_logic;
-- CLOCK_STOP : OUT std_logic;
DEBUG : OUT std_logic;
-- Clocks
T2,T3,T4 : IN std_logic;
P1 : IN std_logic;
clk : IN std_logic
);
END ClockStartStop;
ARCHITECTURE slt OF ClockStartStop IS
signal STT_RST_INLK : std_logic := '1';
signal CLK_STT_CTRL : std_logic := '0';
signal SET_IC_START : std_logic;
signal SET_IC_INLK : std_logic := '1';
signal PROCESS_STOP : std_logic := '0';
signal PROC_STOP_LOOP_ACTIVE : std_logic;
signal LOAD_KEY : std_logic := '0';
signal CF100T4 : std_logic;
signal CF_STOP : std_logic := '0';
signal INSTRUCTION_STEP_SW : std_logic;
signal SINGLE_CYCLE_SW : std_logic;
signal HS_MACH_CHK, HS_ALU_CHK, HS_DIAG, HS_MATCH, HS_INSTR : std_logic;
signal LOAD_REQ : std_logic;
signal PWR_OFF : std_logic := '0';
signal sSTART_SW_RST : std_logic := '0';
signal sE_CY_STOP_SAMPLE : std_logic := '0';
signal sLOAD_KEY_SW : std_logic;
signal sLOAD_KEY_INLK : std_logic := '1';
signal sSET_IC_ALLOWED : std_logic := '0';
signal sROS_SCAN : std_logic;
signal sLOAD_IND : std_logic := '0';
signal sRST_SEL_CHNL_DIAG_LCHS : std_logic;
signal sRST_LOAD : std_logic;
signal sCLOCK_START_LCH : std_logic := '0';
signal sPWR_OFF_SW : std_logic;
signal sN2ND_ERROR_STOP : std_logic := '0';
signal sSEL_CHNL_CPU_CLOCK_STOP : std_logic;
signal sCLOCK_START : std_logic;
signal sEARLY_ROAR_STOP : std_logic;
signal sHARD_STOP_LCH : std_logic := '0';
signal sCLOCK_RST : std_logic;
signal sCLOCK_STOP : std_logic;
signal HS_DIAG_DEGLITCHED : std_logic;
-- The following signals are required to allow the FL components to instantiate
signal CSC_LCH_Set,SSR_LCH_Set,SSR_LCH_Reset,ECS_LCH_Set,ECS_LCH_Reset,LKI_LCH_Set,
LK_LCH_Set,LK_LCH_Reset,SI_LCH_Set,SI_LCH_Reset,SIA_LCH_Set,SIA_LCH_Reset,
PS_LCH_Set,PS_LCH_Reset,CFS_LCH_Reset,CS_LCH_Set,CS_LCH_Reset,N2E_LCH_Set,N2E_LCH_Reset,
PO_LCH_Set,HS_LCH_Set : std_logic;
BEGIN
-- Fig 5-03C
-- STT RST INLK
SRI_LCH: FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output
-- STT RST
SSR_LCH_Set <= ALLOW_MAN_OPER and STT_RST_INLK and not SW_START;
SSR_LCH_Reset <= T2 or MACH_RST_SW;
SSR_LCH: FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7
START_SW_RST <= sSTART_SW_RST;
-- CLK STT CTRL
CSC_LCH_Set <= sCLOCK_RST or sE_CY_STOP_SAMPLE;
CSC_LCH: FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5
-- E CY STOP SAMPLE
ECS_LCH_Set <= SET_IC_START or (FT3_MPX_SHARE_REQ and M_CONV_OSC and PROC_STOP_LOOP_ACTIVE) or
(M_CONV_OSC and PROC_STOP_LOOP_ACTIVE and SEL_ROS_REQ) or
(not SW_START and M_CONV_OSC and not CLK_STT_CTRL); -- "not CLK_STT_CTRL" ?? is CLK_STT_CTRL meant to be inverted?
ECS_LCH_Reset <= MACH_RST_SW or T4;
ECS_LCH: FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7
E_CY_STOP_SAMPLE <= sE_CY_STOP_SAMPLE;
-- LOAD KEY INLK
LKI_LCH_Set <= (not SW_LOAD and MACH_RST_3) or LOAD_KEY;
LKI_LCH: FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output
LOAD_KEY_INLK <= sLOAD_KEY_INLK;
-- LOAD KEY
LK_LCH_Set <= not sLOAD_KEY_SW and sLOAD_KEY_INLK;
LK_LCH_Reset <= T4 or sCLOCK_RST;
LK_LCH: FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7
sLOAD_KEY_SW <= SW_LOAD;
LOAD_KEY_SW <= sLOAD_KEY_SW;
-- SET IC INLK
SI_LCH_Set <= (CLOCK_ON and SW_SET_IC) or MACH_RST_3 or sSET_IC_ALLOWED; -- MACH_RST_3 inverted??
SI_LCH_Reset <= not SW_SET_IC; -- FMD is missing invert on switch output??
SI_LCH: FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7
-- SET IC
SIA_LCH_Set <= ALLOW_MAN_OPER and not SET_IC_INLK and SW_SET_IC;
SIA_LCH_Reset <= T2 or MACH_RST_SW;
SIA_LCH: FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7
SET_IC_ALLOWED <= sSET_IC_ALLOWED;
SET_IC_START <= not FORCE_IJ_REQ_LCH and M_CONV_OSC and sSET_IC_ALLOWED; -- AC1D6
-- PROCESS STOP
PS_LCH_Set <= sSET_IC_ALLOWED or SW_STOP or (SAR_DLYD_STOP_SW and MATCH) or (INSTRUCTION_STEP_SW and T4);
PS_LCH_Reset <= sSTART_SW_RST or '0'; -- ?? What is second reset input?
PS_LCH: FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5
DEBUG <= PROCESS_STOP; -- ?? DEBUG ??
PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed??
INH_ROSAR_SET <= PROC_STOP_LOOP_ACTIVE and not ANY_PRIORITY_PULSE; -- AC1D5
STOP_REQ <= PROCESS_STOP and not S_REG_1_DLYD and not INTERRUPT and END_OF_E_CY_LCH; -- AC1H7
-- CF STOP
CF100T4 <= SALS.SALS_CF(0) and not SALS.SALS_CF(1) and not SALS.SALS_CF(2) and T4; -- AA2G5
CFS_LCH_Reset <= (not CF100T4 and T4) or (not FORCE_IJ_REQ and not sROS_SCAN and not SW_PROC) or MACH_START_RST; -- AC1G5 AC1K6 AC1M5 AC1F2 ?? SW_INH_CF_STOP instead of SW_PROC ??
CFS_LCH: FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5
sROS_SCAN <= SW_SCAN;
ROS_SCAN <= sROS_SCAN;
ROS_CTRL_PROC_SW <= SW_PROC;
SINGLE_CYCLE_SW <= SW_SINGLE_CYCLE;
INSTRUCTION_STEP_SW <= SW_INSTRUCTION_STEP;
-- LOAD REQ
sRST_LOAD <= GT_CK_DECODE and SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3); -- AB3F7
RST_LOAD <= sRST_LOAD;
sRST_SEL_CHNL_DIAG_LCHS <= MACH_RST_3 or sRST_LOAD; -- AC1F5,AC1H6
LOAD_REQ_FL: FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5
RST_SEL_CHNL_DIAG_LCHS <= sRST_SEL_CHNL_DIAG_LCHS;
LOAD_IND <= sLOAD_IND;
LOAD_REQ <= sLOAD_IND;
LOAD_REQ_LCH <= sLOAD_IND; -- AC1F2
FT_4_LD_IND <= sLOAD_IND;
-- CLOCK START
CS_LCH_Set <= (LOAD_KEY and P_CONV_OSC) or (P_CONV_OSC and sE_CY_STOP_SAMPLE and not MAN_OPERATION);
CS_LCH_Reset <= sCLOCK_RST or sCLOCK_STOP;
CS_LCH: FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6
CLOCK_START_LCH <= sCLOCK_START_LCH;
sSEL_CHNL_CPU_CLOCK_STOP <= not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and T4) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_T4) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and not SEL_SHARE_HOLD) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_CONV_OSC and SEL_BASIC_CLOCK_OFF); -- AD1D2,AD1C4
SEL_CHNL_CPU_CLOCK_STOP <= sSEL_CHNL_CPU_CLOCK_STOP;
sCLOCK_START <= (not sSEL_CHNL_CPU_CLOCK_STOP and sCLOCK_START_LCH and not PWR_OFF) and ((GT_J_REG_TO_A_BUS or not CF_STOP) and sCLOCK_START_LCH); -- AC1E4,AC1G6 ?? CLOCK_START_LCH twice?
CLOCK_START <= sCLOCK_START;
-- 2ND ERR STP
N2E_LCH_Set <= MACH_CHK_PULSE and P1;
N2E_LCH_Reset <= MACH_CHK_RST or HZ_DEST_RST;
N2E_LCH: FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4
N2ND_ERROR_STOP <= sN2ND_ERROR_STOP;
--PWR OFF
sPWR_OFF_SW <= SW_PWR_OFF;
PWR_OFF_SW <= sPWR_OFF_SW;
PO_LCH_Set <= sPWR_OFF_SW and T3 and not ALLOW_WRITE;
PO_LCH: FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4
-- HARD STOP
HS_MACH_CHK <= (sN2ND_ERROR_STOP and T4 and FIRST_MACH_CHK) or (CHK_OR_DIAG_STOP_SW and ANY_MACH_CHK); -- AB3F4
sEARLY_ROAR_STOP <= MATCH_LCH and EARLY_ROAR_STOP_SW; -- AC1K5
EARLY_ROAR_STOP <= sEARLY_ROAR_STOP;
HS_ALU_CHK <= CHK_OR_DIAG_STOP_SW and ALU_CHK and T4; -- AB3H3
-- Z0_DELAY: entity AR port map(Z_BUS_0,clk,Z_BUS_0_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
-- T4_DELAY: entity AR port map(T4,clk,T4_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
HS_DIAG <= T4 and DIAGNOSTIC_SW and CS_DECODE_X001 and BASIC_CS0 and SUPPR_MACH_CHK_TRAP and not Z_BUS_0; -- AC1J6
-- DEGLITCH: entity DEGLITCH2 port map(HS_DIAG,clk,HS_DIAG_DEGLITCHED);
HS_MATCH <= (SAR_STOP_SW and MATCH_LCH and T4) or (ROAR_STOP_SW and T4 and MATCH_LCH) or (T4 and SINGLE_CYCLE_SW);
HS_INSTR <= T4 and INSTRUCTION_STEP_SW and ANY_PRIORITY_PULSE_PWR and sROS_SCAN; -- AB3H2
HS_LCH_Set <= HS_MACH_CHK or sEARLY_ROAR_STOP or HS_ALU_CHK or HS_DIAG or HS_MATCH or HS_INSTR;
HS_LCH: FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6
HARD_STOP_LCH <= sHARD_STOP_LCH;
sCLOCK_RST <= MACH_RST_3 or (sHARD_STOP_LCH and M_CONV_OSC_2) or (M_CONV_OSC_2 and not GT_J_REG_TO_A_BUS and CF_STOP); -- AC1F6,AC1G5
-- CLOCK_RST <= sCLOCK_RST;
sCLOCK_STOP <= (PROC_STOP_LOOP_ACTIVE and not SEL_ROS_REQ and not MPX_SHARE_REQ and T2) or (not LOAD_REQ and sLOAD_KEY_SW) or SYSTEM_RESET_SW; -- AC1H7,AC1J6,AC1J7
-- CLOCK_STOP <= sCLOCK_STOP;
END slt;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Manual Controls - Front panel switches Display, Store & Reset
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ManualControls IS
port
(
-- Inputs
E_SW_SEL_MAIN_STG,E_SW_SEL_AUX_STG : IN STD_LOGIC; -- 04C
E_CY_STOP_SMPL : IN STD_LOGIC; -- 03C
SEL_CHNL_DATA_XFER : IN STD_LOGIC; -- 12D
POWER_ON_RESET : IN STD_LOGIC; -- 14A
LOAD_KEY_SW : IN STD_LOGIC; -- 03C
CLOCK_OFF,CLOCK_ON : IN STD_LOGIC; -- 08A
WRITE_ECHO_1,WRITE_ECHO_2 : IN STD_LOGIC; -- 05D
READ_ECHO_1,READ_ECHO_2 : IN STD_LOGIC; -- 05D
CPU_READ_PWR : IN STD_LOGIC; -- 04D
SEL_AUX_RD_CALL : IN STD_LOGIC; -- 12C
SEL_WR_CALL : IN STD_LOGIC; -- 12C
ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
RECYCLE_RST : IN STD_LOGIC; -- 04A
MAN_DSPLY_GUV_HUV : IN STD_LOGIC; -- 12C
CPU_WR_PWR : IN STD_LOGIC; -- 04D
LOAD_KEY_INLK : IN STD_LOGIC; -- 03C
POWER_OFF_SW : IN STD_LOGIC; -- 03C
IJ_SEL_SW,UV_SEL_SW : IN STD_LOGIC; -- 04C
SEL_AUX_WR_CALL : IN STD_LOGIC; -- 12C
USE_R : IN STD_LOGIC; -- 04D
SEL_T1 : IN STD_LOGIC;
CU_SALS : IN STD_LOGIC_VECTOR(0 to 1);
-- Switches
SW_DSPLY, SW_STORE,SW_SYS_RST : IN STD_LOGIC;
-- Outputs
MACH_RST_SW,MACH_RST_1,MACH_RST_3,MACH_RST_4,MACH_RST_5,MACH_RST_6,SYSTEM_RST_SW : OUT STD_LOGIC; -- Various
STG_MEM_SEL : OUT STD_LOGIC; -- 08D,04D,05B,06C
USE_MAN_DECODER_PWR : OUT STD_LOGIC; -- 04C,05C,05B
USE_MANUAL_DECODER : OUT STD_LOGIC; -- 04D,05B,04C,10C,07C,11C,05C
ALLOW_MAN_OPERATION : OUT STD_LOGIC; -- 03C,04A
MANUAL_DISPLAY : OUT STD_LOGIC; -- 06C,12C
MAN_STOR_OR_DSPLY : OUT STD_LOGIC; -- 04D,04A,06B,07B
MAN_STORE : OUT STD_LOGIC; -- 01C,06A,04B,06B,06C,01C,06A,04C
MAN_STORE_PWR : OUT STD_LOGIC; -- 05C,08B,06C,07B
STORE_S_REG_RST : OUT STD_LOGIC; -- 07B
CPU_SET_ALLOW_WR_LCH : OUT STD_LOGIC; -- 06C
MAN_RD_CALL : OUT STD_LOGIC; -- 05D,04D
GT_MAN_SET_MN : OUT STD_LOGIC; -- 07B
AUX_WRITE_CALL : OUT STD_LOGIC; -- 04B
ALLOW_WRITE : OUT STD_LOGIC; -- 05D,04A,06C,07A,04D,12C
ALLOW_WR_DLYD : OUT STD_LOGIC; -- 03A,04A,04D,12D,05D,03C,04B,06C,03B,04A
MANUAL_OPERATION : OUT STD_LOGIC; -- 03C
MAN_WRITE_CALL : OUT STD_LOGIC; -- 05D
STORE_R : OUT STD_LOGIC; -- 06C
-- Clocks
CONV_OSC : IN STD_LOGIC;
T1,T2 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END ManualControls;
ARCHITECTURE FMD OF ManualControls IS
signal AC1D4 : STD_LOGIC;
signal WRITE_ECHO,READ_ECHO : STD_LOGIC;
signal MAN_RD_INLK : STD_LOGIC;
signal MAN_RD_CALL_LCH : STD_LOGIC;
signal MAN_WR_CALL : STD_LOGIC;
signal MAN_WR_CALL_RST : STD_LOGIC;
signal sMACH_RST_SW,sMACH_RST_3,sSYSTEM_RST_SW : STD_LOGIC;
signal sSTG_MEM_SEL : STD_LOGIC;
signal sUSE_MANUAL_DECODER : STD_LOGIC;
signal sALLOW_MAN_OPERATION : STD_LOGIC;
signal sMANUAL_DISPLAY : STD_LOGIC;
signal sMAN_STOR_OR_DSPLY : STD_LOGIC;
signal sMAN_STORE,sMAN_STORE2 : STD_LOGIC;
signal sSTORE_S_REG_RST : STD_LOGIC;
signal sCPU_SET_ALLOW_WR_LCH : STD_LOGIC;
signal sMAN_RD_CALL : STD_LOGIC;
signal sALLOW_WRITE : STD_LOGIC;
signal sALLOW_WR : STD_LOGIC;
signal sSTORE_R : STD_LOGIC;
signal UMD_LCH_Set,UMD_LCH_Reset,MD_LCH_Set,MS_LCH_Set,AW_LCH_Set,AW_LCH_Reset,
MW_LCH_Set,MW_LCH_Reset,MRC_LCH_Set,MRC_LCH_Reset,SR_LCH_Set,SR_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-03D
-- USE MAN DECODER
sSTG_MEM_SEL <= E_SW_SEL_MAIN_STG or E_SW_SEL_AUX_STG; -- AC1H3
STG_MEM_SEL <= sSTG_MEM_SEL;
sALLOW_MAN_OPERATION <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CLOCK_OFF); -- AC1C4,AC1G3 ?? Removed a NOT here
ALLOW_MAN_OPERATION <= sALLOW_MAN_OPERATION;
UMD_LCH_Set <= (sALLOW_MAN_OPERATION and SW_DSPLY) or (sALLOW_MAN_OPERATION and SW_STORE);
UMD_LCH_Reset <= E_CY_STOP_SMPL or sMACH_RST_3;
UMD_LCH: FLL port map(UMD_LCH_Set,UMD_LCH_Reset, sUSE_MANUAL_DECODER); -- AC1G4
USE_MANUAL_DECODER <= sUSE_MANUAL_DECODER;
USE_MAN_DECODER_PWR <= not E_CY_STOP_SMPL and sUSE_MANUAL_DECODER; -- AC1J4
-- MAN DSPLY
AC1D4 <= (not E_CY_STOP_SMPL and not SEL_CHNL_DATA_XFER and CONV_OSC); -- AC1G2,AC1D4 -- Inverter removed ??
MD_LCH_Set <= CLOCK_OFF and SW_DSPLY and AC1D4;
MD_LCH: FLL port map(MD_LCH_Set,not SW_DSPLY,sMANUAL_DISPLAY); -- AC1G4 - FMD missing invert on Reset input ??
MANUAL_DISPLAY <= sMANUAL_DISPLAY;
-- MAN STORE R
sSTORE_S_REG_RST <= not CLOCK_ON and SW_STORE; -- AC1J6
STORE_S_REG_RST <= sSTORE_S_REG_RST;
MS_LCH_Set <= AC1D4 and sSTORE_S_REG_RST;
MS_LCH: FLL port map(MS_LCH_Set,not SW_STORE,sMAN_STORE); -- AC1E5
MAN_STORE <= sMAN_STORE;
-- MAN_STORE_PWR <= sMAN_STORE; -- AC1F3 -- Need to delay this a bit
MAN_STORE_DELAY: AR port map(sMAN_STORE,Clk,sMAN_STORE2); -- AC1F3
MAN_STORE2_DELAY: AR port map(sMAN_STORE2,Clk,MAN_STORE_PWR); -- AC1F3
sMAN_STOR_OR_DSPLY <= sMANUAL_DISPLAY or sMAN_STORE; -- AC1J2,AC1F3
MAN_STOR_OR_DSPLY <= sMAN_STOR_OR_DSPLY;
-- SYS RST
sSYSTEM_RST_SW <= SW_SYS_RST;
SYSTEM_RST_SW <= sSYSTEM_RST_SW;
sMACH_RST_SW <= SW_SYS_RST or POWER_ON_RESET or LOAD_KEY_SW;
MACH_RST_SW <= sMACH_RST_SW;
sMACH_RST_3 <= sMACH_RST_SW;
MACH_RST_1 <= sMACH_RST_3;
MACH_RST_3 <= sMACH_RST_3;
MACH_RST_4 <= sMACH_RST_3;
MACH_RST_5 <= sMACH_RST_3;
MACH_RST_6 <= sMACH_RST_3;
WRITE_ECHO <= WRITE_ECHO_1 or WRITE_ECHO_2; -- AA1J4
READ_ECHO <= READ_ECHO_1 or READ_ECHO_2; -- AA1K4
MAN_WR_CALL_RST <= WRITE_ECHO or sMACH_RST_3; -- AC1H3
sCPU_SET_ALLOW_WR_LCH <= (sMAN_STOR_OR_DSPLY and READ_ECHO) or (CPU_READ_PWR and T2); -- AA1K4 Wire-OR of negated signals
CPU_SET_ALLOW_WR_LCH <= sCPU_SET_ALLOW_WR_LCH;
-- ALLOW WR
AW_LCH_Set <= sCPU_SET_ALLOW_WR_LCH or SEL_AUX_RD_CALL;
AW_LCH_Reset <= sMACH_RST_3 or SEL_WR_CALL or MAN_WR_CALL or (ROAR_RESTT_STOR_BYPASS and RECYCLE_RST) or (CPU_WR_PWR and T2);
ALLOW_WRITE_LCH: FLL port map(AW_LCH_Set,AW_LCH_Reset,sALLOW_WRITE); -- AA1J2,AA1F6,AA1H3
ALLOW_WRITE <= sALLOW_WRITE;
DELAY_ALLOW_WR : entity AR port map (D=>sALLOW_WRITE,clk=>Clk,Q=>sALLOW_WR); -- AA1H2,AA1J7
ALLOW_WR_DLYD <= sALLOW_WR;
-- MAN WR CALL
MW_LCH_Set <= (sALLOW_WR and LOAD_KEY_INLK) or (sALLOW_WR and sSYSTEM_RST_SW) or (sALLOW_WR and POWER_OFF_SW) or (sMAN_STOR_OR_DSPLY and READ_ECHO);
MW_LCH_Reset <= CLOCK_ON or MAN_WR_CALL_RST;
MW_LCH: FLL port map(MW_LCH_Set,MW_LCH_Reset,MAN_WR_CALL); -- AC1J2,AC1F4,AC1H5
-- MAN RD INLK
MAN_RD_INLK_FL: FLL port map(MAN_RD_CALL_LCH,not sMAN_STOR_OR_DSPLY,MAN_RD_INLK); -- AC1F4
-- MAN RD CALL
MRC_LCH_Set <= sSTG_MEM_SEL and not MAN_RD_INLK and sMAN_STOR_OR_DSPLY;
MRC_LCH_Reset <= not sMAN_STOR_OR_DSPLY or READ_ECHO;
MAN_RD_CALL_FL: FLL port map(MRC_LCH_Set,MRC_LCH_Reset,MAN_RD_CALL_LCH); -- AC1J2,AC1E2
sMAN_RD_CALL <= MAN_RD_CALL_LCH and not sALLOW_WR; -- AC1J2
MAN_RD_CALL <= sMAN_RD_CALL;
GT_MAN_SET_MN <= (MAN_RD_CALL_LCH and sUSE_MANUAL_DECODER and not sALLOW_WR) or
(sMANUAL_DISPLAY and IJ_SEL_SW and not sALLOW_WR) or
(sMANUAL_DISPLAY and UV_SEL_SW and not sALLOW_WR)
or MAN_DSPLY_GUV_HUV; -- AC1H4,AC1G3
AUX_WRITE_CALL <= (CPU_WR_PWR and T2) or SEL_AUX_WR_CALL; -- AA1K4,AA1C3
MANUAL_OPERATION <= sMAN_RD_CALL or MAN_WR_CALL or MAN_WR_CALL_RST or READ_ECHO;
-- STORE R
SR_LCH_Set <= MAN_WR_CALL or (T1 and USE_R);
SR_LCH_Reset <= SEL_T1 or (T1 and not CU_SALS(0) and CU_SALS(1));
SR_LCH: FLL port map(SR_LCH_Set,SR_LCH_Reset,sSTORE_R); -- 06C
STORE_R <= sSTORE_R;
MAN_WRITE_CALL <= not READ_ECHO and MAN_WR_CALL and sSTORE_R; -- AC1G3
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-04A-B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Recycle Controls (04A) & Address Matching (04B)
-- Recycle Controls handles restarts and resets
-- Address Matching handles ROAR and SAR address matching (Address Compare switch)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RecycleCtrlsMatch IS
port
(
-- Inputs
N_CTRL_N : IN STD_LOGIC; -- 06B
XOR_OR_OR : IN STD_LOGIC; -- 02A
S_REG_7_BIT : IN STD_LOGIC; -- 07B
CLOCK_ON,CLOCK_OFF : IN STD_LOGIC; -- 08A
MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
HARD_STOP_LCH : IN STD_LOGIC; -- 03C
MPX_METERING_IN : IN STD_LOGIC; -- 08D
METER_IN_SX1 : IN STD_LOGIC; -- 11D
METER_IN_SX2 : IN STD_LOGIC; -- 13D
SEL_SHARE_HOLD : IN STD_LOGIC; -- 12D
KEY_SW : IN STD_LOGIC; -- 14A
MACH_RST_SW : IN STD_LOGIC; -- 03D
LOAD_KEY_SW : IN STD_LOGIC; -- 03C
SYSTEM_RESET_SW : IN STD_LOGIC; -- 03D
CL_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
INH_ROSAR_SET : IN STD_LOGIC; -- 03C
ALLOW_WRITE : IN STD_LOGIC; -- 03D
ALLOW_WRITE_DLYD : IN STD_LOGIC; -- 03D
SET_IC_LCH : IN STD_LOGIC; -- 03C
MACH_RST_3 : IN STD_LOGIC; -- 03D
FORCE_IJ_PULSE : IN STD_LOGIC; -- 03A
FORCE_IJ_REQ_LCH : IN STD_LOGIC; -- 03A
START_SW_RST : IN STD_LOGIC; -- 03C
MACH_RST_6 : IN STD_LOGIC; -- 03D
ANY_MACH_CHK : IN STD_LOGIC; -- 07A
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
SUPPR_MACH_CHK_TRAP : IN STD_LOGIC; -- 03A
ALLOW_MAN_OPERATION : IN STD_LOGIC; -- 03D
LOAD_IND : IN STD_LOGIC; -- 03C
N1050_INTRV_REQ : IN STD_LOGIC; -- 10C
TT6_POS_ATTN : IN STD_LOGIC; -- 10B
FT2_MPX_OPNL : IN STD_LOGIC; -- 08C
H_REG_5_PWR : IN STD_LOGIC; -- 04C
ROS_CTRL_PROC_SW : IN STD_LOGIC; -- 03C
RATE_SW_PROC_SW : IN STD_LOGIC; -- 03C
ODD : IN STD_LOGIC; -- 06B
INTRODUCE_ALU_CHK : IN STD_LOGIC; -- 06B
GT_SW_TO_WX_LCH : IN STD_LOGIC; -- 03A
HZ_DEST_RST : IN STD_LOGIC; -- 03A
MAIN_STORAGE : IN STD_LOGIC; -- 03D
WX_REG_BUS : IN STD_LOGIC_VECTOR(0 to 12); -- 01B
ABCD_SW_BUS : IN STD_LOGIC_VECTOR(0 to 15); --04C
MN_REGS_BUS : IN STD_LOGIC_VECTOR(0 to 15); -- 07A
AUX_WRITE_CALL : IN STD_LOGIC; -- 03D
DIAG_LATCH_RST : IN STD_LOGIC; -- NEW
-- Switches
SW_LAMP_TEST : IN STD_LOGIC;
SW_CHK_RST : IN STD_LOGIC;
SW_ROAR_RST : IN STD_LOGIC;
SW_CHK_RESTART,SW_DIAGNOSTIC,SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE : IN STD_LOGIC;
SW_ROAR_RESTT_STOR_BYPASS,SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,
SW_ROAR_STOP,SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : IN STD_LOGIC;
-- Outputs
LAMP_TEST : OUT STD_LOGIC; -- Various
CLOCK_OUT : OUT STD_LOGIC; -- 11D,13D,08D
TO_KEY_SW : OUT STD_LOGIC; -- 14A
METERING_OUT : OUT STD_LOGIC; -- 08D,13D,11D
MACH_RST_SET_LCH : OUT STD_LOGIC; -- 06B,01A
MACH_RST_SET_LCH_DLYD : OUT STD_LOGIC; -- 01B,06C,07B
FORCE_DEAD_CY_LCH : OUT STD_LOGIC; -- 03A
END_OF_E_CY_LCH : OUT STD_LOGIC; -- 03C
FORCE_IJ_REQ : OUT STD_LOGIC; -- 03A,03C
MACH_START_RST : OUT STD_LOGIC; -- 03C
DIAGNOSTIC_SW : OUT STD_LOGIC; -- 03A,03C,06B,08D
CHK_OR_DIAG_STOP_SW : OUT STD_LOGIC; -- 01A,01B,03C,13A,11A,11D,13D
-- CHK_SW_PROCESS_SW : OUT STD_LOGIC; -- 08D,07A,01B,11A
-- CHK_SW_DISABLE_SW : OUT STD_LOGIC; -- 07C
RECYCLE_RST : OUT STD_LOGIC; -- 03A,06B,03D,06B,04C,08D
MACH_CHK_RST : OUT STD_LOGIC; -- 03C,07A
CHK_RST_SW : OUT STD_LOGIC; -- 11A,13A
MACH_RST_LCH : OUT STD_LOGIC; -- 03A
GT_SWS_TO_WX_PWR : OUT STD_LOGIC; -- 01B,03A,06B
MATCH_LCH : OUT STD_LOGIC; -- 03C
MATCH : OUT STD_LOGIC; -- 03C
-- Indicators
IND_SYST,IND_MAN,IND_WAIT,IND_TEST,IND_LOAD,IND_EX,IND_CY_MATCH : OUT STD_LOGIC;
IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
Clk : IN STD_LOGIC
);
END RecycleCtrlsMatch;
ARCHITECTURE FMD OF RecycleCtrlsMatch IS
signal NWAIT : STD_LOGIC;
signal CHNL_TO_METER : STD_LOGIC;
signal SYSTEM_OPERATING : STD_LOGIC;
signal FORCE_DEAD_CY : STD_LOGIC;
signal TEST : STD_LOGIC;
signal END_OF_E_CYCLE : STD_LOGIC;
signal CHK_RESTT_LCH : STD_LOGIC;
signal CHK_RESTART_SW,CHK_STOP_SW : STD_LOGIC;
signal ROAR_RESTT_SW_ORED : STD_LOGIC;
signal RST_MATCH : STD_LOGIC;
signal MATCH_SET_MACH_RST_LCH : STD_LOGIC;
signal GT_MATCH_MN_CKT_1,GT_MATCH_WX_CKT_2 : STD_LOGIC;
signal OEA1,OEA2,OEA3,ANDWX,ANDMN : STD_LOGIC;
signal sTO_KEY_SW : STD_LOGIC;
signal sLAMP_TEST : STD_LOGIC;
signal sCLOCK_OUT : STD_LOGIC;
signal sFORCE_DEAD_CY_LCH : STD_LOGIC;
signal sEND_OF_E_CY_LCH : STD_LOGIC;
signal sFORCE_IJ_REQ : STD_LOGIC;
signal sMACH_RST_SET_LCH : STD_LOGIC;
signal sDIAGNOSTIC_SW : STD_LOGIC;
signal sRECYCLE_RST : STD_LOGIC;
signal sMACH_CHK_RST : STD_LOGIC;
signal sMATCH_LCH : STD_LOGIC;
signal sCHK_SW_PROCESS_SW : STD_LOGIC;
signal sMATCH : STD_LOGIC;
signal sMACH_RST_LCH : STD_LOGIC;
signal sGT_SWS_TO_WX_REG : STD_LOGIC;
signal NW_LCH_Set,NW_LCH_Reset,MRS_LCH_Reset,EEC_LCH_Set,FIJ_LCH_Set,FIJ_LCH_Reset,
CR_LCH_Set,CR_LCH_Reset,MR_LCH_Set,MR_LCH_Reset,GSWX_LCH_Set,GSWX_LCH_Reset,
M_LCH_Set,M_LCH_Reset : STD_LOGIC;
signal DIAG_LATCH : STD_LOGIC;
BEGIN
-- Fig 5-04A
NW_LCH_Set <= N_CTRL_N and XOR_OR_OR and T2;
NW_LCH_Reset <= not S_REG_7_BIT or sRECYCLE_RST;
NW_LCH: FLL port map(NW_LCH_Set,NW_LCH_Reset,NWAIT); --AC1E6,AC1F6
sCLOCK_OUT <= (not NWAIT and CLOCK_ON) or MAN_STOR_OR_DSPLY; -- AC1G6
CLOCK_OUT <= sCLOCK_OUT;
CHNL_TO_METER <= not HARD_STOP_LCH and (MPX_METERING_IN or METER_IN_SX1 or METER_IN_SX2); -- AC1K4,AC1F2 ??
SYSTEM_OPERATING <= sCLOCK_OUT or CHNL_TO_METER; -- AB2D2
sTO_KEY_SW <= sCLOCK_OUT or CHNL_TO_METER or SEL_SHARE_HOLD; -- AB2D2
TO_KEY_SW <= sTO_KEY_SW;
METERING_OUT <= sTO_KEY_SW and KEY_SW; -- AB2F4
sLAMP_TEST <= SW_LAMP_TEST;
LAMP_TEST <= sLAMP_TEST;
IND_SYST <= SYSTEM_OPERATING or sLAMP_TEST;
IND_MAN <= ALLOW_MAN_OPERATION or sLAMP_TEST;
IND_WAIT <= NWAIT or sLAMP_TEST;
IND_TEST <= TEST or sLAMP_TEST;
IND_LOAD <= LOAD_IND or sLAMP_TEST;
IND_EX <= END_OF_E_CYCLE or sLAMP_TEST;
IND_CY_MATCH <= sMATCH_LCH or sLAMP_TEST;
IND_ALLOW_WR <= ALLOW_WRITE or sLAMP_TEST;
IND_1050_INTRV <= N1050_INTRV_REQ or sLAMP_TEST;
IND_1050_REQ <= TT6_POS_ATTN or sLAMP_TEST;
IND_MPX <= FT2_MPX_OPNL or sLAMP_TEST;
IND_SEL_CHNL <= H_REG_5_PWR or sLAMP_TEST;
TEST <= (not ROS_CTRL_PROC_SW) or (not RATE_SW_PROC_SW) or (not SW_ADDR_COMP_PROC) or (not ODD) or (not sCHK_SW_PROCESS_SW) or INTRODUCE_ALU_CHK; -- AC1C4,AC1K5,AC1D4,AC1K5 ??
MRS_LCH_Reset <= not LOAD_KEY_SW and not SYSTEM_RESET_SW;
MRS_LCH: FLL port map(MACH_RST_SW,MRS_LCH_Reset,sMACH_RST_SET_LCH); -- AA2H5,AA2F5
MACH_RST_SET_LCH <= sMACH_RST_SET_LCH;
MACH_RST_SET_LCH_DLYD <= sMACH_RST_SET_LCH; -- ?? Should be delayed by 1 gate
-- MACH_RST_DELAY: AR port map(D=>sMACH_RST_SET_LCH,CLK=>Clk,Q=>MACH_RST_SET_LCH_DLYD); -- Delay
FORCE_DEAD_CY <= SW_SAR_RESTART and T4 and MATCH_SET_MACH_RST_LCH; -- AB3B6
FDC_LCH: FLL port map(FORCE_DEAD_CY,T3,sFORCE_DEAD_CY_LCH); -- AB3L3
FORCE_DEAD_CY_LCH <= sFORCE_DEAD_CY_LCH;
EEC_LCH_Set <= T2 and (CL_SALS(0) and CL_SALS(1) and CL_SALS(2) and CL_SALS(3)); -- ?? additional NOT
EEC_LCH: FLL port map(EEC_LCH_Set,T1,sEND_OF_E_CY_LCH); -- AC1G4 ?? Reset input is unlabeled
END_OF_E_CY_LCH <= sEND_OF_E_CY_LCH;
END_OF_E_CYCLE <= sEND_OF_E_CY_LCH or INH_ROSAR_SET; -- AC1J7
MATCH_SET_MACH_RST_LCH <= ((SW_SAR_RESTART and sMATCH_LCH and not ALLOW_WRITE_DLYD) or
(not ALLOW_WRITE_DLYD and CHK_RESTT_LCH and not ROAR_RESTT_SW_ORED and not SW_ROAR_RESTT_STOR_BYPASS)); -- AC1D2,AC1E6,AC1D4 ?? AC1D4 removed ??
FIJ_LCH_Set <= (MATCH_SET_MACH_RST_LCH and CLOCK_ON) or SET_IC_LCH; -- ?? *not* MATCH_SET_MACH_RST_LCH & *not* CLOCK_ON ??
FIJ_LCH_Reset <= MACH_RST_3 or (T1 and FORCE_IJ_PULSE);
FIJ_LCH: FLL port map(FIJ_LCH_Set,FIJ_LCH_Reset,sFORCE_IJ_REQ); -- AC1E6,AC1H6
FORCE_IJ_REQ <= sFORCE_IJ_REQ;
MACH_START_RST <= (sFORCE_IJ_REQ and not FORCE_IJ_REQ_LCH) or START_SW_RST or MACH_RST_6; -- AB3J5,AB3H3
CR_LCH_Set <= ANY_MACH_CHK and CHK_RESTART_SW;
CR_LCH_Reset <= ANY_PRIORITY_LCH or sMACH_CHK_RST;
CR_LCH: FLL port map(CR_LCH_Set,CR_LCH_Reset,CHK_RESTT_LCH); -- AB3H4,AC1H6
CHK_RESTART_SW <= SW_CHK_RESTART;
-- Diagnostic latch is not in the FMD but must have appeared later
-- It is set on Sys Reset and reset by the YL / 0->DIAG function (Alt-CK=0000)
DIAG_FL: FLL port map(S=>MACH_RST_6,R=>DIAG_LATCH_RST,Q=>DIAG_LATCH);
sDIAGNOSTIC_SW <= SW_DIAGNOSTIC or DIAG_LATCH;
DIAGNOSTIC_SW <= sDIAGNOSTIC_SW;
CHK_STOP_SW <= SW_CHK_STOP;
sCHK_SW_PROCESS_SW <= SW_CHK_SW_PROCESS;
-- CHK_SW_PROCESS_SW <= sCHK_SW_PROCESS_SW;
-- CHK_SW_DISABLE_SW <= SW_CHK_SW_DISABLE;
CHK_OR_DIAG_STOP_SW <= (sDIAGNOSTIC_SW and SUPPR_MACH_CHK_TRAP) or CHK_STOP_SW; -- AC1H3,AC1F5 ?? *not* SUPPR_MACH_CHK_TRAP ??
sRECYCLE_RST <= sMACH_RST_SET_LCH or
(SW_ROAR_RESTT_STOR_BYPASS and GT_SW_TO_WX_LCH) or
(ANY_PRIORITY_LCH and sFORCE_DEAD_CY_LCH and SW_SAR_RESTART) or
(SW_ROAR_RESTT_WITHOUT_RST and GT_SW_TO_WX_LCH and CHK_RESTART_SW) or
(GT_SW_TO_WX_LCH and SW_ROAR_RESTT); -- AB3K5,AB3L5,AB3L4
RECYCLE_RST <= sRECYCLE_RST;
sMACH_CHK_RST <= sRECYCLE_RST or SW_CHK_RST; -- AB3L3,AB3H5
MACH_CHK_RST <= sMACH_CHK_RST;
CHK_RST_SW <= SW_CHK_RST; -- AB3F5
MR_LCH_Set <= FORCE_DEAD_CY or MACH_RST_6;
MR_LCH_Reset <= HZ_DEST_RST or SW_ROAR_RST; -- ?? *not* SW_ROAR_RST
MR_LCH: FLL port map(MR_LCH_Set,MR_LCH_Reset,sMACH_RST_LCH); -- AB3F2,AB3J4
MACH_RST_LCH <= sMACH_RST_LCH;
GSWX_LCH_Set <= (SW_ROAR_RST and ALLOW_MAN_OPERATION) or
(SW_ROAR_RESTT_STOR_BYPASS and sMATCH) or
(T3 and ROAR_RESTT_SW_ORED and CHK_RESTT_LCH and not ALLOW_WRITE_DLYD) or
(not ALLOW_WRITE_DLYD and ROAR_RESTT_SW_ORED and sMATCH) or
(SW_ROAR_RESTT_STOR_BYPASS and CHK_RESTT_LCH);
GSWX_LCH_Reset <= MACH_RST_SW or (T3 and GT_SW_TO_WX_LCH);
GSWX_LCH: FLL port map(GSWX_LCH_Set,GSWX_LCH_Reset,sGT_SWS_TO_WX_REG); -- AC1H5,AC1H7,AC1H4,AC1K5,AC1J7
GT_SWS_TO_WX_PWR <= not sMACH_RST_LCH and sGT_SWS_TO_WX_REG; -- AC1E7
-- Fig 5-04B
ROAR_RESTT_SW_ORED <= SW_ROAR_RESTT or SW_ROAR_RESTT_WITHOUT_RST; -- AC1M5
GT_MATCH_WX_CKT_2 <= SW_ROAR_RESTT or SW_ROAR_RESTT_WITHOUT_RST or SW_EARLY_ROAR_STOP or
SW_ROAR_RESTT_STOR_BYPASS or SW_ROAR_STOP or SW_ROAR_SYNC; -- AC1M6
GT_MATCH_MN_CKT_1 <= SW_ADDR_COMP_PROC or
(MAIN_STORAGE and SW_SAR_DLYD_STOP) or
(MAIN_STORAGE and SW_SAR_STOP) or
(MAIN_STORAGE and SW_SAR_RESTART); -- AC1M6
RST_MATCH <= (SW_ADDR_COMP_PROC and T1) or
(SW_ROAR_SYNC and T1) or
(not ALLOW_WRITE_DLYD and START_SW_RST) or
(FORCE_IJ_REQ_LCH and T1) or
(sGT_SWS_TO_WX_REG and T1); -- AC1H3,AC1K4
OEA1 <= '1' when (not ABCD_SW_BUS(4 to 7) xor ((MN_REGS_BUS(4 to 7) and (4 to 7 => GT_MATCH_MN_CKT_1)) or (WX_REG_BUS(1 to 4) and (1 to 4 => GT_MATCH_WX_CKT_2))))="1111" else '0'; -- AA2C4
OEA2 <= '1' when (not ABCD_SW_BUS(8 to 11) xor ((MN_REGS_BUS(8 to 11) and (8 to 11 => GT_MATCH_MN_CKT_1)) or (WX_REG_BUS(5 to 8) and (5 to 8 => GT_MATCH_WX_CKT_2))))="1111" else '0'; -- AA2C5
OEA3 <= '1' when (not ABCD_SW_BUS(12 to 15) xor ((MN_REGS_BUS(12 to 15) and (12 to 15 => GT_MATCH_MN_CKT_1)) or (WX_REG_BUS(9 to 12) and (9 to 12 => GT_MATCH_WX_CKT_2))))="1111" else '0'; -- AA2D5
ANDMN <= AUX_WRITE_CALL and
(ABCD_SW_BUS(0) xnor MN_REGS_BUS(0)) and
(ABCD_SW_BUS(1) xnor MN_REGS_BUS(1)) and
(ABCD_SW_BUS(2) xnor MN_REGS_BUS(2)) and
(ABCD_SW_BUS(3) xnor MN_REGS_BUS(3)) and
GT_MATCH_MN_CKT_1 and OEA2 and OEA1 and OEA3; -- AC1K7,AC1L7
ANDWX <= (WX_REG_BUS(0) xor not ABCD_SW_BUS(3)) and OEA1 and OEA2 and OEA3 and GT_MATCH_WX_CKT_2 and T3; -- AC1L7
M_LCH_Set <= ANDMN or ANDWX;
M_LCH_Reset <= RST_MATCH or MACH_RST_SW;
M_LCH: FLL port map(M_LCH_Set,M_LCH_Reset,sMATCH_LCH); -- AC1L7,AC1L4
MATCH_LCH <= sMATCH_LCH;
sMATCH <= sMATCH_LCH and not CLOCK_OFF; -- AC1H5
MATCH <= sMATCH;
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-04C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Manual Data (E switch) & C,F,H registers
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ManualDataCFH IS
port
(
-- Inputs
MACH_RST_PROT : IN STD_LOGIC; -- 07B
USE_MAN_DECO_PWR : IN STD_LOGIC; -- 03D
N60_CY_TIMER_PULSE : IN STD_LOGIC; -- 14A
L_REGISTER : IN STD_LOGIC_VECTOR(0 to 7); -- 05C
MACH_RST_SW : IN STD_LOGIC; -- 03D
EXT_TRAP_MASK_ON : IN STD_LOGIC; -- 08C
USE_MAN_DECODER, USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
CK_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
GT_CK_DECO : IN STD_LOGIC; -- 03B
Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS_P : IN STD_LOGIC;
MACH_RST_2B : IN STD_LOGIC; -- 06B
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
RECYCLE_RST : IN STD_LOGIC; -- 04A
-- Switches
SW_INTRP_TIMER : IN STD_LOGIC;
SW_CONS_INTRP : IN STD_LOGIC;
SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
-- Outputs
ABCD_SW_BUS,FGHJ_SW_BUS : OUT STD_LOGIC_VECTOR(0 to 15);
AB_SW_P,CD_SW_P,FG_SW_P,HJ_SW_P : OUT STD_LOGIC;
IJ_SEL,UV_SEL : OUT STD_LOGIC;
TIMER_UPDATE : OUT STD_LOGIC; -- 02A
TIMER_UPDATE_OR_EXT_INT : OUT STD_LOGIC; -- 02A
EXT_INTRP : OUT STD_LOGIC; -- 02A
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
H_REG_BITS : OUT STD_LOGIC_VECTOR(0 to 7); -- 03B,03A
H_REG_P : OUT STD_LOGIC; -- 03B,03A
H_REG_6 : OUT STD_LOGIC;
H_REG_5_PWR : OUT STD_LOGIC; -- 02A,08B
GT_1050_TAGS : OUT STD_LOGIC; -- 10C
GT_1050_BUS : OUT STD_LOGIC; -- 10C
CD_REG_2 : OUT STD_LOGIC; -- 05C
-- E switch
E_SW : IN E_SW_BUS_Type;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END ManualDataCFH;
ARCHITECTURE FMD OF ManualDataCFH IS
signal RST_COUNTER : STD_LOGIC;
signal N10MSPULSE : STD_LOGIC;
signal BIN_DRIVE : STD_LOGIC;
signal CTRL_TRG : STD_LOGIC;
signal CTRL_LCH : STD_LOGIC;
signal CNTR_FULL : STD_LOGIC;
signal C_BINARY_CNTR : STD_LOGIC_VECTOR(4 to 7);
signal EXT_INT : STD_LOGIC;
signal RESET_F_REG : STD_LOGIC;
signal F_REGISTER : STD_LOGIC_VECTOR(0 to 7);
signal F_REGISTER_1A : STD_LOGIC;
signal SET_F_REG_0 : STD_LOGIC;
signal GT_C_TO_A_BUS : STD_LOGIC;
signal GT_F_TO_A : STD_LOGIC;
signal GT_H_TO_A : STD_LOGIC;
signal C_EXT_INT : STD_LOGIC_VECTOR(2 to 7);
signal H_SET : STD_LOGIC;
signal sTIMER_UPDATE : STD_LOGIC;
signal sH_REG_BITS : STD_LOGIC_VECTOR(0 to 7);
signal sH_REG_P : STD_LOGIC;
signal CTL_LCH_Set,CTL_LCH_Reset,CT_FF_Set,BD_FF_Set,EI_LCH_Set,EI_LCH_Reset,F0_LCH_Reset,F1_LCH_Set,F1A_LCH_Reset : STD_LOGIC;
signal F07_LCH_Reset,F07_LCH_Set : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-04C
-- Rotary switches ABCD and FGHJ
ABCD_SW_BUS <= SW_A & SW_B & SW_C & SW_D;
AB_SW_P <= SW_AP xnor SW_BP; -- AC1D2,AC1E3
CD_SW_P <= SW_CP xnor SW_DP; -- AC1D4,AC1E3,AC1D2
FGHJ_SW_BUS <= SW_F & SW_G & SW_H & SW_J;
FG_SW_P <= SW_FP xnor SW_GP; -- AC1D4,AC1E3,AC1D2
HJ_SW_P <= SW_HP xnor SW_JP; -- AC1D4,AC1E3,AC1D2
IJ_SEL <= '1' when (E_SW.I_SEL='1' or E_SW.J_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
UV_SEL <= '1' when (E_SW.U_SEL='1' or E_SW.V_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
RST_COUNTER <= MACH_RST_PROT; -- BE3G5
CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (not sTIMER_UPDATE and SW_INTRP_TIMER);
CTL_LCH_Reset <= CTRL_TRG and T3;
CTL_LCH: FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5
N10MSPULSE <= not(N60_CY_TIMER_PULSE and not T3); -- 10ms monostable here
CT_FF_Set <= CTRL_LCH and T4;
CT_FF: FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6
BD_FF_Set <= not CTRL_LCH and T2 and N10MSPULSE and not CNTR_FULL;
BD_FF: FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6
process(BIN_DRIVE,RST_COUNTER,CTRL_TRG) -- BE3G7,BE3F7
begin
if RST_COUNTER='1' or CTRL_TRG='1' then
C_BINARY_CNTR <= "0000";
else if BIN_DRIVE'event and BIN_DRIVE='0' then
C_BINARY_CNTR <= C_BINARY_CNTR + "0001";
end if;
end if;
end process;
CNTR_FULL <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6
-- Interrupt generation
sTIMER_UPDATE <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6,BE3G5
TIMER_UPDATE <= sTIMER_UPDATE;
-- TIMER_UPDATE_OR_EXT_INT <= sTIMER_UPDATE or EXT_INT; -- AC1D5
TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporary prevent Timer
EXT_INT <= (F_REGISTER(0) or F_REGISTER(1) or F_REGISTER(2) or F_REGISTER(3) or
F_REGISTER(4) or F_REGISTER(5) or F_REGISTER(6) or F_REGISTER(7)) and EXT_TRAP_MASK_ON; -- AC1G2 ?? Should this include EXT_TRAP_MASK_ON ?
EI_LCH_Reset <= MACH_RST_SW or RESET_F_REG;
EI_LCH_Set <= EXT_INT and T3; -- ?? Seems to be needed, not as per MDM
EI_LCH: FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2
-- F register - here it is held in True polarity, in the 2030 it is inverted
C_EXT_INT <= "000000";
SET_F_REG_0 <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1111
RESET_F_REG <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and not CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1110
F1A_LCH_Reset <= (L_REGISTER(1) and RESET_F_REG) or RECYCLE_RST;
F1_LCH_Set <= F_REGISTER_1A and SW_CONS_INTRP;
F1A_LCH: FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2
F07_LCH_Set <= SET_F_REG_0 & F1_LCH_Set & C_EXT_INT(2 to 7);
F07_LCH_Reset <= (0 to 7 => RECYCLE_RST) or ((0 to 7 => RESET_F_REG) and ('1' & L_REGISTER(1 to 7)));
F07_LCH: FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2
-- H register
H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or
(T4 and not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3)); -- AB1J2 CD=0101
GT_1050_TAGS <= not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and not CD_CTRL_REG(3); -- AB1B3 CD=0100
GT_1050_BUS <= not CD_CTRL_REG(0) and not CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3); -- AB1B3 CD=0001
CD_REG_2 <= CD_CTRL_REG(2); -- AB1B3
H_LCH: PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3
H_REG_BITS <= sH_REG_BITS;
HP_LCH: PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3
H_REG_P <= sH_REG_P;
H_REG_6 <= sH_REG_BITS(6); -- AB1C6,AB1G2
H_REG_5_PWR <= sH_REG_BITS(5); -- AB1L2
-- A bus drive
GT_C_TO_A_BUS <= (E_SW.C_SEL and USE_MAN_DECODER) or
(not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0100
GT_F_TO_A <= (E_SW.F_SEL and USE_MAN_DECO_PWR) or
(not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0000
GT_H_TO_A <= (E_SW.H_SEL and USE_MAN_DECODER) or
(not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3) and USE_BASIC_CA_DECODER); -- AB3C7 CA=0101
A_BUS <= not ("0000" & C_BINARY_CNTR & '0') when GT_C_TO_A_BUS='1'
else (F_REGISTER & '0') when GT_F_TO_A='1' -- ?? F_REGISTER should be inverted?
else not (sH_REG_BITS & sH_REG_P) when GT_H_TO_A='1'
else "111111111"; -- AB1F6
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-04D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Read/Write Storage Controls
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RWStgCntl IS
port
(
-- Inputs
SALS : IN SALS_Bus;
ANY_PRIORITY_PULSE,ANY_PRIORITY_PULSE_2 : IN STD_LOGIC; -- 03A
SEL_SHARE_HOLD : IN STD_LOGIC; -- 12D
G_REG_0_BIT,G_REG_1_BIT : IN STD_LOGIC; -- 05C
N1401_MODE : IN STD_LOGIC; -- 05A
USE_CPU_DECODER : IN STD_LOGIC; -- 05C
USE_MAN_DECODER : IN STD_LOGIC; -- 03D
E_SW_SEL_AUX_STG : IN STD_LOGIC; -- 04C
MEM_SEL : IN STD_LOGIC; -- 03D
ALLOW_WRITE,ALLOW_WRITE_2 : IN STD_LOGIC; -- 03D
SEL_RD_WR_CTRL : IN STD_LOGIC; -- 12C
MAN_STOR_OR_DISPLAY : IN STD_LOGIC; -- 03D
MACH_RST_1 : IN STD_LOGIC; -- 03D
MANUAL_RD_CALL,MANUAL_WR_CALL : IN STD_LOGIC; -- 03D
HSMPX_READ_CALL : IN STD_LOGIC; -- ?
SEL_RD_CALL_TO_STP : IN STD_LOGIC; -- 12C
SELECT_CPU_BUMP : IN STD_LOGIC; -- 08B
-- Outputs
USE_ALT_CU_DECODE : OUT STD_LOGIC; -- 01B
USE_GR_OR_HR : OUT STD_LOGIC; -- 12D,14D
USE_R : OUT STD_LOGIC; -- 06C,03D
CPU_WRITE_IN_R_REG : OUT STD_LOGIC; -- 07A
CPU_WRITE_PWR : OUT STD_LOGIC; -- 03D,12D,03D,05D
COMPUTE : OUT STD_LOGIC; -- 01C
CPU_READ_PWR : OUT STD_LOGIC; -- 07B,03D,05D
FORCE_M_REG_123 : OUT STD_LOGIC; -- 05B,08B
CU_DECODE_UCW : OUT STD_LOGIC; -- 05B
MAIN_STORAGE_CP : OUT STD_LOGIC; -- 07B,05Bm08B
LOCAL_STORAGE_CP : OUT STD_LOGIC; -- 07A
MAIN_STORAGE : OUT STD_LOGIC; -- 03B,06C,04B,06C,07A,08B
EARLY_LOCAL_STG : OUT STD_LOGIC; -- 05D
GT_LOCAL_STG : OUT STD_LOGIC; -- 08B
CHANNEL_RD_CALL : OUT STD_LOGIC; -- 07B
N_MEM_SELECT : OUT STD_LOGIC; -- 07B
RW_CTRL_STACK : OUT STD_LOGIC; -- 07B
-- Clocks
T1 : IN STD_LOGIC;
SEL_T1 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END RWStgCntl;
ARCHITECTURE FMD OF RWStgCntl IS
signal RD_SEL,WR_SEL : STD_LOGIC;
signal CU01,CM0X0 : STD_LOGIC;
signal CU_DECODE_CPU_LOCAL,MAN_SEL_LOCAL : STD_LOGIC;
signal sCU_DECODE_UCW : STD_LOGIC;
signal sMAIN_STORAGE_CP : STD_LOGIC;
signal sGT_LOCAL_STG : STD_LOGIC;
signal sCHANNEL_RD_CALL : STD_LOGIC;
signal sCPU_READ_PWR : STD_LOGIC;
signal sCPU_WRITE_PWR : STD_LOGIC;
signal sUSE_ALT_CU_DECODE : STD_LOGIC;
signal sUSE_R : STD_LOGIC;
signal sEARLY_LOCAL_STG : STD_LOGIC;
BEGIN
-- Fig 5-04D
sCHANNEL_RD_CALL <= (SEL_T1 and not SEL_RD_WR_CTRL) or HSMPX_READ_CALL; -- AD1L5,BE3E4
CHANNEL_RD_CALL <= sCHANNEL_RD_CALL;
RD_SEL <= MANUAL_RD_CALL or (sCPU_READ_PWR and T1) or sCHANNEL_RD_CALL; -- BE3D3,BE3H5,BE3J5
WR_SEL <= (T1 and sCPU_WRITE_PWR and ALLOW_WRITE_2) or MANUAL_WR_CALL or (SEL_RD_CALL_TO_STP or HSMPX_READ_CALL); -- BE3J5,BE3H5
N_MEM_SELECT <= not (not SELECT_CPU_BUMP and (RD_SEL or WR_SEL)); -- BE3H6
-- ?? Note TD not implemented (yet)
RW_LCH: FLL port map(RD_SEL,WR_SEL,RW_CTRL_STACK); -- BE3J5
sUSE_ALT_CU_DECODE <= not ANY_PRIORITY_PULSE and not sCPU_READ_PWR; -- AB3D2
USE_ALT_CU_DECODE <= sUSE_ALT_CU_DECODE;
CU01 <= not SALS.SALS_CU(0) and SALS.SALS_CU(1); -- AB3E2
USE_GR_OR_HR <= (sUSE_ALT_CU_DECODE and USE_CPU_DECODER and CU01); -- AB3E2,AB3H6-removed??
sUSE_R <= not CU01 and not SEL_SHARE_HOLD; -- AB3D5,AB3H3
USE_R <= sUSE_R;
CM0X0 <= not SALS.SALS_CM(0) and not SALS.SALS_CM(2); -- AB3D6
CPU_WRITE_IN_R_REG <= sUSE_R and CM0X0; -- AB3F2
sCPU_WRITE_PWR <= CM0X0;
CPU_WRITE_PWR <= sCPU_WRITE_PWR;
sCPU_READ_PWR <= (SALS.SALS_CM(0) and not ANY_PRIORITY_PULSE_2) or (SALS.SALS_CM(1) and SALS.SALS_CM(2) and not ANY_PRIORITY_PULSE_2); -- AB3B6,AB3D2
CPU_READ_PWR <= sCPU_READ_PWR;
COMPUTE <= not sCPU_WRITE_PWR and not sCPU_READ_PWR; -- AB3F2
CU_DECODE_CPU_LOCAL <= ((not G_REG_0_BIT or N1401_MODE) and (N1401_Mode or not G_REG_1_BIT) and SALS.SALS_CU(0) and SALS.SALS_CU(1) and USE_CPU_DECODER) or
(not SALS.SALS_CU(0) and SALS.SALS_CU(1) and USE_CPU_DECODER); -- AA1C2,AA1J4 ?? *not* N1401_MODE ??
FORCE_M_REG_123 <= CU_DECODE_CPU_LOCAL; -- AA1H2
sCU_DECODE_UCW <= SALS.SALS_CU(0) and not SALS.SALS_CU(1) and USE_CPU_DECODER; -- AA1C2
CU_DECODE_UCW <= sCU_DECODE_UCW;
MAN_SEL_LOCAL <= USE_MAN_DECODER and E_SW_SEL_AUX_STG; -- AA1C2
sEARLY_LOCAL_STG <= CU_DECODE_CPU_LOCAL or sCU_DECODE_UCW or MAN_SEL_LOCAL; -- AA1C3
EARLY_LOCAL_STG <= sEARLY_LOCAL_STG;
sMAIN_STORAGE_CP <= not sEARLY_LOCAL_STG; -- AA1J2
MAIN_STORAGE_CP <= sMAIN_STORAGE_CP;
-- SELECT_CPU_BUMP <= sEARLY_LOCAL_STG; -- ? Not sure!
sGT_LOCAL_STG <= ((MEM_SEL and not ALLOW_WRITE) and MAN_STOR_OR_DISPLAY) or (T1 and sCPU_READ_PWR) or (SEL_T1 and not SEL_RD_WR_CTRL) or MACH_RST_1; -- AA1C2,AA1J2-removed??,AA1G4
GT_LOCAL_STG <= sGT_LOCAL_STG;
LS_LCH: PH port map(not sMAIN_STORAGE_CP,sGT_LOCAL_STG,LOCAL_STORAGE_CP); -- AA1F4
MS_LCH: PH port map(not sEARLY_LOCAL_STG,sGT_LOCAL_STG,MAIN_STORAGE); -- AA1F4
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05A.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- R Reg (MSDR) Indicators and Checks
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RIndsChks IS
port
(
-- Inputs
TEST_LAMP : IN STD_LOGIC; -- 04A
R_REG_BUS : IN STD_LOGIC_VECTOR(0 to 7);
R_REG_BUS_P : IN STD_LOGIC;
G_REG_1 : IN STD_LOGIC;
V_REG_6,V_REG_7 : IN STD_LOGIC;
GM_WM_DETECTED : IN STD_LOGIC; -- 06C
CARRY_1_LCHD : IN STD_LOGIC; -- 06A
S_REG_1 : IN STD_LOGIC; -- 07B
W3_TO_MATCH : IN STD_LOGIC; -- 01B
ROS_SCAN : IN STD_LOGIC; -- 03C
GT_SW_MACH_RST : IN STD_LOGIC; -- 03A
-- Outputs
IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
IND_MSDR_P : OUT STD_LOGIC;
R_REG_PC : OUT STD_LOGIC; -- 07A
R_REG_VALID_DEC_DIGIT : OUT STD_LOGIC; -- 02A
N1BC_OR_R1 : OUT STD_LOGIC; -- 02A
S_REG_1_OR_R_REG_2 : OUT STD_LOGIC; -- 02A
G_REG_1_OR_R_REG_3 : OUT STD_LOGIC; -- 02A
V67_00_OR_GM_WM : OUT STD_LOGIC; -- 02A
N1401_MODE : OUT STD_LOGIC; -- 05B,06C,07A,01B,04D,13C
-- Clocks
T2 : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END RIndsChks;
ARCHITECTURE FMD OF RIndsChks IS
signal V67_EQUALS_00 : STD_LOGIC;
signal N1401_MODE_SET,N1401_MODE_RESET : STD_LOGIC;
signal sN1401_MODE : STD_LOGIC;
BEGIN
-- Fig 5-05A
IND_MSDR <= R_REG_BUS or (0 to 7 => TEST_LAMP);
IND_MSDR_P <= R_REG_BUS_P or TEST_LAMP;
R_REG_PC <= EvenParity(R_REG_BUS & R_REG_BUS_P); -- AA1K6
R_REG_VALID_DEC_DIGIT <= ((not R_REG_BUS(0) or not R_REG_BUS(1)) and (not R_REG_BUS(0) or not R_REG_BUS(2))) and
((not R_REG_BUS(4) or not R_REG_BUS(5)) and (not R_REG_BUS(4) or not R_REG_BUS(6))); -- ?? *and* or *or* as per MDM?
N1401_MODE_SET <= W3_TO_MATCH and not ROS_SCAN; -- AC1C4
N1401_MODE_RESET <= T2 or GT_SW_MACH_RST;
MODE1401: FLL port map(N1401_MODE_SET,N1401_MODE_RESET,sN1401_MODE); -- AB2B2,AB1B3,AB2C2
N1401_MODE <= sN1401_MODE;
V67_EQUALS_00 <= not V_REG_6 and not V_REG_7; -- AA1H6
-- AB2C2,AB2B2:
N1BC_OR_R1 <= (not sN1401_MODE or R_REG_BUS(1)) and ((CARRY_1_LCHD and not sN1401_MODE) or sN1401_MODE);
S_REG_1_OR_R_REG_2 <= (not sN1401_MODE or R_REG_BUS(2)) and (sN1401_MODE or S_REG_1);
G_REG_1_OR_R_REG_3 <= (not sN1401_MODE or R_REG_BUS(3)) and (sN1401_MODE or (not sN1401_MODE and G_REG_1));
V67_00_OR_GM_WM <= (not sN1401_MODE or GM_WM_DETECTED) and ((not sN1401_MODE and V67_EQUALS_00) or sN1401_MODE);
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- M & N register (MSAR) assembly
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY MNAssem IS
port
(
-- Inputs
MAIN_STORAGE_CP : IN STD_LOGIC; -- 04D
SX_2_BUMP_SW_GT : IN STD_LOGIC; -- 13C
USE_CPU_DECODER : IN STD_LOGIC; -- 05C
E_SEL_SW_BUS : IN E_SW_BUS_Type; -- 04C
SALS : IN SALS_Bus; -- 01C
MEM_SEL : IN STD_LOGIC; -- 03D
USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
N1401_MODE : IN STD_LOGIC; -- 05A
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03D
SX_2_R_W_CTRL : IN STD_LOGIC; -- 14D
SX_2_SHARE_CYCLE : IN STD_LOGIC; -- 14D
SX_2_GATE : IN STD_LOGIC; -- 13C
SX_1_R_W_CTRL : IN STD_LOGIC; -- 12D
SX_1_SHARE_CYCLE : IN STD_LOGIC; -- 12D
SX_1_GATE : IN STD_LOGIC; -- 13C
XXH : IN STD_LOGIC; -- 08C
CU_DECODE_UCW : IN STD_LOGIC; -- 04D
FORCE_M_REG_123 : IN STD_LOGIC; -- 04D
XH,XL : IN STD_LOGIC; -- 08C
CU_SAL_0_BIT : IN STD_LOGIC; -- 01C
MACH_RST_2A : IN STD_LOGIC; -- 06B
ABCD_SW_BUS : IN STD_LOGIC_VECTOR(0 to 15); -- 04B
AB_SW_P,CD_SW_P : IN STD_LOGIC; -- 04B
I,U,T,V,J,L,GU,GV,HU,HV : IN STD_LOGIC_VECTOR(0 to 7);
I_P,U_P,T_P,V_P,J_P,L_P,GU_P,GV_P,HU_P,HV_P : IN STD_LOGIC;
IJ_SEL, UV_SEL : IN STD_LOGIC; -- 04C
-- Outputs
GT_T_TO_MN_REG : OUT STD_LOGIC; -- 08B
GT_CK_TO_MN_REG : OUT STD_LOGIC; -- 08B
GT_V_TO_N_REG : OUT STD_LOGIC; -- 03B
GT_J_TO_N_REG : OUT STD_LOGIC; -- 03B
M_BUS,N_BUS : OUT STD_LOGIC_VECTOR(0 to 7);
M_BUS_P,N_BUS_P : OUT STD_LOGIC
);
END MNAssem;
ARCHITECTURE FMD OF MNAssem IS
signal GT_ABCD_SWS_TO_MN : STD_LOGIC;
signal GT_I_TO_M_REG,GT_U_TO_M_REG : STD_LOGIC;
signal CK_BUS : STD_LOGIC_VECTOR(0 to 7);
signal CK_BUS_P : STD_LOGIC;
signal GATE_L_REG_TO_M_BUS : STD_LOGIC;
signal GT_GUV_OR_HUV_TO_MN : STD_LOGIC;
signal GT_HUV_TO_MN,GT_GUV_TO_MN : STD_LOGIC;
signal M_BUSP,N_BUSP : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal sGT_T_TO_MN_REG : STD_LOGIC;
signal sGT_CK_TO_MN_REG : STD_LOGIC;
signal sGT_V_TO_N_REG : STD_LOGIC;
signal sGT_J_TO_N_REG : STD_LOGIC;
BEGIN
-- Fig 5-05B
GT_ABCD_SWS_TO_MN <= MEM_SEL and USE_MAN_DECODER_PWR; -- AC1F3
GT_I_TO_M_REG <= IJ_SEL or (MAIN_STORAGE_CP and USE_CPU_DECODER and not SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2)); -- AA1H2,AA1H7,AA1J7 CM=011
GT_U_TO_M_REG <= (MAIN_STORAGE_CP and USE_CPU_DECODER and SALS.SALS_CM(0) and not SALS.SALS_CM(1) and not SALS.SALS_CM(2)) or UV_SEL; -- AA1H7,AA1H2,AA1J7 CM=100
sGT_T_TO_MN_REG <= USE_CPU_DECODER and SALS.SALS_CM(0) and not SALS.SALS_CM(1) and SALS.SALS_CM(2); -- AB3E2,AB3F7-removed?? CM=101
GT_T_TO_MN_REG <= sGT_T_TO_MN_REG;
sGT_CK_TO_MN_REG <= USE_CPU_DECODER and SALS.SALS_CM(0) and SALS.SALS_CM(1) and not SALS.SALS_CM(2); -- AB3E2,AB3F7-removed?? CM=110
GT_CK_TO_MN_REG <= sGT_CK_TO_MN_REG;
CK_BUS(0) <= '1';
CK_BUS(1) <= '0';
CK_BUS(2) <= SALS.SALS_CN(0) or SX_2_BUMP_SW_GT; -- AB1C6
CK_BUS(3) <= SALS.SALS_CK(0);
CK_BUS(4) <= '1';
CK_BUS(5) <= SALS.SALS_CK(1);
CK_BUS(6) <= SALS.SALS_CK(2);
CK_BUS(7) <= SALS.SALS_CK(3);
CK_BUS_P <= (not SALS.SALS_PK or SALS.SALS_CM(0) or not CK_BUS(2)) and (not SALS.SALS_PK or SX_2_BUMP_SW_GT); -- AB1C6
sGT_V_TO_N_REG <= UV_SEL or (SALS.SALS_CM(0) and not SALS.SALS_CM(1) and not SALS.SALS_CM(2) and USE_CPU_DECODER); -- AB3C2 CM=100
GT_V_TO_N_REG <= sGT_V_TO_N_REG;
sGT_J_TO_N_REG <= (not SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2) and USE_CPU_DECODER) or IJ_SEL; -- AB3C2 CM=011
GT_J_TO_N_REG <= sGT_J_TO_N_REG;
GT_GUV_OR_HUV_TO_MN <= USE_CPU_DECODER and SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2); -- AB3C2 CM=111
GT_HUV_TO_MN <= (USE_MANUAL_DECODER and E_SEL_SW_BUS.E_SEL_SW_HUV_HCD) or (not SX_2_R_W_CTRL and SX_2_SHARE_CYCLE) or (SX_2_GATE and GT_GUV_OR_HUV_TO_MN); -- AE1D5
GT_GUV_TO_MN <= (USE_MANUAL_DECODER and E_SEL_SW_BUS.E_SEL_SW_GUV_GCD) or (not SX_1_R_W_CTRL and SX_1_SHARE_CYCLE) or (GT_GUV_OR_HUV_TO_MN and SX_1_GATE); -- AD1H6
GATE_L_REG_TO_M_BUS <= N1401_MODE and MAIN_STORAGE_CP and sGT_T_TO_MN_REG; -- AB2B3
M_BUSP <= ((0 to 8 => GT_HUV_TO_MN) and HU & HU_P) or -- AB1D2
((0 to 8 => GT_ABCD_SWS_TO_MN) and ABCD_SW_BUS(0 to 7) & AB_SW_P) or -- AB1D2
((0 to 8 => GATE_L_REG_TO_M_BUS) and L & L_P) or -- AB1D2
((0 to 8 => GT_GUV_TO_MN) and GU & GU_P) or -- AB1C2
((0 to 8 => GT_I_TO_M_REG) and I & I_P) or -- AB1C2
((0 to 8 => GT_U_TO_M_REG) and U & U_P) or -- AB1C2
(0 => '0', 1 => (XXH and CU_DECODE_UCW) or (CU_DECODE_UCW and N1401_MODE) or FORCE_M_REG_123, 2 to 8 => '0') or -- AA1B4
(0 to 1 => '0', 2 => (CU_DECODE_UCW and XH and not N1401_MODE) or FORCE_M_REG_123, 3 to 8 => '0') or -- AB1B3,AA1J4
(0 to 2 => '0', 3 => (CU_DECODE_UCW and XL) or (FORCE_M_REG_123 and not N1401_MODE) or (N1401_MODE and CU_SAL_0_BIT and USE_CPU_DECODER), 4 to 8 => '0') or -- AA1B4
(0 to 7 => '0', 8 => (not N1401_MODE and sGT_T_TO_MN_REG) or MACH_RST_2A or sGT_CK_TO_MN_REG); -- AB1G2
M_BUS <= M_BUSP(0 to 7);
M_BUS_P <= M_BUSP(8);
N_BUSP <= ((0 to 8 => GT_ABCD_SWS_TO_MN) and ABCD_SW_BUS(8 to 15) & CD_SW_P) or -- AB1D4
((0 to 8 => sGT_CK_TO_MN_REG) and CK_BUS & CK_BUS_P) or -- AB1D4
(0 to 7 => '0', 8 => MACH_RST_2A) or -- AB1D4
((0 to 8 => sGT_T_TO_MN_REG) and T & T_P) or -- AB1C4
((0 to 8 => sGT_V_TO_N_REG) and V & V_P) or -- AB1C4
((0 to 8 => sGT_J_TO_N_REG) and J & J_P) or -- AB1C4
((0 to 8 => GT_HUV_TO_MN) and HV & HV_P) or -- AB1E4
((0 to 8 => GT_GUV_TO_MN) and GV & GV_P); -- AB1E4
N_BUS <= N_BUSP(0 to 7);
N_BUS_P <= N_BUSP(8);
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- I,J,U,V,T,G,L & D registers and A,B bus assembly
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RegsABAssm IS
port
(
-- Inputs
-- A_BUS_IN : INOUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
SALS : IN SALS_BUS;
MACH_RST_SET_LCH : IN STD_LOGIC; -- 03B
SEL_SHARE_CYCLE : IN STD_LOGIC; -- ?
USE_MAN_DECODER : IN STD_LOGIC; -- 03D
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
FG_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 04C
FG_SW_P : IN STD_LOGIC;
HJ_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 8 is P
HJ_SW_P : IN STD_LOGIC;
USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
MPX_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08C 8 is P
FT0,FT3,FT5,FT6 : IN STD_LOGIC; -- 08D
FT1 : IN STD_LOGIC; -- 07C
FT2,FT7 : IN STD_LOGIC; -- 08C
FT4 : IN STD_LOGIC; -- 03C
E_SW_SEL_BUS : IN E_SW_BUS_TYPE; -- 04C
CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3);
CD_REG_2 : IN STD_LOGIC; -- 04C Unused
MACH_RST_2A_B : IN STD_LOGIC; -- 06B
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
R_REG : IN STD_LOGIC_VECTOR(0 to 8); -- 06C 8 is P
-- Outputs
USE_CPU_DECODER : OUT STD_LOGIC; -- 05B,04D
GATED_CA_BITS : OUT STD_LOGIC_VECTOR(0 to 3); -- 07C,10C
GT_J_TO_A,GT_D_TO_A : OUT STD_LOGIC; -- 03C
I,J,U,V,T,G,L : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
B_BUS_OUT : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
-- Clocks
T4 : IN STD_LOGIC
);
END RegsABAssm;
ARCHITECTURE FMD OF RegsABAssm IS
alias CA : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CA;
alias CK : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CK;
alias CB : STD_LOGIC_VECTOR(0 to 1) is SALS.SALS_CB;
alias AK_SAL_BIT : STD_LOGIC is SALS.SALS_AK;
signal GT_HJ_SWS_TO_B_BUS : STD_LOGIC;
signal GT_R_TO_B,GT_L_TO_B,GT_D_TO_B,GT_CK_TO_B : STD_LOGIC;
signal GT_FG_TO_A, GT_MPX_TAGS_TO_A, GT_MPX_BUS_TO_A,GT_I_TO_A,GT_U_TO_A, GT_V_TO_A,GT_T_TO_A,GT_G_TO_A,GT_L_TO_A,GT_R_TO_A : STD_LOGIC;
signal LCH_I,LCH_J,LCH_U,LCH_V,LCH_T,LCH_G,LCH_L,LCH_D : STD_LOGIC;
signal sUSE_CPU_DECODER : STD_LOGIC;
signal sGATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal sGT_J_TO_A, sGT_D_TO_A : STD_LOGIC;
signal sI,sJ,sU,sV,sT,sG,sL,sD : STD_LOGIC_VECTOR(0 to 8);
BEGIN
-- Fig 5-05C
sUSE_CPU_DECODER <= not MACH_RST_SET_LCH and not SEL_SHARE_CYCLE and not USE_MAN_DECODER; -- AB3C5
USE_CPU_DECODER <= sUSE_CPU_DECODER;
sGATED_CA_BITS <= CA and (0 to 3 => sUSE_CPU_DECODER); -- AA2J6,AA2J2
GATED_CA_BITS <= sGATED_CA_BITS;
GT_HJ_SWS_TO_B_BUS <= (not CK(0) and CK(1) and not CK(2) and not CK(3) and AK_SAL_BIT) or (MAN_STOR_PWR and USE_MAN_DECODER_PWR); -- AB3H7
GT_R_TO_B <= not CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_L_TO_B <= not CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_D_TO_B <= CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_CK_TO_B <= CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
B_BUS_OUT <= ((0 to 8 => GT_R_TO_B) and R_REG) or -- AB1K5
((0 to 8 => GT_L_TO_B) and sL) or -- AB1K5
((0 to 8 => GT_D_TO_B) and sD) or -- AB1K5
((0 to 8 => GT_CK_TO_B) and CK & CK & '1') or -- AB1L5
((0 to 8 => GT_HJ_SWS_TO_B_BUS) and HJ_SWS & HJ_SW_P); -- AB1L5
GT_FG_TO_A <= '1' when sGATED_CA_BITS="0001" and USE_ALT_CA_DECODER='1' else '0'; -- AB1F5
GT_MPX_TAGS_TO_A <= '1' when (sGATED_CA_BITS="0000" and USE_BASIC_CA_DECODER='1' and sUSE_CPU_DECODER='1') or (E_SW_SEL_BUS.FT_SEL='1' and USE_MAN_DECODER_PWR='1') else '0'; -- AA2C6 ?? and sUSE_CPU_DECODER required to prevent FT (CA=0000) from being put on A bus when not wanted
GT_MPX_BUS_TO_A <= '1' when (sGATED_CA_BITS="0110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.FI_SEL='1') else '0'; -- AB3C3
GT_I_TO_A <= '1' when (sGATED_CA_BITS="1111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.I_SEL='1') else '0'; -- AB1F4
sGT_J_TO_A <= '1' when (sGATED_CA_BITS="1110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.J_SEL='1') else '0'; -- AB1F4
GT_J_TO_A <= sGT_J_TO_A;
GT_U_TO_A <= '1' when (sGATED_CA_BITS="1101" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.U_SEL='1') else '0'; -- AB1F4
GT_V_TO_A <= '1' when (sGATED_CA_BITS="1100" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.V_SEL='1') else '0'; -- AB1F4
GT_T_TO_A <= '1' when (sGATED_CA_BITS="1011" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.T_SEL='1') else '0'; -- AB1F4
GT_G_TO_A <= '1' when (sGATED_CA_BITS="1010" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.G_SEL='1') else '0'; -- AB1F4
GT_L_TO_A <= '1' when (sGATED_CA_BITS="1001" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.L_SEL='1') else '0'; -- AB3C3
sGT_D_TO_A <= '1' when (sGATED_CA_BITS="1000" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.D_SEL='1') else '0'; -- AB3C3
GT_D_TO_A <= sGT_D_TO_A;
GT_R_TO_A <= '1' when (sGATED_CA_BITS="0111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.R_SEL='1') else '0'; -- AB3C3
A_BUS <= not(FG_SWS & FG_SW_P) when GT_FG_TO_A='1' else
not(FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') when GT_MPX_TAGS_TO_A='1' else
not MPX_BUS when GT_MPX_BUS_TO_A='1' else
not sI when GT_I_TO_A='1' else
not sJ when sGT_J_TO_A='1' else
not sU when GT_U_TO_A='1' else
not sV when GT_V_TO_A='1' else
not sT when GT_T_TO_A='1' else
not sG when GT_G_TO_A='1' else
not sL when GT_L_TO_A='1' else
not sD when sGT_D_TO_A='1' else
not R_REG when GT_R_TO_A='1' else
"111111111";
-- A_BUS_OUT <= A_BUS_IN or
-- ((0 to 8 => GT_FG_TO_A) and FG_SWS & FG_SW_P) or -- AB1D6
-- ((0 to 8 => GT_MPX_TAGS_TO_A) and FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') or -- AB1D6
-- ((0 to 8 => GT_MPX_BUS_TO_A) and MPX_BUS) or -- AB1D6
-- ((0 to 8 => GT_I_TO_A) and sI) or -- AB1F4
-- ((0 to 8 => sGT_J_TO_A) and sJ) or -- AB1F4
-- ((0 to 8 => GT_U_TO_A) and sU) or -- AB1F4
-- ((0 to 8 => GT_V_TO_A) and sV) or -- AB1C7
-- ((0 to 8 => GT_T_TO_A) and sT) or -- AB1C7
-- ((0 to 8 => GT_G_TO_A) and sG) or -- AB1C7
-- ((0 to 8 => GT_L_TO_A) and sL) or -- AB3C3
-- ((0 to 8 => sGT_D_TO_A) and sD) or -- AB3C3
-- ((0 to 8 => GT_R_TO_A) and R_REG); -- AB3C3
LCH_I <= '1' when (CD_CTRL_REG="1111" and T4='1') or (E_SW_SEL_BUS.I_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_J <= '1' when (CD_CTRL_REG="1110" and T4='1') or (E_SW_SEL_BUS.J_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_U <= '1' when (CD_CTRL_REG="1101" and T4='1') or (E_SW_SEL_BUS.U_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_V <= '1' when (CD_CTRL_REG="1100" and T4='1') or (E_SW_SEL_BUS.V_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_T <= '1' when (CD_CTRL_REG="1011" and T4='1') or (E_SW_SEL_BUS.T_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_G <= '1' when (CD_CTRL_REG="1010" and T4='1') or (E_SW_SEL_BUS.G_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_L <= '1' when (CD_CTRL_REG="1001" and T4='1') or (E_SW_SEL_BUS.L_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
LCH_D <= '1' when (CD_CTRL_REG="1000" and T4='1') or (E_SW_SEL_BUS.D_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
I_REG: PHV9 port map(Z_BUS,LCH_I,sI); -- AB1G3
I <= sI;
J_REG: PHV9 port map(Z_BUS,LCH_J,sJ); -- AB1G4
J <= sJ;
U_REG: PHV9 port map(Z_BUS,LCH_U,sU); -- AB1H3
U <= sU;
V_REG: PHV9 port map(Z_BUS,LCH_V,sV); -- AB1H4
V <= sV;
T_REG: PHV9 port map(Z_BUS,LCH_T,sT); -- AB1J4
T <= sT;
G_REG: PHV9 port map(Z_BUS,LCH_G,sG); -- AB1K4
G <= sG;
L_REG: PHV9 port map(Z_BUS,LCH_L,sL); -- AB1J2
L <= sL;
D_REG: PHV9 port map(Z_BUS,LCH_D,sD); -- AB1K3
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Read/Write Storage Clocks for 1st 32k
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RWStgClk1st32k IS
port
(
-- Inputs
ALLOW_WRITE : IN STD_LOGIC; -- 03D
CPU_READ_PWR : IN STD_LOGIC; -- 04D
SEL_RD_CALL : IN STD_LOGIC; -- 12C
MAN_RD_CALL : IN STD_LOGIC; -- 03D
ROAR_RESTT_AND_STOR_BYPASS : IN STD_LOGIC; -- 04B
SEL_WR_CALL : IN STD_LOGIC; -- 12C
MAN_WR_CALL : IN STD_LOGIC; -- 03D
CPU_WRITE_PWR : IN STD_LOGIC; -- 04D
EARLY_LOCAL_STG : IN STD_LOGIC; -- 04D
EARLY_M_REG_0 : IN STD_LOGIC; -- 07B
M_REG_0 : IN STD_LOGIC; -- 07B
MACH_RST_SW : IN STD_LOGIC; -- 03D
-- Outputs
READ_CALL : OUT STD_LOGIC; -- 03A,03B
USE_LOCAL_MAIN_MEM : OUT STD_LOGIC; -- 06D
USE_MAIN_MEMORY : OUT STD_LOGIC; -- 06D
READ_ECHO_1, READ_ECHO_2 : OUT STD_LOGIC; -- 03D
DATA_READY_1, DATA_READY_2 : OUT STD_LOGIC; -- 03A 03B
WRITE_ECHO_1, WRITE_ECHO_2 : OUT STD_LOGIC; -- 03D
-- Debug
DEBUG1,DEBUG2,DEBUG3,DEBUG4 : OUT STD_LOGIC;
DEBUG : OUT STD_LOGIC;
DBG_TD1_1, DBG_TD1_2 : OUT STD_LOGIC_VECTOR(1 to 38);
DBG_RD_OR_WR_SET1,DBG_RD_OR_WR_RST1 : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
CLK : IN STD_LOGIC -- 50MHz / 20ns
);
END RWStgClk1st32k;
ARCHITECTURE FMD OF RWStgClk1st32k IS
signal START_RD,START_WR : STD_LOGIC;
signal START_1ST_32K : STD_LOGIC;
signal READ_CALL_TO_MEM,WRITE_CALL_TO_MEM : STD_LOGIC;
signal sREAD_CALL : STD_LOGIC;
signal sUSE_LOCAL_MAIN_MEM : STD_LOGIC;
signal USE_LOCAL_Set,USE_LOCAL_Reset : STD_LOGIC;
signal TD1 : STD_LOGIC_VECTOR(1 to 38) := (others=>'0'); -- 20ns steps 20 to 740ns
signal RD_OR_WR_RST1, RD_OR_WR_SET1, nRD_OR_WR_SET1, CTRL_R_WIDTH1, TD1IN : STD_LOGIC;
signal TD1_80, TD1_150, TD1_200, TD1_500, TD1_560, TD1_660, TD1_680, TD1_700 : STD_LOGIC;
signal RD_OR_WR_SET1_RESET, dRD_OR_WR_SET1_RESET, CTRL_R_WIDTH1_RESET : STD_LOGIC;
signal READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_2_RESET : STD_LOGIC;
signal WRITE_ECHO_1_SET : STD_LOGIC;
signal WRITE_ECHO_1_RESET : STD_LOGIC;
signal READ_RST_SET1, READ_RST_SET2 : STD_LOGIC;
signal READ_RST_RESET1, READ_RST_RESET2 : STD_LOGIC;
signal RD_RST_CTRL1 : STD_LOGIC;
signal WRITE_RST_SET1 : STD_LOGIC;
signal WRITE_RST_RESET1 : STD_LOGIC;
signal WR_RST_CTRL1 : STD_LOGIC;
signal SET_READ_LCHS1 : STD_LOGIC;
signal DATA_READY1_SET, DATA_READY1_RESET : STD_LOGIC;
signal SET_READ_LCHS1_RESET : STD_LOGIC;
signal dT1 : STD_LOGIC;
signal sDATA_READY_1 : STD_LOGIC;
BEGIN
-- Fig 5-05D
START_RD <= not ALLOW_WRITE and CPU_READ_PWR and T1; -- AA1K4
START_WR <= ALLOW_WRITE and CPU_WRITE_PWR and T1; -- AA1K4
sREAD_CALL <= START_RD or SEL_RD_CALL or MAN_RD_CALL; -- AA1J2
READ_CALL <= sREAD_CALL;
READ_CALL_TO_MEM <= sREAD_CALL and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J3,AA1C2
WRITE_CALL_TO_MEM <= (MAN_WR_CALL or SEL_WR_CALL or START_WR) and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J2,AA1J3
USE_LOCAL_Set <= EARLY_LOCAL_STG and READ_CALL_TO_MEM;
USE_LOCAL_Reset <= not EARLY_LOCAL_STG and READ_CALL_TO_MEM;
USE_LOCAL: FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2
USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM;
USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2
START_1ST_32K <= (not EARLY_M_REG_0 and READ_CALL_TO_MEM) or (READ_CALL_TO_MEM and EARLY_LOCAL_STG) or (not M_REG_0 and WRITE_CALL_TO_MEM) or (WRITE_CALL_TO_MEM and sUSE_LOCAL_MAIN_MEM); -- CB1E2
-- START_2ND_32K <= (READ_CALL_TO_MEM and EARLY_M_REG_0 and not sUSE_LOCAL_MAIN_MEM) or (WRITE_CALL_TO_MEM and M_REG_0 and not sUSE_LOCAL_MAIN_MEM); -- CB1E2
-- Generate timing signals relative to START_xxx_32K
-- READ_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
-- WRITE_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
-- DATA_READY_n ON at 640ns OFF at 700ns (or MACH_RST_SW)
-- First 32K
TD1_80 <= TD1(4); -- 80ns
TD1_150 <= TD1(8); -- 160ns
TD1_200 <= TD1(10); -- 200ns
TD1_500 <= TD1(25); -- 500ns
TD1_560 <= TD1(28); -- 560ns
TD1_660 <= TD1(33); -- 660ns
TD1_680 <= TD1(34); -- 680ns
TD1_700 <= TD1(35); -- 700ns
nRD_OR_WR_SET1 <= not RD_OR_WR_SET1;
RD_OR_WR_RST1_FL: FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1);
RD_OR_WR_SET1_RESET <= RD_OR_WR_RST1 or MACH_RST_SW;
-- The delay is to prevent a combinatorial loop:
Delay_RD_OR_WR_SET1_RESET: AR port map (D=>RD_OR_WR_SET1_RESET, clk=>Clk, Q=>dRD_OR_WR_SET1_RESET);
RD_OR_WR_SET1_FL: FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1);
TD1IN <= not RD_OR_WR_RST1 and RD_OR_WR_SET1;
-- READ CLOCK 0
READ_ECHO_1_SET <= TD1_150 and SET_READ_LCHS1;
READ_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and RD_RST_CTRL1);
READ_ECHO_1_FL: FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns
-- READ CLOCK 4
DATA_READY1_SET <= TD1_560 and SET_READ_LCHS1;
DATA_READY1_RESET <= MACH_RST_SW or (TD1_660 and RD_RST_CTRL1);
DATA_READY1_FL: FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns
DATA_READY_1 <= sDATA_READY_1;
-- READ CLOCK 5
READ_RST_SET1 <= TD1_500 and SET_READ_LCHS1;
READ_RST_RESET1 <= MACH_RST_SW or TD1_700;
READ_RST1_FL: FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns
-- WRITE CLOCK 0
WRITE_ECHO_1_SET <= TD1_150 and not SET_READ_LCHS1;
WRITE_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and WR_RST_CTRL1);
WRITE_ECHO_1_FL: FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns
-- WRITE CLOCK 4
SET_READ_LCHS1_RESET <= MACH_RST_SW or WRITE_CALL_TO_MEM; -- ??
SET_READ_LCHS1_FL: FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL
-- WRITE CLOCK 5
WRITE_RST_SET1 <= TD1_500 and not SET_READ_LCHS1;
WRITE_RST_RESET1 <= MACH_RST_SW or TD1_150; -- 150ns or 1050ns or 1500ns?
WRITE_RST1_FL: FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns??
-- Second 32K
READ_ECHO_2 <= '0';
DATA_READY_2 <= '0';
WRITE_ECHO_2 <= '0';
-- Debug
DEBUG <= START_RD;
DBG_TD1_1 <= TD1;
DBG_RD_OR_WR_SET1 <= RD_OR_WR_SET1;
DBG_RD_OR_WR_RST1 <= RD_OR_WR_RST1;
delayLine: process(CLK)
begin
if (rising_edge(CLK)) then
TD1 <= TD1IN & TD1(1 to TD1'right-1);
end if;
end process;
-- Debug latch
R_DEBUG: process (clk,T1,TD1IN)
begin
if rising_edge(clk) then
if T1='1' and dT1='0' then
DEBUG1 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T1)='1' then
DEBUG1 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG2 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T2)='1' then
DEBUG2 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG3 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T3)='1' then
DEBUG3 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG4 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T4)='1' then
DEBUG4 <= '1'; -- Set on any DATA_READY
end if;
end if;
dT1 <= T1;
end if;
end process;
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-06A-B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- ALU, A & B registers
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ABALU IS
port
(
-- Inputs
LAMP_TEST : IN STD_LOGIC; -- 04A
SALS : IN SALS_Bus; -- 01C
MANUAL_STORE : IN STD_LOGIC; -- 03D
RECYCLE_RST : IN STD_LOGIC; -- 04A
S_REG_3 : IN STD_LOGIC; -- 07B
SERV_IN_SIG,STAT_IN_SIG,OPNL_IN,ADDR_IN : IN STD_LOGIC; -- 08D
T_REQUEST : IN STD_LOGIC; -- 10B
A_BUS, B_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 8 is P
MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
MACH_RST_SET_LCH : IN STD_LOGIC; -- 04B
S_REG_0 : IN STD_LOGIC; -- 07B
CTRL : IN CTRL_REG; -- 01C
DIAG_SW : IN STD_LOGIC; -- 04A
S_REG_RST : IN STD_LOGIC; -- 07B
GT_Z_BUS_TO_S_REG : IN STD_LOGIC; -- 07B
ROS_SCAN : IN STD_LOGIC; -- 03C
GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04A
RST_LOAD : IN STD_LOGIC; -- 03C
SYSTEM_RST_PRIORITY_LCH : IN STD_LOGIC; -- 03A
-- Outputs
IND_A,IND_B,IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
A_REG_PC,B_REG_PC : OUT STD_LOGIC; -- 11A,07A,13A
OPNL_IN_LCHD,STATUS_IN_LCHD,Z0_BUS_0,SERV_IN_LCHD,ADDR_IN_LCHD : OUT STD_LOGIC; -- 02A
CARRY_1_LCHD : OUT STD_LOGIC; -- 05A
CARRY_0_LATCHED : OUT STD_LOGIC; -- 01B,02A
CARRY_0 : OUT STD_LOGIC; -- 07B
ALU_CHK : OUT STD_LOGIC; -- 03C,01A,07A
NTRUE,COMPLEMENT : OUT STD_LOGIC; -- 03B
P_CONNECT : OUT STD_LOGIC; -- 02A
P_CTRL_N : OUT STD_LOGIC; -- 02A,03A
N_CTRL_N : OUT STD_LOGIC; -- 04A
N_CTRL_LM : OUT STD_LOGIC; -- 02A
P_Z_BUS,N_Z_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
Z_HI_0,Z_LO_0,Z_0,Z_BUS_LO_DIGIT_PARITY : OUT STD_LOGIC;
MACH_RST_2A,MACH_RST_2B,MACH_RST_2C : OUT STD_LOGIC;
ODD : OUT STD_LOGIC; -- 04A
ALU_CHK_LCH : OUT STD_LOGIC; -- 01B,08D
GT_CARRY_TO_S3 : OUT STD_LOGIC; -- 07B
INTRODUCE_ALU_CHK : OUT STD_LOGIC; -- 04A
DECIMAL : OUT STD_LOGIC; -- 02A
-- Debug
DBG_P_ALU_A_IN, DBG_P_ALU_B_IN, DBG_P_ALU_CARRY, DBG_P_ALU_SUMS : OUT STD_LOGIC_VECTOR(0 to 7);
DBG_N_ALU_A_IN, DBG_N_ALU_B_IN, DBG_N_ALU_CARRY, DBG_N_ALU_SUMS : OUT STD_LOGIC_VECTOR(0 to 7);
DEBUG : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END ABALU;
ARCHITECTURE FMD OF ABALU IS
alias CC : STD_LOGIC_VECTOR(0 to 2) is CTRL.CTRL_CC;
alias CV : STD_LOGIC_VECTOR(0 to 1) is CTRL.CTRL_CV;
alias CROSSED : STD_LOGIC is CTRL.CROSSED;
alias STRAIGHT : STD_LOGIC is CTRL.STRAIGHT;
alias GT_A_LO : STD_LOGIC is CTRL.GT_A_REG_LO;
alias GT_A_HI : STD_LOGIC is CTRL.GT_A_REG_HI;
alias GT_B_REG_LO : STD_LOGIC is CTRL.GT_B_REG_LO;
alias GT_B_REG_HI : STD_LOGIC is CTRL.GT_B_REG_HI;
signal P_CARRY_IN_7,N_CARRY_IN_7 : STD_LOGIC;
signal P_Z_ALU_BUS,N_Z_ALU_BUS : STD_LOGIC_VECTOR(0 to 7);
signal A_REG,B_REG : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal CARRY_S3,INSERT_CARRY,INSERT_0_CARRY : STD_LOGIC;
signal NOT_S3 : STD_LOGIC;
signal HEX,sDECIMAL : STD_LOGIC;
-- signal N_CONNECT : std_logic;
-- signal P_CTRL_LM : STD_LOGIC;
signal P_ALU_A_IN,N_ALU_A_IN : STD_LOGIC_VECTOR(0 to 7);
signal P_ALU_B_IN,N_ALU_B_IN : STD_LOGIC_VECTOR(0 to 7);
signal P_SUMS,N_SUMS,P_CARRY,N_CARRY : STD_LOGIC_VECTOR(0 to 7);
signal HSEL,LSEL : STD_LOGIC_VECTOR(0 to 2);
signal sINTRODUCE_ALU_CHK : STD_LOGIC;
signal sODD,EVEN : STD_LOGIC;
signal DIAG_TEST_BIT : STD_LOGIC;
signal sNTRUE : STD_LOGIC;
signal sP_Z_BUS,sN_Z_BUS : STD_LOGIC_VECTOR(0 to 8);
signal sALU_CHK_LCH : STD_LOGIC;
signal sZ_HI_0, sZ_LO_0, sZ_0 : STD_LOGIC;
signal sMACH_RST_2, sMACH_RST_2A : STD_LOGIC;
signal sGT_CARRY_TO_S3 : STD_LOGIC;
signal SI_LCH_Set,STI_LCH_Set,Z0C1C0_LCH,PC7_LCH_Set,PC7_LCH_Reset,
NC7_LCH_Set,A_LCH_L,B_LCH_L,NS3_LCH_Set,NS3_LCH_Reset,EVEN_LCH_Set,EVEN_LCH_Reset,AC_LCH_Set,AC_LCH_Reset : STD_LOGIC;
signal sCARRY_0_LATCHED, sALU_CHK : STD_LOGIC; -- Debug
BEGIN
-- Fig 5-06A
-- A REGISTER, B REGISTER INDICATORS
IND_A <= "111111111" when LAMP_TEST='1' else A_REG;
IND_B <= "111111111" when LAMP_TEST='1' else B_REG;
A_REG_PC <= EvenParity(A_REG); -- AB2H2
B_REG_PC <= EvenParity(B_REG); -- AB2J2
-- IMMED STAT REG
SI_LCH_Set <= SERV_IN_SIG and not T_REQUEST;
SI_LCH: PH port map(SI_LCH_Set,T3,SERV_IN_LCHD); -- AB2D6
STI_LCH_Set <= STAT_IN_SIG and not T_REQUEST;
STI_LCH: PH port map(STI_LCH_Set,T3,STATUS_IN_LCHD); -- AB2D6
OI_LCH: PH port map(OPNL_IN,T3,OPNL_IN_LCHD); -- AB2D6
AI_LCH: PH port map(ADDR_IN,T3,ADDR_IN_LCHD); -- AB2D6
Z0C1C0_LCH <= T4 or RECYCLE_RST;
Z0_LCH: PH port map(sZ_0,Z0C1C0_LCH,Z0_BUS_0); -- AB2D6
C1_LCH: PH port map(P_CARRY(1),Z0C1C0_LCH,CARRY_1_LCHD); -- AB2D6
C0_LCH: PH port map(P_CARRY(0),Z0C1C0_LCH,sCARRY_0_LATCHED); -- AB2D6
CARRY_0_LATCHED <= sCARRY_0_LATCHED;
-- ALU INDICATORS
IND_ALU <= "111111111" when LAMP_TEST='1' else sP_Z_BUS;
-- CARRY IN LATCHES
CARRY_S3 <= '1' when CC="110" else '0'; -- AB2E7
INSERT_CARRY <= '1' when (CC="001") or (CC="101") else '0'; -- AB2E6
INSERT_0_CARRY <= '1' when (CC="000") or (CC="010") or (CC="011") or (CC="100") or (CC="111") else '0'; -- AB2E7
PC7_LCH_Set <= (S_REG_3 and CARRY_S3 and P1) or (P1 and INSERT_CARRY);
PC7_LCH_Reset <= MANUAL_STORE or T1 or RECYCLE_RST;
PC7_LCH: FLL port map(PC7_LCH_Set,PC7_LCH_Reset,P_CARRY_IN_7); -- AB2F3,AB2E4
NC7_LCH_Set <= (NOT_S3 and CARRY_S3 and P1) or (P1 and INSERT_0_CARRY) or RECYCLE_RST or MANUAL_STORE;
NC7_LCH: FLL port map(NC7_LCH_Set,T1,N_CARRY_IN_7); -- AB2F3,AB2E4
-- ALU CHECK
sALU_CHK <= '1' when (P_Z_ALU_BUS xor N_Z_ALU_BUS)/="11111111" or (P_SUMS(0) = N_SUMS(0)) or (P_SUMS(4) = N_SUMS(4)) or (P_CARRY(0) = N_CARRY(0)) else '0'; -- AB2D3,AB2D4,AB2E4
ALU_CHK <= sALU_CHK;
-- Fig 5-06B
-- A REG and B REG
A_LCH_L <= MAN_STOR_OR_DSPLY or MACH_RST_SET_LCH or T1;
A_LCH: PHV9 port map(not A_BUS,A_LCH_L,A_REG); -- AB1J5,AB1K7
B_LCH_L <= MACH_RST_SET_LCH or T1 or MANUAL_STORE;
B_LCH: PHV9 port map(B_BUS,B_LCH_L,B_REG); -- AB1J5,AB1L5
-- ALU B entry
sNTRUE <= '1' when (CV(0)='1' and S_REG_0='0') or CV="00" else '0'; -- AB2K7
NTRUE <= sNTRUE;
COMPLEMENT <= '1' when (CV(0)='1' and S_REG_0='1') or CV="01" else '0'; -- AB2L7
HEX <= '1' when CV(0)='0' or CV(1)='0' else '0'; -- AB2J7
sDECIMAL <= '1' when CV="11" else '0'; -- AB2H7
DECIMAL <= sDECIMAL;
HSEL <= GT_B_REG_HI & sDECIMAL & sNTRUE;
with HSEL select P_ALU_B_IN(0 to 3) <=
B_REG(0 to 3) + "0110" when "111", -- Spec A1
B_REG(0 to 3) when "101", -- Spec A2
not B_REG(0 to 3) when "100"|"110", -- Spec A3
"0110" when "011", -- Spec A4 ???
"1111" when "000"|"010", -- Spec A5
"0000" when others
;
LSEL <= GT_B_REG_LO & sDECIMAL & sNTRUE;
with LSEL select P_ALU_B_IN(4 to 7) <=
B_REG(4 to 7) + "0110" when "111", -- Spec A1
B_REG(4 to 7) when "101", -- Spec A2
not B_REG(4 to 7) when "100"|"110", -- Spec A3
"0110" when "011", -- Spec A4 ???
"1111" when "000"|"010", -- Spec A5
"0000" when others
;
N_ALU_B_IN <= not P_ALU_B_IN;
-- ALU A entry
P_ALU_A_IN(0 to 3) <=
((0 to 3 => not CROSSED) or A_REG(4 to 7)) and
((0 to 3 => not STRAIGHT) or A_REG(0 to 3)) and
(0 to 3 => GT_A_HI);
P_ALU_A_IN(4 to 7) <=
((4 to 7 => not CROSSED) or A_REG(0 to 3)) and
((4 to 7 => not STRAIGHT) or A_REG(4 to 7)) and
(4 to 7 => GT_A_LO);
N_ALU_A_IN(0 to 3) <=
not(((0 to 3 => GT_A_HI and STRAIGHT) and A_REG(0 to 3)) or
((0 to 3 => GT_A_HI and CROSSED) and A_REG(4 to 7))); -- ?? GT_A_HI is missing in MDM
N_ALU_A_IN(4 to 7) <=
not(((4 to 7 => GT_A_LO and STRAIGHT) and A_REG(4 to 7)) or
((4 to 7 => GT_A_LO and CROSSED) and A_REG(0 to 3)));
-- ALU
P_CONNECT <= '1' when (CC(0)='0' and CC(1)='1') or (CC(1)='1' and CC(2)='1') else '0'; -- AB2D7,AB2F7 CC=01X or CC=X11 i.e. 010 011 111
-- N_CONNECT <= '1' when (CC(0)/='0' or CC(1)/='1') and (CC(1)/='1' or CC(2)/='1') else '0'; -- AB2G7 i.e. 000 001 100 101 110www.typeupsidedown.
P_CTRL_N <= '1' when CC(1)='0' or CC(0)='1' else '0'; -- AB2D7,AB2F7 CC=X0X or 1XX ie. 000 001 100 101 110 111
N_CTRL_N <= '1' when CC(0)/='1' and CC(1)/='0' else '0'; -- AB2G7 CC=1XX nor CC=X0X ==> CC\=1XX and CC\=X0X i.e. 010 or 011
N_CTRL_LM <= '1' when CC/="010" else '0'; -- AB2G7
-- P_CTRL_LM <= '1' when CC="010" else '0'; -- AB2H7
-- CC functions
-- 000 Add, Carry in 0, Ignore Carry out
-- 001 Add, Carry in 1, Ignore Carry out
-- 010 And, Ignore Carry out
-- 011 Or, Ignore Carry out
-- 100 Add, Carry in 0, Set S3 to 1 on Carry out
-- 101 Add, Carry in 1, Set S3 to 1 on Carry out
-- 110 Add, Carry in from S3, Set S3 to 1 on Carry out
-- 111 Xor, Ignore Carry out
-- ALU P
with CC select P_SUMS <= -- AB2J6,AB2H6,AB2G6,AB2F6,AB2J5,AB2H5,AB2G5,AB2F5
P_ALU_A_IN and P_ALU_B_IN when "010",
P_ALU_A_IN or P_ALU_B_IN when "011",
P_ALU_A_IN xor P_ALU_B_IN when "111",
P_ALU_A_IN xor P_ALU_B_IN xor P_CARRY(1 to 7) & P_CARRY_IN_7 when others;
with CC select P_CARRY <=
"00000000" when "010"|"011"|"111",
(P_ALU_A_IN and P_ALU_B_IN) or
(P_ALU_A_IN and P_CARRY(1 to 7) & P_CARRY_IN_7) or
(P_ALU_B_IN and P_CARRY(1 to 7) & P_CARRY_IN_7) when others; -- Ripple carry
CARRY_0 <= P_CARRY(0);
sINTRODUCE_ALU_CHK <= DIAG_SW and sALU_CHK_LCH; -- AE3H5,AB3F6,AB3F7
INTRODUCE_ALU_CHK <= sINTRODUCE_ALU_CHK;
-- ALU N
with CC select N_SUMS <= -- AB2J6,AB2H6,AB2G6,AB2F6,AB2J5,AB2H5,AB2G5,AB2F5
(N_ALU_A_IN or N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "010",
(N_ALU_A_IN and N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "011",
(N_ALU_A_IN xnor N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "111",
(N_ALU_A_IN xor N_ALU_B_IN xor N_CARRY(1 to 7) & N_CARRY_IN_7) or (0 to 7 => sINTRODUCE_ALU_CHK) when others;
with CC select N_CARRY <=
"11111111" and (0 to 7 => not sINTRODUCE_ALU_CHK) when "010"|"011"|"111",
((N_ALU_A_IN and N_ALU_B_IN) or
(N_ALU_A_IN and N_CARRY(1 to 7) & N_CARRY_IN_7) or
(N_ALU_B_IN and N_CARRY(1 to 7) & N_CARRY_IN_7)) and (0 to 7 => not sINTRODUCE_ALU_CHK) when others;
-- Debug
DBG_P_ALU_A_IN <= P_ALU_A_IN;
DBG_P_ALU_B_IN <= P_ALU_B_IN;
DBG_P_ALU_CARRY <= P_CARRY;
DBG_P_ALU_SUMS <= P_SUMS;
DBG_N_ALU_A_IN <= N_ALU_A_IN;
DBG_N_ALU_B_IN <= N_ALU_B_IN;
DBG_N_ALU_CARRY <= N_CARRY;
DBG_N_ALU_SUMS <= N_SUMS;
sGT_CARRY_TO_S3 <= '1' when CC="100" or CC="101" or CC="110" else '0'; -- AB2E6
GT_CARRY_TO_S3 <= sGT_CARRY_TO_S3;
-- Debug
NOT_S3 <= not S_REG_3;
-- NS3_LCH_Set <= (N_CARRY(0) and T4 and sGT_CARRY_TO_S3) or S_REG_RST;
-- NS3_LCH_Reset <= (sGT_CARRY_TO_S3 and T4 and P_CARRY(0)) or (GT_Z_BUS_TO_S_REG and sP_Z_BUS(3));
-- NS3_LCH: FLE port map(NS3_LCH_Set,NS3_LCH_Reset,clk,NOT_S3); -- AB2E3
-- Temp Debug
P_Z_ALU_BUS(0 to 3) <= ((0 => sODD and HEX, 1 to 3 => HEX) and P_SUMS(0 to 3)) or
((0 to 3 => P_CARRY(0) and sDECIMAL) and P_SUMS(0 to 3)) or
((0 to 3 => N_CARRY(0) and sDECIMAL) and (P_SUMS(0 to 3) - "0110"));
N_Z_ALU_BUS(0 to 3) <= ((0 to 3 => HEX) and N_SUMS(0 to 3)) or
((0 to 3 => sDECIMAL and P_CARRY(0)) and N_SUMS(0 to 3)) or
((0 to 3 => sDECIMAL and N_CARRY(0)) and (N_SUMS(0 to 3) + "0110"));
P_Z_ALU_BUS(4 to 7) <= ((4 => sODD and HEX, 5 to 7 => HEX) and P_SUMS(4 to 7)) or
((4 to 7 => P_CARRY(4) and sDECIMAL) and P_SUMS(4 to 7)) or
((4 to 7 => N_CARRY(4) and sDECIMAL) and (P_SUMS(4 to 7) - "0110"));
N_Z_ALU_BUS(4 to 7) <= ((4 to 7 => HEX) and N_SUMS(4 to 7)) or
((4 to 7 => sDECIMAL and P_CARRY(4)) and N_SUMS(4 to 7)) or
((4 to 7 => sDECIMAL and N_CARRY(4)) and (N_SUMS(4 to 7) + "0110"));
sP_Z_BUS <= P_Z_ALU_BUS & EvenParity(P_Z_ALU_BUS & EVEN); -- AB3C4
-- Note N_Z parity is not inverted, so is the same as P_Z
-- This may force a parity error when INTRODUCE_ALU_CHK is active,
-- depending on the value of P_Z. This parity error into R is required
-- for Diag B73 to work
sN_Z_BUS <= N_Z_ALU_BUS & EvenParity(P_Z_ALU_BUS & EVEN);
P_Z_BUS <= sP_Z_BUS;
N_Z_BUS <= sN_Z_BUS;
Z_BUS_LO_DIGIT_PARITY <= EvenParity(P_Z_ALU_BUS(4 to 7)); -- AB3C4
sZ_HI_0 <= '1' when sP_Z_BUS(0 to 3)="0000" else '0'; -- AB2E5
Z_HI_0 <= sZ_HI_0;
sZ_LO_0 <= '1' when sP_Z_BUS(4 to 7)="0000" else '0'; -- AB2E5
Z_LO_0 <= sZ_LO_0;
sZ_0 <= sZ_HI_0 and sZ_LO_0; -- AB2D5
Z_0 <= sZ_0;
sMACH_RST_2 <= sZ_0 and RECYCLE_RST; -- AB3C5
MACH_RST_2A_DELAY: AR port map(D=>sMACH_RST_2,Clk=>Clk,Q=>sMACH_RST_2A);
MACH_RST_2A <= sMACH_RST_2A;
MACH_RST_2B <= sMACH_RST_2A;
MACH_RST_2C <= sMACH_RST_2A;
DIAG_TEST_BIT <= '1' when SALS.SALS_CK="1000" and SALS.SALS_AK='1' else '0'; -- AB3E7
EVEN_LCH_Set <= T2 and DIAG_TEST_BIT and not sALU_CHK_LCH;
EVEN_LCH_Reset <= (T2 and sALU_CHK_LCH) or RST_LOAD or SYSTEM_RST_PRIORITY_LCH or RECYCLE_RST; -- ?? *not* SYSTEM_RST_PRIORITY_LCH ??
EVEN_LCH: FLL port map(EVEN_LCH_Set,EVEN_LCH_Reset,EVEN); -- AB3E5,AB3G2
sODD <= not EVEN;
ODD <= sODD;
AC_LCH_Set <= EVEN and DIAG_TEST_BIT and T1;
AC_LCH_Reset <= RECYCLE_RST or RST_LOAD or (ROS_SCAN and GT_SWS_TO_WX_PWR);
AC_LCH: FLL port map(AC_LCH_Set,AC_LCH_Reset,sALU_CHK_LCH); -- AG3G7,AB3G2
ALU_CHK_LCH <= sALU_CHK_LCH;
-- Debug
DEBUG <= '1' when NC7_LCH_Set='1' else '0';
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-06C-D.vhd
-- Creation Date: 11/08/05
-- Description:
-- R Register and assembly, Main and Local (Auxiliary, Bump) Storage
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RREG_STG IS
port
(
-- Inputs
SALS : IN SALS_Bus;
CTRL : IN CTRL_REG;
SX2_RD_CYCLE : IN STD_LOGIC; -- 14D
SEL_T3 : IN STD_LOGIC;
GT_DETECTORS_TO_HR : IN STD_LOGIC; -- 14D
SEL_DATA_READY : IN STD_LOGIC; -- 03B
SEL_R_W_CTRL : IN STD_LOGIC; -- 12C
SX2_WR_CYCLE : IN STD_LOGIC; -- 14D
SX1_RD_CYCLE : IN STD_LOGIC; -- 12D
SX1_WR_CYCLE : IN STD_LOGIC; -- 12D
GT_DETECTORS_TO_GR : IN STD_LOGIC; -- 12D
EVEN_HR_0_7_BITS : IN STD_LOGIC; -- 13A
EVEN_GR_0_7_BITS : IN STD_LOGIC; -- 11A
HR_REG_0_7 : IN STD_LOGIC_VECTOR(0 TO 7); -- 13C
GR_REG_0_7 : IN STD_LOGIC_VECTOR(0 TO 7); -- 11C
DR_CORR_P_BIT : IN STD_LOGIC := '0'; -- HSMPX
HR_REG_P_BIT : IN STD_LOGIC; -- 13A
GR_REG_P_BIT : IN STD_LOGIC; -- 11A
STORE_HR : IN STD_LOGIC; -- 14D
STORE_GR : IN STD_LOGIC; -- 12D
STORE_R : IN STD_LOGIC; -- 03D
MEM_SELECT : IN STD_LOGIC; -- 03D
MAN_STORE_PWR : IN STD_LOGIC; -- 03D
E_SW_SEL_R : IN STD_LOGIC; -- 04C
GT_HSMPX_INTO_R_REG : IN STD_LOGIC := '0'; -- HSMPX
HSMPX_BUS : IN STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- HSMPX
COMPUTE_CY_LCH : IN STD_LOGIC; -- 01C
CLOCK_OFF : IN STD_LOGIC; -- 08A
ALLOW_WRITE_1 : IN STD_LOGIC; -- 03D
PROT_LOC_CPU_OR_MPX : IN STD_LOGIC; -- 08B
USE_R : IN STD_LOGIC; -- 04D
MANUAL_DISPLAY : IN STD_LOGIC; -- 03D
MAN_STORE : IN STD_LOGIC; -- 03D
DATA_READY : IN STD_LOGIC; -- 03A
MACH_RST_SET_LCH_DLY : IN STD_LOGIC; -- 04B
SEL_SHARE_CYCLE : IN STD_LOGIC; -- 12D
MN_REG_CHK_SMPLD : IN STD_LOGIC; -- 07A
MEM_WRAP : IN STD_LOGIC; -- 03B
MAIN_STG : IN STD_LOGIC; -- 04D
MACH_RST_2A : IN STD_LOGIC; -- 06B
MACH_RST_6 : IN STD_LOGIC; -- 03D
ALLOW_WRITE : IN STD_LOGIC; -- 03D
-- STORAGE_BUS : IN STD_LOGIC_VECTOR(0 TO 8); -- 06D/07D -- Included here
CPU_SET_ALLOW_WR_LCH : IN STD_LOGIC; -- 03D
N1401_MODE : IN STD_LOGIC; -- 05A
MACH_RST_SW : IN STD_LOGIC; -- 03D
MN : IN STD_LOGIC_VECTOR(0 to 15); -- 07B
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 8);
USE_MAIN_MEM,USE_LOC_MAIN_MEM : IN STD_LOGIC; -- 05D
READ_1,READ_2,WRITE_1,WRITE_2 : IN STD_LOGIC := '0'; -- 05D Unused
PHASE_RD_1,PHASE_RD_2,PHASE_WR_1,PHASE_WR_2 : IN STD_LOGIC; -- 05D
-- Outputs
R_0 : OUT STD_LOGIC; -- 02A
R_REG_BUS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 05C
P_8F_DETECTED : OUT STD_LOGIC; -- 03A
ALLOW_PROTECT : OUT STD_LOGIC; -- 03A7
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
-- Clocks
-- P3 : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END RREG_STG;
ARCHITECTURE FMD OF RREG_STG IS
TYPE MAIN_STG_TYPE is ARRAY(0 to 8191) of STD_LOGIC_VECTOR(0 to 8);
TYPE LOCAL_STG_TYPE is ARRAY(0 to 511) of STD_LOGIC_VECTOR(0 to 8);
SIGNAL SX1_STOR,SX2_STOR : STD_LOGIC;
SIGNAL INPUT_CORRECTED_P_BIT : STD_LOGIC;
SIGNAL GRP, HRP : STD_LOGIC;
SIGNAL INH_Z_BUS_SET_R : STD_LOGIC;
SIGNAL PROTECT_MEMORY : STD_LOGIC;
SIGNAL STORE_MAN : STD_LOGIC;
SIGNAL FORCE_Z_SET_R, FORCE_Z_SET_R2 : STD_LOGIC;
SIGNAL GT_R_1,GT_R : STD_LOGIC;
SIGNAL R_REG : STD_LOGIC_VECTOR(0 TO 8) := "000000001";
SIGNAL DET0F : STD_LOGIC;
SIGNAL GMWM_DETECTED : STD_LOGIC;
SIGNAL FORCE_MEM_SET_R,MEM_SET_R, MEM_SET_R2 : STD_LOGIC;
SIGNAL R_MUX,STORAGE_BUS : STD_LOGIC_VECTOR(0 to 8);
SIGNAL sALLOW_PROTECT : STD_LOGIC;
signal sSTORE_BITS : STD_LOGIC_VECTOR(0 to 8);
signal SX1_STOR_INPUT_DATA_Set,SX1_STOR_INPUT_DATA_Reset,SX2_STOR_INPUT_DATA_Set,SX2_STOR_INPUT_DATA_Reset,
PROT_MEM_Set,PROT_MEM_Reset,P_8F_DETECT_Set,P_8F_DETECT_Reset : STD_LOGIC;
SIGNAL LOCAL_STG_ARRAY : LOCAL_STG_TYPE := (
336 => "000000001",
337 => "000000001",
338 => "000000001",
339 => "010111010", -- R5 = 0000005D
368 => "000000001",
369 => "000000001",
370 => "000000001",
371 => "100110011", -- R7 = 00000099
others => "000000001"
);
SIGNAL MAIN_STG_ARRAY : MAIN_STG_TYPE := (
16#000# => "000000001", -- 00
16#001# => "000000010", -- 01
16#002# => "000000001", -- 00
16#003# => "000000001", -- 00
16#004# => "000000001", -- 00
16#005# => "000000001", -- 00
16#006# => "000000010", -- 01
16#007# => "000000001", -- 00
16#008# => "110100110", -- L
16#009# => "110100011", -- J
16#00A# => "111001100", -- W
16#00B# => "111100100", -- 2
16#00C# => "111100001", -- 0
16#00D# => "111100110", -- 3
16#00E# => "111100001", -- 0
-- The following program is from p73 of the System/360 programming tutorial
-- The "Indian" problem
-- Compound interest on $24 (price of Manhattan) at 3% for 338 years = $523998.22
16#100# => "000001011", -- 05 BALR 11,0
16#101# => "101100000", -- B0
16#102# => "111100100", -- F2
16#103# => "011000111", -- 63
16#104# => "101100000", -- B0
16#105# => "010010100", -- 4A
16#106# => "101100000", -- B0
16#107# => "010000000", -- 40
16#108# => "111100100", -- F2
16#109# => "000100101", -- 12
16#10A# => "101100000", -- B0
16#10B# => "010100010", -- 51
16#10C# => "101100000", -- B0
16#10D# => "010001001", -- 44
16#10E# => "111100100", -- F2
16#10F# => "011100101", -- 72
16#110# => "101100000", -- B0
16#111# => "010101101", -- 56
16#112# => "101100000", -- B0
16#113# => "010001111", -- 47
16#114# => "010011110", -- 4F
16#115# => "010000000", -- 40
16#116# => "101100000", -- B0
16#117# => "010101101", -- 56
16#118# => "111111001", -- FC
16#119# => "011000010", -- 61
16#11A# => "101100000", -- B0
16#11B# => "010010100", -- 4A
16#11C# => "101100000", -- B0
16#11D# => "010100010", -- 51
16#11E# => "111110101", -- FA
16#11F# => "011000010", -- 61
16#120# => "101100000", -- B0
16#121# => "010010100", -- 4A
16#122# => "101100000", -- B0
16#123# => "010111100", -- 5E
16#124# => "110100011", -- D1
16#125# => "000000001", -- 00
16#126# => "101100000", -- B0
16#127# => "010011110", -- 4F
16#128# => "101100000", -- B0
16#129# => "010100001", -- 50
16#12A# => "110100101", -- D2
16#12B# => "000001011", -- 05
16#12C# => "101100000", -- B0
16#12D# => "011000001", -- 60
16#12E# => "101100000", -- B0
16#12F# => "010010100", -- 4A
16#130# => "111110000", -- F8
16#131# => "011001011", -- 65
16#132# => "101100000", -- B0
16#133# => "010010100", -- 4A
16#134# => "101100000", -- B0
16#135# => "011000001", -- 60
16#136# => "010001100", -- 46
16#137# => "010000000", -- 40
16#138# => "101100000", -- B0
16#139# => "000101100", -- 16
16#13A# => "111100111", -- F3
16#13B# => "100001100", -- 86
16#13C# => "101100000", -- B0
16#13D# => "011001101", -- 66
16#13E# => "101100000", -- B0
16#13F# => "010010100", -- 4A
16#140# => "000001110", -- 07 BCR 15,11
16#141# => "111110110", -- FB
16#142# => "111100100", -- F2
16#143# => "111101000", -- F4
16#144# => "111100001", -- F0
16#145# => "110000001", -- C0
16#146# => "111100010", -- F1
16#147# => "111100001", -- F0
16#148# => "110000111", -- C3
16#149# => "111100111", -- F3
16#14A# => "111100111", -- F3
16#14B# => "110010000", -- C8
16#160# => "000001011", -- 05
16#161# => "000011001", -- 0C
others => "000000001"
);
signal dT1 : STD_LOGIC;
BEGIN
-- Fig 5-06C
SX2_STOR_INPUT_DATA_Set <= SX2_RD_CYCLE and SEL_T3;
SX2_STOR_INPUT_DATA_Reset <= (GT_DETECTORS_TO_HR and SEL_DATA_READY) or (not SEL_R_W_CTRL and not SX2_WR_CYCLE);
SX2_STOR_INPUT_DATA: FLL port map(SX2_STOR_INPUT_DATA_Set,SX2_STOR_INPUT_DATA_Reset,SX2_STOR); -- AE1G3,AE1L3
SX1_STOR_INPUT_DATA_Set <= SX1_RD_CYCLE and SEL_T3;
SX1_STOR_INPUT_DATA_Reset <= (GT_DETECTORS_TO_GR and SEL_DATA_READY) or (not SEL_R_W_CTRL and not SX1_WR_CYCLE);
SX1_STOR_INPUT_DATA: FLL port map(SX1_STOR_INPUT_DATA_Set,SX1_STOR_INPUT_DATA_Reset,SX1_STOR); -- AD2E4,AD2G4
INPUT_CORRECTED_P_BIT <= (SX2_STOR and EVEN_HR_0_7_BITS) or (SX1_STOR and EVEN_GR_0_7_BITS) or DR_CORR_P_BIT; -- AD2G4,AA1E7
HRP <= not SX2_STOR and HR_REG_P_BIT and STORE_HR; -- AA1F7
GRP <= not SX1_STOR and GR_REG_P_BIT and STORE_GR; -- AA1F7
sSTORE_BITS <= ((HR_REG_0_7 & INPUT_CORRECTED_P_BIT) and (0 TO 8 => STORE_HR)) or -- AA1G7
((GR_REG_0_7 & INPUT_CORRECTED_P_BIT) and (0 TO 8 => STORE_GR)) or -- AA1G6
("00000000" & HRP) or
("00000000" & GRP) or
(R_REG and (0 to 8 => STORE_R)); -- AA1G5
STORE_BITS <= sSTORE_BITS;
R_REG_BUS <= R_REG;
R_0 <= R_REG(0); -- AA3K6
INH_Z_BUS_SET_R <= CLOCK_OFF or (ALLOW_WRITE_1 and PROT_LOC_CPU_OR_MPX) or (USE_R and PROTECT_MEMORY); -- AB3D5
FORCE_Z_SET_R <= STORE_HR or STORE_GR or STORE_MAN or (not T1 and COMPUTE_CY_LCH and not INH_Z_BUS_SET_R) or (SALS.SALS_CM(1) and not INH_Z_BUS_SET_R); -- AA1F7,AA1J5
Delay_ZSetR: AR port map(FORCE_Z_SET_R,clk,FORCE_Z_SET_R2);
STORE_MAN <= (MEM_SELECT and MAN_STORE_PWR) or (MAN_STORE_PWR and E_SW_SEL_R); -- AA1H6
GT_R_1 <= '1' when STORE_MAN='1' or (CTRL.CTRL_CD="0111" and not INH_Z_BUS_SET_R='1') else '0'; -- AA1H7,AA1J4
GT_R <= (GT_R_1 and T4) or (GT_R_1 and MAN_STORE) or (DATA_READY and MEM_SET_R) or MACH_RST_SET_LCH_DLY; -- AA1G4
-- Temp debug replacing above line - without this the diags stop at B96 because ASCII latch never gets set
-- GT_R <= (GT_R_1 and T4) or (GT_R_1 and MAN_STORE) or (DATA_READY and MEM_SET_R and MANUAL_DISPLAY) or (DATA_READY and MEM_SET_R and P3) or MACH_RST_SET_LCH_DLY; -- AA1G4
RREG: PHV9 port map(R_MUX,GT_R,R_REG); -- AA1H4
sALLOW_PROTECT <= '1' when ((SALS.SALS_CM="010") or (SALS.SALS_CD="0111")) else '0'; -- AA2J3,AA2G5,AA2K4 ?? Extra inverter not required ??
ALLOW_PROTECT <= sALLOW_PROTECT;
PROT_MEM_Set <= MN_REG_CHK_SMPLD or (T2 and MEM_WRAP and MAIN_STG);
PROT_MEM_Reset <= MACH_RST_6 or (not ALLOW_WRITE and T4);
PROT_MEM: FLL port map(PROT_MEM_Set,PROT_MEM_Reset,PROTECT_MEMORY); -- AB3F5,AB3H6
-- If we have a protection violation, we must retain the location's value in R so that it can be written back, even if
-- R contained a new value destined for that location
FORCE_MEM_SET_R <= MANUAL_DISPLAY or (PROT_LOC_CPU_OR_MPX and sALLOW_PROTECT) or (USE_R and PROTECT_MEMORY and sALLOW_PROTECT); -- AA3L5
-- The following line determines whether the storage output data is actually gated into the R register
-- If you can understand this then you can understand anything in the 2030
-- By the time DATA_READY is active, the next CCROS word has been read in and it is this word which controls the gating
-- The next cycle after a storage read must always be a WRITE, COMPUTE or STORE (i.e. it can't be another READ)
-- If it is a STORE then the data is NOT gated to R, as R is about to be written into to storage
-- As the following cycle is not a read then the Alt CU decode is used, and if it is "GR" then the data is NOT gated to R (but to GR/HR instead)
-- However, if storage protection is activated, then the storage value is ALWAYS put into R so it can be rewritten by the subsequent WRITE or STORE
-- (this is what FORCE_MEM_SET_R does)
-- So MEM_SET_R<='1' when CU=X0|1X (i.e. not 01=GR) and CM/=X1X (i.e. not 010=STORE)
MEM_SET_R <= (FORCE_MEM_SET_R or SALS.SALS_CU(0) or not SALS.SALS_CU(1)) and (not SALS.SALS_CM(1) or FORCE_MEM_SET_R) and not SEL_SHARE_CYCLE; -- AA1J5
Delay_MemSetR: AR port map(MEM_SET_R,clk,MEM_SET_R2);
-- Input data (0 to 7) is inverted
R_MUX(0 to 7) <= ((0 to 7 => FORCE_Z_SET_R2) and not N_Z_BUS(0 to 7)) or ((0 to 7 => GT_HSMPX_INTO_R_REG) and HSMPX_BUS(0 to 7)) or ((0 to 7 => MEM_SET_R2) and STORAGE_BUS(0 to 7)); -- AA1G2 AA1H4
-- Input parity (8) is not inverted
R_MUX(8) <= (FORCE_Z_SET_R2 and N_Z_BUS(8)) or (GT_HSMPX_INTO_R_REG and HSMPX_BUS(8)) or (MEM_SET_R2 and STORAGE_BUS(8)) or MACH_RST_2A; -- AA1G2,AA1H4,AA1H2
-- Word Mark detection for 1401 usage
DET0F <= '1' when (STORAGE_BUS(1 to 7) = "0001111") and (DATA_READY='1') else '0'; -- AA1B7
GMWM: FLL port map(DET0F,CPU_SET_ALLOW_WR_LCH,GMWM_DETECTED); -- AA1F5
P_8F_DETECT_Set <= STORAGE_BUS(0) and MAIN_STG and N1401_MODE and DET0F;
P_8F_DETECT_Reset <= MACH_RST_SW or GMWM_DETECTED;
P_8F_DETECT: FLL port map(P_8F_DETECT_Set,P_8F_DETECT_Reset,P_8F_DETECTED); -- AA1F5
STG_Wr: process (PHASE_WR_1)
begin
if (PHASE_WR_1'EVENT AND PHASE_WR_1='1') then
if (USE_MAIN_MEM='1') then
MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15)))) <= sSTORE_BITS;
else
LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15)))) <= sSTORE_BITS;
end if;
end if;
end process;
STG_Rd: process (PHASE_RD_1,USE_MAIN_MEM,MAIN_STG_ARRAY,LOCAL_STG_ARRAY,MN)
begin
if (PHASE_RD_1='1') then
if (USE_MAIN_MEM='1') then
STORAGE_BUS <= MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15))));
else
STORAGE_BUS <= LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15))));
end if;
else
STORAGE_BUS <= "000000000";
end if;
end process;
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07A1.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- MN (MSAR) indicators
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY MNInd IS
port
(
-- Inputs
MN : IN STD_LOGIC_VECTOR(0 to 15);
M_P, N_P : IN STD_LOGIC;
LAMP_TEST : IN STD_LOGIC; -- 04A
MAIN_STG,LOCAL_STG : IN STD_LOGIC; -- 04D
N1401_MODE : IN STD_LOGIC; -- 05A
-- Outputs
IND_M : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
IND_N : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
IND_MAIN_STG,IND_LOC_STG,IND_COMP_MODE : OUT STD_LOGIC;
MN_PC : OUT STD_LOGIC -- 06C,11A,13A
);
END MNInd;
ARCHITECTURE FMD OF MNInd IS
BEGIN
-- Fig 5-07A
IND_M <= "111111111" when LAMP_TEST='1' else MN(0 to 7) & M_P;
IND_N <= "111111111" when LAMP_TEST='1' else MN(8 to 15) & N_P;
IND_MAIN_STG <= MAIN_STG or LAMP_TEST;
IND_LOC_STG <= LOCAL_STG or LAMP_TEST;
IND_COMP_MODE <= N1401_MODE or LAMP_TEST;
MN_PC <= (EvenParity(MN(0 to 7) & M_P) or EvenParity(MN(8 to 15) & N_P)) and not LOCAL_STG; -- AA1C4,AA1C5,AA1E5,AA1E6,AA1C3,AA1J3
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07A2.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Check Register Indicators
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ChkRegInd IS
port
(
-- Inputs
LAMP_TEST : IN STD_LOGIC; -- 04A
GT_CA_TO_W_REG : IN STD_LOGIC; -- 02B
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02B
CA_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
ROS_SCAN : IN STD_LOGIC; -- 03C
MACH_CHK_PULSE : IN STD_LOGIC; -- 03A
GT_D_REG_TO_A_BUS : IN STD_LOGIC; -- 05C
MACH_RST_SW : IN STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
SET_IND_ROSAR : IN STD_LOGIC; -- 01A
MACH_RST_6 : IN STD_LOGIC; -- 03D
WX_CHK : IN STD_LOGIC; -- 01A
A_REG_PC,B_REG_PC : IN STD_LOGIC; -- 06A
N2ND_ERROR_STOP : IN STD_LOGIC; -- 03C
ALLOW_WRITE : IN STD_LOGIC; -- 03D
CTRL_REG_CHK : IN STD_LOGIC; -- 01A
SALS_PC : IN STD_LOGIC; -- 01A
R_REG_PC : IN STD_LOGIC; -- 05A
ALU_CHK : IN STD_LOGIC; -- 06A
CHK_SW_PROC_SW : IN STD_LOGIC; -- 04A
SUPPR_MACH_CHK_TRAP : IN STD_LOGIC; -- 03A
CPU_WR_IN_R_REG : IN STD_LOGIC; -- 03D
GT_Q_REG_TO_A_BUS : IN STD_LOGIC; -- 07C
STACK_PC : IN STD_LOGIC; -- 08B
MEM_PROT_REQUEST : IN STD_LOGIC; -- 03A
SEL_CHNL_CHK : IN STD_LOGIC; -- 11A
MACH_CHK_RST : IN STD_LOGIC; -- 04A
AK_SAL_BIT : IN STD_LOGIC; -- 01C
CK_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
MN_PC : IN STD_LOGIC;
N1401_MODE : IN STD_LOGIC;
-- Outputs
SUPPR_A_REG_CHK : OUT STD_LOGIC; -- 03A
ALLOW_PC_SALS : OUT STD_LOGIC; -- 01B
MN_REG_CHK_SMPLD : OUT STD_LOGIC; -- 06C
FIRST_MACH_CHK,FIRST_MACH_CHK_REQ : OUT STD_LOGIC; -- 03A,03C
ANY_MACH_CHK : OUT STD_LOGIC; -- 01A,03C,04A
IND_MC_A_REG,IND_MC_B_REG,IND_MC_STOR_ADDR,IND_MC_CTRL_REG,IND_MC_ROS_SALS,IND_MC_ROS_ADDR,IND_MC_STOR_DATA,IND_MC_ALU : OUT STD_LOGIC;
MC : OUT STD_LOGIC_VECTOR(0 to 7);
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END ChkRegInd;
ARCHITECTURE FMD OF ChkRegInd IS
signal W_REG_CHK : STD_LOGIC;
signal RST_MACH_CHK : STD_LOGIC;
signal MC_REG : STD_LOGIC_VECTOR(0 to 8);
signal SETMC : STD_LOGIC_VECTOR(0 to 7);
signal SET1ST : STD_LOGIC;
signal CAX1X1,CA0X11,CAX11X,CA1XXX : STD_LOGIC;
signal N_ALLOW_PC_SALS : STD_LOGIC;
signal ALLOW_A_REG_CHK : STD_LOGIC;
signal sSUPPR_A_REG_CHK : STD_LOGIC;
signal sALLOW_PC_SALS : STD_LOGIC;
signal sMN_REG_CHK_SMPLD : STD_LOGIC;
signal sANY_MACH_CHK : STD_LOGIC;
signal sMC : STD_LOGIC_VECTOR(0 to 7);
signal SUPR_A_REG_CHK_Set,SUPR_A_REG_CHK_Reset,ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,NOT_ALLOW_PC_SALS_Set : STD_LOGIC;
signal REG_MC_Set,REG_MC_Reset : STD_LOGIC_VECTOR(0 to 8);
BEGIN
-- Fig 5-07A
SUPR_A_REG_CHK_Set <= MACH_CHK_PULSE and T2;
SUPR_A_REG_CHK_Reset <= (GT_D_REG_TO_A_BUS and T1) or MACH_RST_SW;
SUPR_A_REG_CHK: FLE port map(SUPR_A_REG_CHK_Set,SUPR_A_REG_CHK_Reset,clk,sSUPPR_A_REG_CHK); -- AB3H3,AB3J4,AB3H4
SUPPR_A_REG_CHK <= sSUPPR_A_REG_CHK;
CAX1X1 <= CA_SALS(1) and CA_SALS(3); -- AB3G3
CA0X11 <= not CA_SALS(0) and CA_SALS(2) and CA_SALS(3); -- AB3J5
CAX11X <= CA_SALS(1) and CA_SALS(2); -- AB3F3
CA1XXX <= CA_SALS(0); -- AB3K5
-- MDM has USE_ALT with CAX1X1 which would check the Q reg which has no valid parity. Using USE_BASIC checks H reg instead
ALLW_A_REG_CHK_Set <= (P1 and USE_BASIC_CA_DECO and not GT_CA_TO_W_REG and CAX1X1) or -- AB3G3 ?? MDM has USE_ALT here ??
(USE_ALT_CA_DECODER and not GT_CA_TO_W_REG and CA0X11 and P1) or -- AB3J5
(CAX11X and not GT_CA_TO_W_REG and USE_BASIC_CA_DECO and P1) or -- AB3F3
(USE_BASIC_CA_DECO and CA1XXX and P1); -- AB3K5
ALLW_A_REG_CHK_Reset <= T1 or ROS_SCAN or sSUPPR_A_REG_CHK or ANY_PRIORITY_LCH;
ALLW_A_REG_CHK: FLL port map(ALLW_A_REG_CHK_Set,ALLW_A_REG_CHK_Reset,ALLOW_A_REG_CHK); -- AB3K5,AB3B6,AB3J4
NOT_ALLOW_PC_SALS_Set <= (SET_IND_ROSAR and T4) or MACH_RST_6;
NOT_ALLOW_PC_SALS: FLL port map(NOT_ALLOW_PC_SALS_Set,not T3,N_ALLOW_PC_SALS); -- AB3F6,AB3D7,AB3E5
sALLOW_PC_SALS <= not N_ALLOW_PC_SALS;
ALLOW_PC_SALS <= sALLOW_PC_SALS;
W_REG_CHK <= WX_CHK and not MACH_CHK_PULSE; -- AB3F6,AB3B6
RST_MACH_CHK <= T1 and AK_SAL_BIT when CK_SALS="1011" else '0'; -- AB3E7,AB3H5
SETMC(0) <= ALLOW_A_REG_CHK and A_REG_PC and T3; -- AB3G4
SETMC(1) <= B_REG_PC and not N2ND_ERROR_STOP and T3; -- AB3G4
sMN_REG_CHK_SMPLD <= MN_PC and ALLOW_WRITE and T3; -- AB3G4
MN_REG_CHK_SMPLD <= sMN_REG_CHK_SMPLD;
SETMC(2) <= sMN_REG_CHK_SMPLD; -- AB3G4
SETMC(3) <= sALLOW_PC_SALS and T2 and CTRL_REG_CHK; -- AB3G5
SETMC(4) <= SALS_PC and sALLOW_PC_SALS and T2; -- AB3G5
SETMC(5) <= T2 and W_REG_CHK; -- AB3G5
SETMC(6) <= (T2 and R_REG_PC and (CPU_WR_IN_R_REG or N1401_MODE)) or
((not N2ND_ERROR_STOP or (GT_Q_REG_TO_A_BUS and not GT_CA_TO_W_REG)) and T2 and STACK_PC and MEM_PROT_REQUEST); -- AB3G6
SETMC(7) <= ALU_CHK and T4; -- AB3G6
sANY_MACH_CHK <= SETMC(0) or SETMC(1) or SETMC(2) or SETMC(3) or SETMC(4) or SETMC(5) or SETMC(6) or SETMC(7) or SEL_CHNL_CHK; -- AB3G4,AB3G5,AB3J4,AB3D7,AB3F4
ANY_MACH_CHK <= sANY_MACH_CHK;
SET1ST <= CHK_SW_PROC_SW and not SUPPR_MACH_CHK_TRAP and sANY_MACH_CHK; -- AB3G6
REG_MC_Set <= SETMC & SET1ST;
REG_MC_Reset <= (0 to 7 => MACH_CHK_RST or RST_MACH_CHK,8 => (T1 and MACH_CHK_PULSE) or MACH_CHK_RST or RST_MACH_CHK); -- AB3G7,AB3H6-removed??
REG_MC: FLVL port map(REG_MC_Set,REG_MC_Reset,MC_REG); -- AB3G4,AB3G5,AB3G6
sMC <= MC_REG(0 to 7);
MC <= sMC;
FIRST_MACH_CHK <= MC_REG(8);
FIRST_MACH_CHK_REQ <= MC_REG(8); -- AB3F6
IND_MC_A_REG <= sMC(0) or LAMP_TEST;
IND_MC_B_REG <= sMC(1) or LAMP_TEST;
IND_MC_STOR_ADDR <= sMC(2) or LAMP_TEST;
IND_MC_CTRL_REG <= sMC(3) or LAMP_TEST;
IND_MC_ROS_SALS <= sMC(4) or LAMP_TEST;
IND_MC_ROS_ADDR <= sMC(5) or LAMP_TEST;
IND_MC_STOR_DATA <= sMC(6) or LAMP_TEST;
IND_MC_ALU <= sMC(7) or LAMP_TEST;
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B1.vhd
-- Creation Date: 11/01/09
-- Description:
-- SAR (MSAR) and SA (Protection Stack Address) registers
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY SARSA IS
port
(
-- Inputs
M_ASSM_BUS,N_ASSM_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 05B
MACH_RST_SW : IN STD_LOGIC; -- 03D
MACH_RESET_SET_LCH_DLY : IN STD_LOGIC; -- 04B
MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
CPU_RD_PWR : IN STD_LOGIC; -- 04D
SEL_RDWR_CTRL : IN STD_LOGIC; -- 12C
GT_MAN_SET_MN : IN STD_LOGIC; -- 03D
CHNL_RD_CALL : IN STD_LOGIC; -- 04D
XH,XL,XXH : IN STD_LOGIC; -- 08C
MAIN_STORAGE_CP : IN STD_LOGIC; -- 08B
MPX_CP : IN STD_LOGIC; -- 08B
-- Outputs
MN, MN_ST3 : OUT STD_LOGIC_VECTOR(0 to 15);
M_P, N_P , M_ST3_P, N_ST3_P: OUT STD_LOGIC;
SA_REG : OUT STD_LOGIC_VECTOR(0 to 7);
EARLY_M0, M_REG_0 : OUT STD_LOGIC;
MACH_RST_PROTECT : OUT STD_LOGIC;
-- Clocks
T1 : IN STD_LOGIC;
SEL_T1 : IN STD_LOGIC
);
END SARSA;
ARCHITECTURE FMD OF SARSA IS
signal LATCH_MN, LATCH_MN_ST3 : STD_LOGIC;
signal sMACH_RST_PROTECT : STD_LOGIC;
signal STACK_ADDR_REG_SET: STD_LOGIC;
signal SA_REG_IN, SA_REG_IN1, SA_REG_IN2 : STD_LOGIC_VECTOR(0 to 7);
signal sMN : STD_LOGIC_VECTOR(0 to 15);
BEGIN
-- Fig 5-07B
sMACH_RST_PROTECT <= MACH_RST_SW; -- AA3H3
MACH_RST_PROTECT <= sMACH_RST_PROTECT;
LATCH_MN <= MACH_RESET_SET_LCH_DLY or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1D4
LATCH_MN_ST3 <= sMACH_RST_PROTECT or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1E4
REG_M: PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN,sMN(0 to 7)); -- AA1D2
REG_MP: PH port map(M_ASSM_BUS(8),LATCH_MN,M_P); -- AA1D2
REG_N: PHV8 port map(N_ASSM_BUS(0 to 7),LATCH_MN,sMN(8 to 15) ); -- AA1D3
REG_NP: PH port map(N_ASSM_BUS(8),LATCH_MN,N_P); -- AA1D3
REG_MST3: PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN_ST3,MN_ST3(0 to 7)); -- AA1D5
REG_MST3P: PH port map(M_ASSM_BUS(8),LATCH_MN_ST3,M_ST3_P); -- AA1D5
REG_NST3: PHV8 port map(N_ASSM_BUS(0 TO 7),LATCH_MN_ST3,MN_ST3(8 to 15)); -- AA1D6
REG_NST3P: PH port map(N_ASSM_BUS(8),LATCH_MN_ST3,N_ST3_P); -- AA1D6
STACK_ADDR_REG_SET <= CHNL_RD_CALL or (CPU_RD_PWR and T1) or GT_MAN_SET_MN or sMACH_RST_PROTECT; -- BE3H7
SA_REG_IN1 <= "111" & M_ASSM_BUS(0 to 4) when MAIN_STORAGE_CP='1' else "00000000"; -- PE3J6
SA_REG_IN2 <= XXH & XL & XH & N_ASSM_BUS(0 to 4) when MPX_CP='1' else "00000000"; -- PE3J6
SA_REG_IN <= SA_REG_IN1 or SA_REG_IN2; -- PE3J6
REG_SA: PHV8 port map(SA_REG_IN,STACK_ADDR_REG_SET,SA_REG); -- PE3J6
MN <= sMN;
EARLY_M0 <= M_ASSM_BUS(0);
M_REG_0 <= sMN(0);
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B2.vhd
-- Creation Date: 01/11/09
-- Description:
-- S Register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY SReg IS
port
(
SA : IN STD_LOGIC; -- 01C
CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B
GT_CARRY_TO_S3 : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(0 to 7);
GT_Z_BUS_TO_S : OUT STD_LOGIC;
S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC; -- 01C
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
STORE_S_REG_RST : IN STD_LOGIC; -- 03D
E_SW_SEL_S : IN STD_LOGIC; -- 04C
MACH_RST_2C : IN STD_LOGIC; -- 06B
T_REQUEST : IN STD_LOGIC; -- 10BC6
FB_K_T2_PULSE : OUT STD_LOGIC;
CS_DECODE_X001 : OUT STD_LOGIC; -- 03C
BASIC_CS_0 : OUT STD_LOGIC; -- 03C
P1, T1, T2, T3, T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END SReg;
ARCHITECTURE FMD OF SReg IS
signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7);
signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC;
signal CD_0110 : STD_LOGIC;
signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC;
signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC;
signal sGT_Z_BUS_TO_S : STD_LOGIC;
signal sS_REG_RST : STD_LOGIC;
signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC;
signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-07B
CS_X000 <= '1' when CS(1 to 3)="000" else '0';
CS_X001 <= '1' when CS(1 to 3)="001" else '0';
CS_DECODE_X001 <= CS_X001;
CS_X010 <= '1' when CS(1 to 3)="010" else '0';
CS_X011 <= '1' when CS(1 to 3)="011" else '0';
CS_X100 <= '1' when CS(1 to 3)="100" else '0';
CS_X101 <= '1' when CS(1 to 3)="101" else '0';
CS_X110 <= '1' when CS(1 to 3)="110" else '0';
CS_X111 <= '1' when CS(1 to 3)="111" else '0';
CS_X01X <= '1' when CS(1 to 2)="01" else '0';
CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0';
CS_0XXX <= '1' when CS(0)='0' else '0';
CS_1XXX <= '1' when CS(0)='1' else '0';
GT_CS_OPT_Set <= SA and P1;
GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
BASIC_CS_0 <= sBASIC_CS_0;
FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3
CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6
sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S;
sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
S_REG_RST <= sS_REG_RST;
SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7
SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7
SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7
SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7
SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7
SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7
SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7
SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7
RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7
RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7
RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7
RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7
RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS);
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS);
S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- A Register Assembly
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ARegAssm IS
port
(
-- Inputs
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03D
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02A
E_SEL_SW_BUS : IN E_SW_BUS_Type; -- 04C
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
CHK_SW_DISABLE : IN STD_LOGIC; -- 04A
S : IN STD_LOGIC_VECTOR(0 to 7); -- 07B
MC_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 7); -- 07A
Q_REG : IN STD_LOGIC_VECTOR(0 to 8); -- 08B
SEL_CHNL_GJ_BUS : IN STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- 11B
GT_GJ_TO_A_REG : IN STD_LOGIC := '0'; -- 12C
-- Outputs
-- GT_DDC_TO_A_BUS : OUT STD_LOGIC; -- 07A
GT_Q_REG_TO_A_BUS : OUT STD_LOGIC; -- 07A
A_BUS : INOUT STD_LOGIC_VECTOR(0 to 8)
);
END ARegAssm;
ARCHITECTURE FMD OF ARegAssm IS
signal GT_MC_REG_TO_A_BUS : STD_LOGIC;
signal sGT_Q_REG_TO_A_BUS : STD_LOGIC;
signal sGT_DDC_TO_A_BUS : STD_LOGIC;
signal GT_S_REG_TO_A : STD_LOGIC;
signal JI_REG : STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- BE3D5
BEGIN
-- Fig 5-07C
GT_MC_REG_TO_A_BUS <= '1' when USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0010" else '0'; -- AB1F5
sGT_Q_REG_TO_A_BUS <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.Q_SEL='1') or (USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0101") else '0'; -- AB3C7
GT_Q_REG_TO_A_BUS <= sGT_Q_REG_TO_A_BUS;
sGT_DDC_TO_A_BUS <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.JI_SEL='1') or (USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0110") else '0'; -- AB3C7
-- GT_DDC_TO_A_BUS <= sGT_DDC_TO_A_BUS;
GT_S_REG_TO_A <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.S_SEL='1') or (USE_BASIC_CA_DECO='1' and GTD_CA_BITS="0100") else '0'; -- AB3C3
A_BUS <= not(S & '0') when GT_S_REG_TO_A='1' else
not(MC_CTRL_REG & '0') when GT_MC_REG_TO_A_BUS='1' and CHK_SW_DISABLE='0' else -- ABJK6 AB3L6
not JI_REG when sGT_DDC_TO_A_BUS='1' else
not SEL_CHNL_GJ_BUS when GT_GJ_TO_A_REG='1' else
not Q_REG when sGT_Q_REG_TO_A_BUS='1' else -- AC2D2
"111111111";
-- A_REG_BUS_2 <= ((S & '0') and (A_REG_BUS_2'range => GT_S_REG_TO_A)) or ((MC_CTRL_REG & '0') and (A_REG_BUS_2'range => (GT_MC_REG_TO_A_BUS and not CHK_SW_DISABLE))); -- ABJK6 AB3L6
-- A_REG_BUS_3 <= (JI_REG and (A_REG_BUS_3'range => sGT_DDC_TO_A_BUS)) or (SEL_CHNL_GJ_BUS and (A_REG_BUS_3'range => GT_GJ_TO_A_REG)) or (Q_REG and (A_REG_BUS_3'range => GT_Q_REG_TO_A_BUS)); -- AC2D2
END FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08A1.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Clock generator - 4 phase (T1,T2,T3,T4 and P1,P2,P3,P4)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Gates_package.all;
entity Clock is Port (
-- Clock stuff
CLOCK_IN : in std_logic;
T1,T2,T3,T4 : out std_logic;
P1,P2,P3,P4 : out std_logic;
OSC_T_LINE : out std_logic; -- 12A
M_CONV_OSC : out std_logic; -- 03C
P_CONV_OSC : out std_logic; -- 03D,03C
M_CONV_OSC_2 : out std_logic; -- 03C
CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B
CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D
CLOCK_START : in std_logic; -- 03C
MACH_RST_3 : in std_logic; -- 03D
Sw_Slow : in std_logic -- '1' to run slow
);
end Clock;
architecture FMD of Clock is
-- Following 2 lines to run clock at 5.33MHz (standard)
-- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0);
subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0);
constant RATIOFast : DividerSize := "00000000000000000000001000"; -- 5 gives 10MHz => 720ns cycle
-- Following 2 lines to run clock at 5Hz
constant RATIOSlow : DividerSize := "00100010010101010001000000"; -- 5M gives 10Hz => 720ms cycle
constant ZERO : DividerSize := (others=>'0');
constant ONE : DividerSize := (0=>'1',others=>'0');
signal DIVIDER : DividerSize := (others=>'0');
signal DIVIDER_MAX : DividerSize;
signal OSC2,OSC,M_DLYD_OSC,DLYN_OSC,T1A,T2A,T3A,T4A,OSC2_DLYD : STD_LOGIC := '0';
-- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4);
signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001";
begin
-- Divide the 50MHz FPGA clock down
-- 1.5us storage cycle means T1-4 takes 750ns, or 1.33MHz
-- The clock to generate the four phases is therefore 2.66MHz
-- OSC2 is actually double the original oscillator (5.33MHz) as only one edge is used
DIVIDER_MAX <= RatioSlow when Sw_Slow='1' else RATIOFast;
OSC2 <= '1' when DIVIDER > '0' & DIVIDER_MAX(DIVIDER_MAX'left downto 1) else '0';
process (CLOCK_IN)
begin
if CLOCK_IN'event and CLOCK_IN='1' then
if DIVIDER>=DIVIDER_MAX then
DIVIDER <= ZERO;
else
DIVIDER <= DIVIDER + ONE;
end if;
end if;
end process;
-- AC1K6,AC1C6 Probably have to re-do this lot to get it work
--SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4);
--SETS(2) <= DLYD_OSC not CLK(4) and CLK(1);
--SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2);
--SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1';
--RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1';
--RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1';
--RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1';
--RSTS(4) <= OSC and CLK(1);
--FLV(SETS,RSTS,CLK); -- AC1C6
-- The following process forms a ring counter
-- MACH_RST_3 forces the counter to 0001
-- If CLOCK_START is false, the counter stays at 0001
-- When CLOCK_START goes true, the counter cycles through
-- 0001 0001 0001 1001 1100 0110 0011 1001 1100 ....
-- When CLOCK_START subsequently goes false, the sequence continues
-- until reaching 0011, after which it stays at 0001
-- ... 1001 1100 0110 0011 0001 0001 0001 ...
-- The original counter used a level-triggered implementation, driven by
-- both levels of the OSC signal. Here it is easier to make it edge triggered
-- which requires a clock of twice the frequency, hence OSC2
process (OSC2, MACH_RST_3, CLOCK_START)
begin
if OSC2'event and OSC2='1' then
if OSC='0' then -- OSC Rising edge: +P1 (P4=1 & START) -P3 (P4=1) or -P1 +P3 (P2=1)
OSC <= '1';
if CLK(2)='1' or MACH_RST_3='1' then
CLK(1) <= '0';
elsif CLOCK_START='1' and CLK(4)='1' then
CLK(1) <= '1';
end if;
if CLK(4)='1' or MACH_RST_3='1' then
CLK(3) <= '0';
elsif CLK(2)='1' then
CLK(3) <= '1';
end if;
else -- OSC Falling edge: +P2 -P4 (P1=1) or -P2 +P4 (P3=1)
OSC <= '0';
if CLK(3)='1' or MACH_RST_3='1' then
CLK(2) <= '0';
elsif CLK(1)='1' then
CLK(2) <= '1';
end if;
if CLK(3)='1' or MACH_RST_3='1' then
CLK(4) <= '1';
elsif CLK(1)='1' then
CLK(4) <= '0';
end if;
end if;
end if;
end process;
OSC_T_LINE <= OSC; -- AC1B6
M_CONV_OSC <= not OSC; -- AC1C6
M_DLYD_OSC <= not OSC; -- AC1C6
DLYN_OSC <= OSC; -- AC1C6
P1 <= CLK(1);
P2 <= CLK(2);
P3 <= CLK(3);
P4 <= CLK(4);
T1 <= CLK(4) and CLK(1);
T2 <= CLK(1) and CLK(2);
T3 <= CLK(2) and CLK(3);
T4 <= CLK(3) and CLK(4);
CLOCK_ON <= CLK(1) or CLK(2) or CLK(3);
CLOCK_OFF <= not (CLK(1) or CLK(2) or CLK(3));
P_CONV_OSC <= OSC and not (CLK(1) or CLK(2) or CLK(3));
M_CONV_OSC_2 <= not(OSC and not (CLK(1) or CLK(2) or CLK(3)));
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08A2.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Multiplexor Channel Indicators
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MpxInd is Port (
-- Mpx Indicator stuff
TEST_LAMP : in std_Logic; -- 04A
OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN,
SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT,
SUPPRESS_OUT : in std_logic; -- 08D
FO_P : in std_logic; -- 08C
FO : in std_logic_vector(0 to 7); -- 08C
IND_OPNL_IN, IND_ADDR_IN,IND_STATUS_IN,IND_SERV_IN,
IND_SEL_OUT,IND_ADDR_OUT,IND_CMMD_OUT,IND_SERV_OUT,
IND_SUPPR_OUT,IND_FO_P : out std_logic;
IND_FO : out std_logic_vector(0 to 7)
);
end MpxInd;
architecture FMD of MpxInd is
begin
-- The indicator drivers for the Multiplexor channel are here
IND_OPNL_IN <= OPNL_IN or TEST_LAMP;
IND_ADDR_IN <= ADDR_IN or TEST_LAMP;
IND_STATUS_IN <= STATUS_IN or TEST_LAMP;
IND_SERV_IN <= SERVICE_IN or TEST_LAMP;
IND_SEL_OUT <= SELECT_OUT or TEST_LAMP;
IND_ADDR_OUT <= ADDR_OUT or TEST_LAMP;
IND_CMMD_OUT <= COMMAND_OUT or TEST_LAMP;
IND_SERV_OUT <= SERVICE_OUT or TEST_LAMP;
IND_SUPPR_OUT <= SUPPRESS_OUT or TEST_LAMP;
IND_FO_P <= FO_P or TEST_LAMP;
IND_FO <= FO or (FO'range => TEST_LAMP);
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08B.vhd
-- Creation Date: 21:55:54 27/01/2010
-- Description:
-- Q Register and Storage Protection
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Gates_package.all;
entity QReg_STP is
Port (
-- Inputs
SA_REG : in STD_LOGIC_VECTOR (0 to 7); -- Stack address, F0-FF are MS storage keys, 00-EF are CCW storage keys
Z_BUS : in STD_LOGIC_VECTOR (0 to 8); -- Z bus used to write to Q reg
SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : in STD_LOGIC; -- Selector channel cycle inputs
N_SEL_SHARE_HOLD : in STD_LOGIC; -- Selector channel share cycle
MAIN_STG : in STD_LOGIC; -- Main Storage usage
H_REG_5_PWR : in STD_LOGIC; -- Priority Reg from 04C
FORCE_M_REG_123 : in STD_LOGIC; -- When setting M reg for LS, from 04D
GT_LOCAL_STORAGE : in STD_LOGIC; -- Local Storage usage
GT_T_REG_TO_MN, GT_CK_TO_MN : in STD_LOGIC; -- These operations inhibit storage protect when used with LS
MAIN_STG_CP_1 : in STD_LOGIC; -- Main Storage clock pulse
N_MEM_SELECT : in STD_LOGIC;
N_STACK_MEMORY_SELECT : in STD_LOGIC; -- Indicates that Stack memory should be read/written
STACK_RD_WR_CONTROL : in STD_LOGIC; -- T to indicate Stack is being Read, F to indicate Write
E_SW_SEL_Q : in STD_LOGIC; -- E switch Q Reg selection
MAN_STORE_PWR : in STD_LOGIC; -- Manual Store switch for setting Q Reg
T4 : in STD_LOGIC; -- Main clock phase
MACH_RST_2B : in STD_LOGIC; -- Main system reset
Z_BUS_LO_DIG_PARITY : in STD_LOGIC; -- Parity of Z bus bits 4-7
CD_REG : in STD_LOGIC_VECTOR (0 to 3); -- ALU destination - 0011 specifies Q Reg
CLOCK_OFF : in STD_LOGIC; -- CPU clock stop
GK, HK : in STD_LOGIC_VECTOR (0 to 3); -- Storage key from SX1, SX2
CLK : in STD_LOGIC; -- 50MHz FPGA clock
-- Outputs
Q_REG_BUS : out STD_LOGIC_VECTOR (0 to 8); -- Q Reg output
SEL_CPU_BUMP : out STD_LOGIC; -- Select usage of Aux Storage
STACK_PC : out STD_LOGIC; -- Stack data Parity Check error
MPX_CP : out STD_LOGIC; -- MPX clock pulse
MAIN_STG_CP : out STD_LOGIC; -- MS clock pulse
PROTECT_LOC_CPU_OR_MPX : out STD_LOGIC; -- Storage Protection check from CPU or MPX
PROTECT_LOC_SEL_CHNL : out STD_LOGIC -- Storage Protection check from SX1 or SX2
);
end QReg_STP;
architecture FMD of QReg_STP is
signal Q_REG : STD_LOGIC_VECTOR(0 to 8);
signal INH_STG_PROT : STD_LOGIC;
signal sSTACK_PC : STD_LOGIC;
signal UseQ : STD_LOGIC;
signal SET_Q_HI, SET_Q_LO : STD_LOGIC;
subtype stackData is STD_LOGIC_VECTOR(4 to 8);
type stack is array(0 to 255) of stackData;
signal STP_STACK : stack;
signal STACK_DATA : stackData;
signal Q0_GK0_HK0, Q1_GK1_HK1, Q2_GK2_HK2, Q3_GK3_HK3 : STD_LOGIC;
signal STP : STD_LOGIC;
signal HDWR_STG_KEYS_MAT : STD_LOGIC;
signal CD0011 : STD_LOGIC;
signal STACK_DATA_STROBE, READ_GATE, WRITE_GATE, INHIBIT_TIMING : STD_LOGIC;
type delay is array(0 to 24) of std_logic;
signal delayLine : delay := (others=>'0');
signal setLatch, resetLatch : std_logic;
signal latch : std_logic;
signal INH_STG_PROT_PH_D : std_logic;
signal Q47P_D : std_logic_vector(4 to 8);
begin
Q0_GK0_HK0 <= (HK(0) and SX2_SHARE_CYCLE) or (GK(0) and SX1_SHARE_CYCLE) or (Q_REG(0) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q1_GK1_HK1 <= (HK(1) and SX2_SHARE_CYCLE) or (GK(1) and SX1_SHARE_CYCLE) or (Q_REG(1) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q2_GK2_HK2 <= (HK(2) and SX2_SHARE_CYCLE) or (GK(2) and SX1_SHARE_CYCLE) or (Q_REG(2) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q3_GK3_HK3 <= (HK(3) and SX2_SHARE_CYCLE) or (GK(3) and SX1_SHARE_CYCLE) or (Q_REG(3) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
STP <= not INH_STG_PROT and MAIN_STG and (Q0_GK0_HK0 or Q1_GK1_HK1 or Q2_GK2_HK2 or Q3_GK3_HK3); -- BE3F4
HDWR_STG_KEYS_MAT <= (Q0_GK0_HK0 xnor Q_REG(0)) and (Q1_GK1_HK1 xnor Q_REG(1)) and (Q2_GK2_HK2 xnor Q_REG(2)) and (Q3_GK3_HK3 xnor Q_REG(3)); -- BE3F3
PROTECT_LOC_CPU_OR_MPX <= (not H_REG_5_PWR) and STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
PROTECT_LOC_SEL_CHNL <= STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
INH_STG_PROT_PH_D <= GT_T_REG_TO_MN or GT_CK_TO_MN;
INH_STG_PROT_PH: PH port map(INH_STG_PROT_PH_D,GT_LOCAL_STORAGE,INH_STG_PROT); -- AA1F4
SEL_CPU_BUMP_PH: PH port map(FORCE_M_REG_123,GT_LOCAL_STORAGE,SEL_CPU_BUMP); -- AA1F4
STACK_PC <= sSTACK_PC;
MPX_CP <= not MAIN_STG_CP_1; -- BE3D3 BE3G4
MAIN_STG_CP <= MAIN_STG_CP_1; -- BE3G4
CD0011 <= '1' when CD_REG="0011" else '0';
UseQ <= (CD0011 and (N_SEL_SHARE_HOLD or (not CLOCK_OFF))) or (CLOCK_OFF and N_MEM_SELECT and N_SEL_SHARE_HOLD); -- BE3J3 BE3G4 BE3J3
SET_Q_HI <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ); -- BE3J4
SET_Q_LO <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ) or (STACK_RD_WR_CONTROL and STACK_DATA_STROBE); -- BE3J4
Q03: PHV4 port map(Z_BUS(0 to 3),SET_Q_HI,Q_REG(0 to 3)); -- BE3H2
Q47P_D <= ((Z_BUS(4 to 7) & Z_BUS_LO_DIG_PARITY) and (4 to 8 => UseQ)) or (STACK_DATA(4 to 8) and not (4 to 8 => UseQ));
Q47P: PHV5 port map(Q47P_D, SET_Q_LO, Q_REG(4 to 8));
Q_REG_BUS <= Q_REG;
sSTACK_PC <= EvenParity(Q_REG(4 to 7));
STP_FL: process(clk)
begin
if rising_edge(clk) then
setLatch <= not N_STACK_MEMORY_SELECT;
delayLine <= setLatch & delayLine(0 to 23);
STACK_DATA_STROBE <= delayLine(7); -- 140ns
resetLatch <= not delayLine(24);
if (setLatch='1') then latch <= '1'; end if;
if (resetLatch='1') then latch <= '0'; end if;
READ_GATE <= latch and STACK_RD_WR_CONTROL;
WRITE_GATE <= latch and not STACK_RD_WR_CONTROL;
INHIBIT_TIMING <= latch and not READ_GATE;
if WRITE_GATE='1' then
STP_STACK(Conv_Integer(SA_REG)) <= Q_REG(4 to 8);
elsif READ_GATE='1' then
STACK_DATA <= STP_STACK(Conv_Integer(SA_REG));
end if;
end if;
end process;
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Multiplexor Channel registers FO & FB
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MpxFOFB is
Port ( MPX_ROS_LCH : in STD_LOGIC;
S_REG_0 : in STD_LOGIC;
SET_FW : in STD_LOGIC;
S_REG_1 : in STD_LOGIC;
S_REG_2 : in STD_LOGIC;
T3 : in STD_LOGIC;
CK_SALS : in STD_LOGIC_VECTOR (0 to 3);
PK_SALS : in STD_LOGIC;
FBK_T2 : in STD_LOGIC;
MACH_RST_SET_LCH : in STD_LOGIC;
SALS_CS : in STD_LOGIC_VECTOR (0 to 3);
SALS_SA : in STD_LOGIC;
CK_0_PWR : in STD_LOGIC;
R_REG : in STD_LOGIC_VECTOR (0 to 8);
T1,T2 : in STD_LOGIC;
XXH : out STD_LOGIC;
XH : out STD_LOGIC;
XL : out STD_LOGIC;
FT_7_BIT_MPX_CHNL_INTRP : out STD_LOGIC;
FT_2_BIT_MPX_OPN_LCH : out STD_LOGIC;
SUPPR_CTRL_LCH : out STD_LOGIC;
OP_OUT_SIG : out STD_LOGIC;
MPX_OPN_LT_GATE : out STD_LOGIC;
MACH_RST_MPX : out STD_LOGIC;
MPX_INTRPT : out STD_LOGIC;
SX1_MASK : out STD_LOGIC;
EXT_TRAP_MASK_ON : out STD_LOGIC;
SX2_MASK : out STD_LOGIC;
FAK : out STD_LOGIC;
SET_BUS_O_CTRL_LCH : out STD_LOGIC;
MPX_BUS_O_REG : out STD_LOGIC_VECTOR (0 to 8);
clk : in STD_LOGIC);
end MpxFOFB;
architecture FMD of MpxFOFB is
signal sXXH,sXH,sXL,T3SET,X_SET : STD_LOGIC;
signal XXH_IN,XH_IN,XL_IN : STD_LOGIC;
signal XXHBU,XHBU,XLBU : STD_LOGIC;
signal sMACH_RST_MPX : STD_LOGIC;
signal CK11XX, CKX11X,CKX1X1,CK1X1X,CKXX11 : STD_LOGIC;
signal CHNL_L,OPN_L,SUPPR_L,OUT_L : STD_LOGIC;
signal notOP_OUT_SIG,MpxMask : STD_LOGIC;
alias KP is PK_SALS;
signal sFAK,sSET_BUS_O_CTRL,ResetBusO : STD_LOGIC;
signal BusO_Set,BusO_Reset : STD_LOGIC_VECTOR (0 to 8);
signal sFT_7_BIT_MPX_CHNL_INTRP,sFT_2_BIT_MPX_OPN_LCH,sSUPPR_CTRL_LCH : STD_LOGIC;
begin
-- XL, XH and XXL bits and backup
XXH_BU: entity PH port map (D=>sXXH, L=>SET_FW, Q=> XXHBU);
XXH_IN <= (XXHBU and MPX_ROS_LCH) or (S_REG_0 and not MPX_ROS_LCH);
X_SET <= T3SET or sMACH_RST_MPX;
XXH_PH: entity PH port map (D=>XXH_IN, L=>X_SET, Q=> sXXH);
XXH <= sXXH;
XH_BU: entity PH port map (D=>sXH, L=>SET_FW, Q=> XHBU);
XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH);
XH_PH: entity PH port map (D=>XH_IN, L=>X_SET, Q=>sXH);
XH <= sXH;
XL_BU: entity PH port map (D=>sXL, L=>SET_FW, Q=> XLBU);
XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH);
XL_PH: entity PH port map (D=>XL_IN, L=>X_SET, Q=>sXL);
XL <= sXL;
-- MPX Flags
T3SET <= (MPX_ROS_LCH and T3) or (FBK_T2 and CK_SALS(0) and CK_SALS(3));
sMACH_RST_MPX <= MACH_RST_SET_LCH;
MACH_RST_MPX <= sMACH_RST_MPX;
CK11XX <= CK_SALS(0) and CK_SALS(1) and FBK_T2;
CHNL_L <= sMACH_RST_MPX or CK11XX;
MPX_CHNL: entity PH port map (D=>KP,L=>CHNL_L,Q=>sFT_7_BIT_MPX_CHNL_INTRP);
FT_7_BIT_MPX_CHNL_INTRP <= sFT_7_BIT_MPX_CHNL_INTRP;
CKX11X <= CK_SALS(1) and CK_SALS(2) and FBK_T2;
OPN_L <= sMACH_RST_MPX or CKX11X;
MPX_OPN: entity PH port map (D=>KP,L=>OPN_L,Q=>sFT_2_BIT_MPX_OPN_LCH);
FT_2_BIT_MPX_OPN_LCH <= sFT_2_BIT_MPX_OPN_LCH;
CK1X1X <= CK_SALS(0) and CK_SALS(2) and FBK_T2;
SUPPR_L <= sMACH_RST_MPX or CK1X1X;
SUPPR_CTRL: entity PH port map (D=>KP,L=>SUPPR_L,Q=>sSUPPR_CTRL_LCH);
SUPPR_CTRL_LCH <= sSUPPR_CTRL_LCH;
CKX1X1 <= CK_SALS(1) and CK_SALS(3) and FBK_T2;
OUT_L <= sMACH_RST_MPX or CKX1X1;
OP_OUT_CTRL: entity PH port map (D=>KP,L=>OUT_L,Q=>notOP_OUT_SIG);
OP_OUT_SIG <= not notOP_OUT_SIG;
MPX_OPN_LT_GATE <= CKX11X;
-- External Interrupt Masks
-- ?? Should the R_REG bits be inverted before use?
CKXX11 <= CK_SALS(2) and CK_SALS(3) and FBK_T2;
MPX_MASK: entity PH port map (D=>R_REG(0),L=>CKXX11,Q=>MPXMask);
MPX_INTRPT <= not (sFT_7_BIT_MPX_CHNL_INTRP and MPXMask);
SX1MASK: entity PH port map (D=>R_REG(1),L=>CKXX11,Q=>SX1_MASK);
EXT_MASK: entity PH port map (D=>R_REG(7),L=>CKXX11,Q=>EXT_TRAP_MASK_ON);
SX2MASK: entity PH port map (D=>R_REG(2),L=>CKXX11,Q=>SX2_MASK);
-- MPX BUS OUT REGISTER
sFAK <= SALS_CS(0) and SALS_CS(1) and SALS_CS(2) and SALS_CS(3) and not SALS_SA;
FAK <= sFAK;
sSET_BUS_O_CTRL <= sFAK and CK_0_PWR;
SET_BUS_O_CTRL_LCH <= sSET_BUS_O_CTRL;
BusO_Set <= R_REG and (0 to 8=>(sSET_BUS_O_CTRL and T2)); -- ??? "and T2" added to prevent incorrect setting of BUS_O
BusO_Reset <= (0 to 8=>sSET_BUS_O_CTRL and T1);
MPX_BUSO: entity FLVL port map (S=>BusO_Set,R=>BusO_Reset,Q=>MPX_BUS_O_REG);
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08D.vhd
-- Creation Date: 21:39:37 03/22/2010
-- Description:
-- Multiplexor Channel Controls - FA Register - Indicators
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Gates_package.all;
USE work.Buses_package.all;
entity MpxFA is
Port ( BUS_O_REG : in STD_LOGIC_VECTOR (0 to 8);
DIAG_SW : in STD_LOGIC;
MPX_BUS_OUT_BITS : out STD_LOGIC_VECTOR (0 to 8);
MPX_BUS_IN_BITS : in STD_LOGIC_VECTOR (0 to 8);
TAGS_OUT : out MPX_TAGS_OUT;
TAGS_IN : in MPX_TAGS_IN;
FAK : in STD_LOGIC;
RECYCLE_RST : in STD_LOGIC;
CK_P_BIT : in STD_LOGIC;
ALU_CHK_LCH : in STD_LOGIC;
CHK_SW_PROC_SW : in STD_LOGIC;
N1050_REQ_IN : in STD_LOGIC;
ROS_SCAN : in STD_LOGIC;
FBK_T2 : in STD_LOGIC;
FT5_BIT_SEL_IN : out STD_LOGIC;
SERV_IN_SIGNAL : out STD_LOGIC;
STATUS_IN_SIGNAL : out STD_LOGIC;
FT3_BIT_MPX_SHARE_REQ : out STD_LOGIC;
MPX_SHARE_REQ : out STD_LOGIC;
T1,T2,T3 : in STD_LOGIC;
ANY_PRIORITY_LCH : in STD_LOGIC;
CK_SALS_PWR : in STD_LOGIC_VECTOR (0 to 3);
SET_BUS_O_CTRL_LCH : in STD_LOGIC;
N1401_MODE : in STD_LOGIC;
N1050_OP_IN : in STD_LOGIC;
N1050_CE_MODE : in STD_LOGIC;
MPX_METERING_IN : out STD_LOGIC;
FT7_MPX_CHNL_IN : in STD_LOGIC;
LOAD_IND : in STD_LOGIC;
SUPPR_CTRL_LCH : in STD_LOGIC;
OP_OUT_SIGNAL : in STD_LOGIC;
RECYCLE_RESET : in STD_LOGIC;
-- COMMD_OUT : out STD_LOGIC;
-- SERV_OUT : out STD_LOGIC;
OP_OUT_SIG : in STD_LOGIC;
SEL_O_FT6 : out STD_LOGIC;
N1050_SEL_IN : in STD_LOGIC;
N1050_SEL_OUT : out STD_LOGIC;
N1050_SEL_O : in STD_LOGIC;
N1050_INSTALLED : in STD_LOGIC;
SUPPR_O : out STD_LOGIC;
SUPPR_O_FT0 : out STD_LOGIC;
OP_OUT : out STD_LOGIC;
METERING_OUT : in STD_LOGIC;
CLOCK_OUT : in STD_LOGIC;
CLK : in STD_LOGIC;
-- Mpx Indicators
OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN,
SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT,
SUPPRESS_OUT : out std_logic); -- 08A
end MpxFA;
architecture FMD of MpxFA is
signal sSERV_IN_SIGNAL, sSTATUS_IN_SIGNAL, sADDR_OUT, sSUPPR_O, sOP_OUT : STD_LOGIC;
signal SIS1,SIS2,SIS3 : STD_LOGIC;
signal OP_INLK_SET, OP_INLK : STD_LOGIC;
signal SERV_OUT, CMD_OUT : STD_LOGIC;
signal sTAGS_OUT : MPX_TAGS_OUT;
signal sTAGS_IN : MPX_TAGS_IN;
signal sFT5_BIT_SEL_IN, Reset_SELO : STD_LOGIC;
signal sN1050_SEL_OUT : STD_LOGIC;
signal CMD_STT_Set, RST_CMD_RSTT_ADDR_OUT, CMD_STT : STD_LOGIC;
signal sFT3_BIT_MPX_SHARE_REQ, sSEL_O_FT6, sSUPPR_O_FT0 : STD_LOGIC;
signal FAK_T2 : STD_LOGIC;
signal SetAdrO2, ADDR_OUT_2, SetAdrO1, SetCmdO, RstCmdO, SetSrvO, RstSrvO : STD_LOGIC;
signal SetCUBusyInlk, ResetCUBusyInlk, CUBusy, RST_STT_SEL_OUT : STD_LOGIC;
signal ResetBusOCtrl, BUSOCtrl : STD_LOGIC;
signal SetStartSelO, ResetStartSelO, StartSelO : STD_LOGIC;
signal NO_1050_SEL_O : STD_LOGIC;
signal SetSelReq, ResetSelReq, SetSelOInlk, SelOInlk : STD_LOGIC;
signal SS_RECYCLE_RST : STD_LOGIC;
begin
STATUS_IN <= sTAGS_IN.STA_IN;
SERVICE_IN <= sTAGS_IN.SRV_IN;
ADDR_IN <= sTAGS_IN.ADR_IN; -- AA3F3
OPNL_IN <= sTAGS_IN.OPL_IN; -- AA3F2 AA3F5
SIS1 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.SRV_IN) or OP_INLK; -- AA3F2 AA3E2
sSERV_IN_SIGNAL <= SIS1 and not sTAGS_IN.STA_IN; -- Wire-AND
SERV_IN_SIGNAL <= sSERV_IN_SIGNAL;
SIS3 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.STA_IN) or (OP_INLK and not sTAGS_OUT.ADR_OUT); -- AA3D7 AA3E2
sSTATUS_IN_SIGNAL <= SIS3 and not sTAGS_IN.SRV_IN; -- Wire-AND
STATUS_IN_SIGNAL <= sSTATUS_IN_SIGNAL;
OP_INLK_SET <= not sTAGS_IN.OPL_IN and T2;
OP_INLK_FL: entity FLL port map (S=>OP_INLK_SET, R=> T1, Q=>OP_INLK); -- AA3E4 ?? R=> NOT T1 ??
sFT5_BIT_SEL_IN <= (N1050_SEL_IN and not N1050_INSTALLED) or N1050_SEL_IN; -- AA3E5 AA3E2
FT5_BIT_SEL_IN <= sFT5_BIT_SEL_IN;
Reset_SELO <= RECYCLE_RST or FBK_T2 or sFT5_BIT_SEL_IN; -- AA3D7 AA3E7
CMD_STT_Set <= CK_P_BIT and FAK;
RST_CMD_RSTT_ADDR_OUT <= (FAK and T1) or RECYCLE_RST; -- AA3E6 AA3E2
CMD_STT_FL: entity FLL port map (S=>CMD_STT_Set, R=>RST_CMD_RSTT_ADDR_OUT, Q=>CMD_STT); -- AA3D7 AA3E7
sFT3_BIT_MPX_SHARE_REQ <= (ROS_SCAN or not CMD_STT) and (N1050_REQ_IN or sTAGS_IN.REQ_IN or (ALU_CHK_LCH and CHK_SW_PROC_SW) or sTAGS_IN.OPL_IN); -- AA3F2 AA3E5 AA3G4
MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ;
FT3_BIT_MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ;
sTAGS_IN.OPL_IN <= TAGS_IN.OPL_IN or (DIAG_SW and BUS_O_REG(7)); -- AA3B4
sTAGS_IN.ADR_IN <= TAGS_IN.ADR_IN or (DIAG_SW and BUS_O_REG(6)); -- AA3B4
sTAGS_IN.STA_IN <= TAGS_IN.STA_IN or (DIAG_SW and BUS_O_REG(4)); -- AA3B4
sTAGS_IN.SRV_IN <= TAGS_IN.SRV_IN or (DIAG_SW and BUS_O_REG(5)); -- AA3B4
sTAGS_IN.SEL_IN <= TAGS_IN.SEL_IN or (DIAG_SW and BUS_O_REG(0)); -- AA3B4
sTAGS_IN.REQ_IN <= TAGS_IN.REQ_IN;
sTAGS_IN.MTR_IN <= TAGS_IN.MTR_IN;
FAK_T2 <= FAK and (T2 and not ANY_PRIORITY_LCH); -- AA3B7 AA3F4 AA3E6
SetAdrO2 <= T3 and sADDR_OUT;
ADDR_O_2: entity FLL port map (S=>SetAdrO2, R=>RST_CMD_RSTT_ADDR_OUT, Q=>ADDR_OUT_2); -- AA3E4
SetAdrO1 <= FAK_T2 and CK_SALS_PWR(1);
ADDR_O_1: entity FLL port map (S=>SetAdrO1, R=>RST_CMD_RSTT_ADDR_OUT, Q=>sADDR_OUT); -- AA3D7 AA3E7
ADDR_OUT <= sADDR_OUT;
SetCmdO <= FAK_T2 and CK_SALS_PWR(2);
CMD_O: entity FLL port map (S=>SetCmdO, R=>RstCmdO, Q=>CMD_OUT); -- AA3E4 AA3E5
TAGS_OUT.CMD_OUT <= CMD_OUT;
SetSrvO <= FAK_T2 and CK_SALS_PWR(3);
SRV_O: entity FLL port map (S=>SetSrvO, R=>RstSrvO, Q=>SERV_OUT); -- AA3C7
CU_BUSY_INLK: entity FLL port map (S=>SetCUBusyInlk, R=>ResetCUBusyInlk, Q=>CUBusy); -- AA3B5
RST_STT_SEL_OUT <= not OP_OUT_SIG or CUBusy; -- AA3F7
ResetBusOCtrl <= not sADDR_OUT and not CMD_OUT and not SERV_OUT; -- AA3D7
BUS_O_CTRL: entity FLL port map (S=>SET_BUS_O_CTRL_LCH, R=>ResetBusOCtrl, Q=>BUSOCtrl); -- AA3J5
SetStartSelO <= sADDR_OUT and T2 and BUSOCtrl; -- AA3E6
ResetStartSelO <= RST_STT_SEL_OUT or (not N1401_MODE and sTAGS_IN.ADR_IN) or (not sADDR_OUT and Reset_SelO); -- AA3F5 AA3K3
START_SEL_O: entity FLL port map (S=>SetStartSelO, R=>ResetStartSelO, Q=>StartSelO); -- AA3L4 AA3E7
sSEL_O_FT6 <= not CUBusy and (StartSelO or NO_1050_SEL_O or N1050_SEL_O); -- AA3E5
SEL_O_FT6 <= sSEL_O_FT6;
NO_1050_SEL_O <= not N1050_INSTALLED and sN1050_SEL_OUT; -- AA3D2
SetSelReq <= not SelOInlk and T2 and sFT3_BIT_MPX_SHARE_REQ;
ResetSelReq <= SelOInlk or not sFT3_BIT_MPX_SHARE_REQ;
SEL_REQ: entity FLL port map (S=>SetSelReq, R=>ResetSelReq, Q=>sN1050_SEL_OUT); -- AA3F4
N1050_SEL_OUT <= sN1050_SEL_OUT;
SetSelOInlk <= (sTAGS_IN.ADR_IN and sTAGS_IN.OPL_IN) or (N1050_OP_IN and not N1050_CE_MODE); -- AA3B7
SEL_O_INLK: entity FLL port map (S=>SetSelOInlk, R=>not sTAGS_IN.OPL_IN, Q=>SelOInlk); -- AA3C7
sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) or not LOAD_IND or SUPPR_CTRL_LCH; -- AA3C7 AA3E5
SS_RECYCLE_RST <= RECYCLE_RST; -- AA3G3 Single Shot ??
sOP_OUT <= OP_OUT_SIGNAL and not SS_RECYCLE_RST; -- AA3D6
TAGS_OUT.ADR_OUT2 <= ADDR_OUT_2;
TAGS_OUT.ADR_OUT <= sADDR_OUT;
TAGS_OUT.CMD_OUT <= CMD_OUT;
TAGS_OUT.SRV_OUT <= SERV_OUT;
TAGS_OUT.SEL_OUT <= sSEL_O_FT6; -- ??
TAGS_OUT.MTR_OUT <= METERING_OUT;
TAGS_OUT.CLK_OUT <= CLOCK_OUT;
TAGS_OUT.SUP_OUT <= sSUPPR_O;
TAGS_OUT.OPL_OUT <= sOP_OUT;
-- TAGS_OUT.SEL_OUT <= '0'; -- ??
TAGS_OUT.STA_OUT <= '0'; -- ??
TAGS_OUT.HLD_OUT <= '0'; -- ??
-- Output tag indicators not really shown
SELECT_OUT <= sSEL_O_FT6;
ADDR_OUT <= sADDR_OUT;
COMMAND_OUT <= CMD_OUT;
SERVICE_OUT <= SERV_OUT;
SUPPRESS_OUT <= sSUPPR_O;
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: fmd2030_udc2.vhd
-- Creation Date:
-- Description:
-- Second section of the 360/30, corresponding to Unit Data & Control Diagram 2
-- in the MDM.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
USE work.Gates_package.all;
USE work.Buses_package.all;
USE work.all;
entity UDC2 is
port(
-- Buses
SALS : IN SALS_Bus;
CTRL : IN CTRL_REG;
Z_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
A_BUS1 : IN STD_LOGIC_VECTOR(0 to 8);
B_BUS : IN STD_LOGIC_VECTOR(0 to 8);
M_ASSM_BUS,N_ASSM_BUS : IN STD_LOGIC_VECTOR(0 to 8);
R : OUT STD_LOGIC_VECTOR(0 to 8);
S : OUT STD_LOGIC_VECTOR(0 to 7);
MN : OUT STD_LOGIC_VECTOR(0 to 15);
-- M_P, N_P : OUT STD_LOGIC;
E_BUS : IN E_SW_BUS_Type;
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
MPX_TAGS_I : IN MPX_TAGS_IN;
-- Switches
LAMP_TEST : IN STD_LOGIC;
CHK_SW_PROC_SW : IN STD_LOGIC; -- 04A
CHK_SW_DISABLE : IN STD_LOGIC; -- 04A
Sw_Slow : IN STD_LOGIC;
-- Indicators
IND_OPNL_IN : OUT STD_LOGIC;
IND_ADDR_IN : OUT STD_LOGIC;
IND_STATUS_IN : OUT STD_LOGIC;
IND_SERV_IN : OUT STD_LOGIC;
IND_SEL_OUT : OUT STD_LOGIC;
IND_ADDR_OUT : OUT STD_LOGIC;
IND_CMMD_OUT : OUT STD_LOGIC;
IND_SERV_OUT : OUT STD_LOGIC;
IND_SUPPR_OUT : OUT STD_LOGIC;
IND_FO : OUT STD_LOGIC_VECTOR(0 to 7);
IND_FO_P : OUT STD_LOGIC;
IND_A : OUT STD_LOGIC_VECTOR(0 to 8);
IND_B : OUT STD_LOGIC_VECTOR(0 to 8);
IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8);
IND_M, IND_N : OUT STD_LOGIC_VECTOR(0 to 8);
IND_MAIN_STG, IND_LOC_STG, IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG, IND_CHK_B_REG, IND_CHK_STOR_ADDR, IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS, IND_CHK_ROS_ADDR, IND_CHK_STOR_DATA, IND_CHK_ALU : OUT STD_LOGIC;
-- Controls
CLOCK_START : IN STD_LOGIC;
MACH_RST_3,MACH_RST_6 : IN STD_LOGIC;
CLOCK_ON : OUT STD_LOGIC;
CLOCK_OFF : OUT STD_LOGIC;
MANUAL_STORE : IN STD_LOGIC;
RECYCLE_RST : IN STD_LOGIC;
MAN_STOR_OR_DSPLY : IN STD_LOGIC;
MAN_STOR_PWR : IN STD_LOGIC;
STORE_S_REG_RST : IN STD_LOGIC;
E_SW_SEL_S : IN STD_LOGIC;
MACH_RST_SET_LCH : IN STD_LOGIC;
DIAG_SW : IN STD_LOGIC;
-- S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC;
ROS_SCAN : IN STD_LOGIC;
GT_SWS_TO_WX_PWR : IN STD_LOGIC;
RST_LOAD : IN STD_LOGIC;
SYSTEM_RST_PRIORITY_LCH : IN STD_LOGIC;
A_REG_PC : OUT STD_LOGIC;
-- B_REG_PC : OUT STD_LOGIC;
CARRY_1_LCHD : OUT STD_LOGIC;
CARRY_0_LATCHED : OUT STD_LOGIC;
ALU_CHK : OUT STD_LOGIC;
NTRUE,COMPLEMENT : OUT STD_LOGIC;
P_CONNECT,P_CTRL_N,N_CTRL_N,N_CTRL_LM : OUT STD_LOGIC;
ALU_CHK_LCH : OUT STD_LOGIC;
CPU_RD_PWR : IN STD_LOGIC; -- 04B
GT_MAN_SET_MN : IN STD_LOGIC; -- 03B
CHNL_RD_CALL : IN STD_LOGIC; -- 04D
XH, XL, XXH : OUT STD_LOGIC; -- 08C
MN_PC : OUT STD_LOGIC; -- 07AD3
SET_IND_ROSAR : IN STD_LOGIC;
N_STACK_MEMORY_SELECT, STACK_RD_WR_CONTROL : IN STD_LOGIC;
H_REG_5_PWR : IN STD_LOGIC;
FORCE_M_REG_123 : IN STD_LOGIC;
GT_LOCAL_STORAGE : IN STD_LOGIC;
GT_T_REG_TO_MN : IN STD_LOGIC;
GT_CK_TO_MN : IN STD_LOGIC;
MAIN_STG_CP_1 : IN STD_LOGIC;
N_STACK_MEM_SELECT : IN STD_LOGIC;
SEL_CPU_BUMP : OUT STD_LOGIC; -- 04D
WX_CHK : IN STD_LOGIC; -- 01A
EARLY_M0 : OUT STD_LOGIC; -- 07B to 05D
MEM_WRAP : IN STD_LOGIC;
SUPPR_A_REG_CHK : OUT STD_LOGIC;
ODD : OUT STD_LOGIC;
STATUS_IN_LCHD : OUT STD_LOGIC;
SALS_PC : IN STD_LOGIC;
R_REG_PC : IN STD_LOGIC;
STORE_R : IN STD_LOGIC;
N2ND_ERROR_STOP : IN STD_LOGIC;
DECIMAL : OUT STD_LOGIC;
-- Inputs from UDC1
USE_R : IN STD_LOGIC;
USE_MAIN_MEM, USE_LOC_MAIN_MEM : IN STD_LOGIC;
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02A
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
SUPPR_MACH_CHK_TRAP : IN STD_LOGIC; -- 03A
SEL_DATA_READY : IN STD_LOGIC; -- 03B
N1401_MODE : IN STD_LOGIC; -- 05A
STG_MEM_SELECT : IN STD_LOGIC; -- 03D
MEM_PROT_REQUEST : IN STD_LOGIC; -- 03A
MANUAL_DISPLAY : IN STD_LOGIC; -- 03D
MAIN_STG : IN STD_LOGIC; -- 04D
MACH_RST_SW : IN STD_LOGIC; -- 03D
MACH_RST_SET_LCH_DLY : IN STD_LOGIC; -- 04B
MACH_CHK_RST : IN STD_LOGIC; -- 04A
MACH_CHK_PULSE : IN STD_LOGIC; -- 03A
LOCAL_STG : IN STD_LOGIC; -- 04D
GT_D_REG_TO_A_BUS : IN STD_LOGIC; -- 05C
GT_CA_TO_W_REG : IN STD_LOGIC; -- 02B
DATA_READY : IN STD_LOGIC; -- 03A
CTRL_REG_CHK : IN STD_LOGIC; -- 01A
CPU_WR_IN_R_REG : IN STD_LOGIC; -- 04D
CPU_SET_ALLOW_WR_LCH : IN STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
ALLOW_WRITE_DLYD, ALLOW_WRITE : IN STD_LOGIC; -- 03D
USE_MANUAL_DECODER : IN STD_LOGIC;
GATED_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
MPX_ROS_LCH : IN STD_LOGIC; -- 02A
SET_FW : IN STD_LOGIC; -- 01B
LOAD_IND : IN STD_LOGIC; -- 03C
CLOCK_OUT : IN STD_LOGIC; -- 04A
METERING_OUT : IN STD_LOGIC; -- 04A
READ_ECHO_1,READ_ECHO_2,WRITE_ECHO_1,WRITE_ECHO_2 : IN STD_LOGIC;
-- Outputs to UDC1
FIRST_MACH_CHK_REQ : OUT STD_LOGIC; -- 03A
FIRST_MACH_CHK : OUT STD_LOGIC; -- 03C
ANY_MACH_CHK : OUT STD_LOGIC; -- 01A, 03C, 04A
ALLOW_PROTECT : OUT STD_LOGIC; -- 03A
ALLOW_PC_SALS : OUT STD_LOGIC; -- 01B
P_8F_DETECTED : OUT STD_LOGIC; -- 03A
M_REG_0 : OUT STD_LOGIC; -- 05D
Z0_BUS_0 : OUT STD_LOGIC;
Z_0 : OUT STD_LOGIC;
EXT_TRAP_MASK_ON : OUT STD_LOGIC; -- 08C to 04C
MACH_RST_PROT : OUT STD_LOGIC; -- 07B to 04C
CS_DECODE_X001 : OUT STD_LOGIC; -- 07B to 03C
BASIC_CS0 : OUT STD_LOGIC; -- 07B to 03C
MACH_RST_2A : OUT STD_LOGIC;
MACH_RST_2B : OUT STD_LOGIC;
CARRY_0 : OUT STD_LOGIC;
INTRODUCE_ALU_CHK : OUT STD_LOGIC;
FT0, FT2, FT3, FT5, FT6, FT7 : OUT STD_LOGIC; -- 08C,D to 05C
MPX_INTERRUPT : OUT STD_LOGIC;
MACH_RST_MPX : OUT STD_LOGIC;
MPX_SHARE_REQ : OUT STD_LOGIC;
MPX_METERING_IN : OUT STD_LOGIC;
ADDR_IN_LCHD : OUT STD_LOGIC;
OPNL_IN_LCHD : OUT STD_LOGIC;
SERV_IN_LCHD : OUT STD_LOGIC;
-- Inputs from UDC3
T_REQUEST : IN STD_LOGIC; -- 10B
STORE_HR, STORE_GR : IN STD_LOGIC; -- 14D, 12D
SEL_SHARE_CYCLE : IN STD_LOGIC; -- 12D
SEL_R_W_CTRL : IN STD_LOGIC; -- 12C
SEL_CHNL_CHK : IN STD_LOGIC; -- 11A
HR_REG_0_7, GR_REG_0_7 : IN STD_LOGIC_VECTOR(0 TO 7); -- 13C, 11C
HR_REG_P_BIT, GR_REG_P_BIT : IN STD_LOGIC; -- 13A, 11A
GT_HSMPX_INTO_R_REG : IN STD_LOGIC; -- ???
DR_CORR_P_BIT : IN STD_LOGIC; -- ??? (HSMPX)
GT_DETECTORS_TO_HR, GT_DETECTORS_TO_GR : IN STD_LOGIC; -- 12D, 14D
EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : IN STD_LOGIC; -- 13A, 11A
-- Outputs to UDC3
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
-- Selector & Mpx channels
SX1_RD_CYCLE,SX2_RD_CYCLE,SX1_WR_CYCLE,SX2_WR_CYCLE : IN STD_LOGIC;
SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : IN STD_LOGIC;
N_SEL_SHARE_HOLD : IN STD_LOGIC;
GK,HK : IN STD_LOGIC_VECTOR(0 to 3);
PROTECT_LOC_CPU_OR_MPX, PROTECT_LOC_SEL_CHNL : OUT STD_LOGIC;
FO : OUT STD_LOGIC_VECTOR(0 to 8);
-- Debug
DEBUG : OUT STD_LOGIC;
-- Clocks
CLOCK_IN : IN STD_LOGIC;
T1,T2,T3,T4 : OUT STD_LOGIC;
P1,P2,P3,P4 : OUT STD_LOGIC;
SEL_T1, SEL_T3 : IN STD_LOGIC;
M_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : OUT STD_LOGIC;
Clk : IN STD_LOGIC
);
end entity UDC2;
architecture FMD of UDC2 is
signal sFO : STD_LOGIC_VECTOR(0 to 7);
signal sFO_P : STD_LOGIC;
signal OPNL_IN : STD_LOGIC;
signal ADDR_IN : STD_LOGIC;
signal STATUS_IN : STD_LOGIC;
signal SERVICE_IN : STD_LOGIC;
signal SELECT_OUT : STD_LOGIC;
signal ADDR_OUT : STD_LOGIC;
signal COMMAND_OUT : STD_LOGIC;
signal SERVICE_OUT : STD_LOGIC;
signal SUPPRESS_OUT : STD_LOGIC;
signal Z_HI_0,Z_LO_0,sZ_0 : STD_LOGIC;
signal sCARRY_0, CARRY_4 : STD_LOGIC;
signal GT_CARRY_TO_S3 : STD_LOGIC;
signal sMACH_RST_2A,sMACH_RST_2B,MACH_RST_2C : STD_LOGIC;
signal MN_REG_CHK_SMPLD : STD_LOGIC;
signal A_BUS, A_BUS2, Q_REG_BUS : STD_LOGIC_VECTOR(0 TO 8);
signal R_0 : STD_LOGIC;
signal READ_1,READ_2,WRITE_1,WRITE_2 : STD_LOGIC;
-- signal PHASE_RD_1, PHASE_RD_2, PHASE_WR_1, PHASE_WR_2 : STD_LOGIC;
signal SA : STD_LOGIC_VECTOR(0 to 7);
signal MPX_CP : STD_LOGIC;
signal OSC_T_LINE : STD_LOGIC;
signal FB_K_T2_PULSE : STD_LOGIC;
signal GT_Q_REG_TO_A_BUS : STD_LOGIC;
signal STACK_PC : STD_LOGIC;
signal MC : STD_LOGIC_VECTOR(0 to 7);
signal MAIN_STORAGE_CP : STD_LOGIC;
signal GATE_Z_BUS_TO_S_REG : STD_LOGIC;
signal GT_DDC_TO_A_BUS : STD_LOGIC;
-- signal A_BUS_2,A_BUS_3 : STD_LOGIC_VECTOR(0 to 8);
-- IO
signal SERV_IN_SIG : STD_LOGIC := '0';
signal STAT_IN_SIG : STD_LOGIC := '0';
signal sT1,sT2,sT3,sT4 : STD_LOGIC;
signal sP1,sP2,sP3,sP4 : STD_LOGIC;
signal sCLOCK_ON, sCLOCK_OFF : STD_LOGIC;
signal sM_CONV_OSC, sP_CONV_OSC, sM_CONV_OSC_2 : STD_LOGIC;
signal sA_REG_PC, sB_REG_PC : STD_LOGIC;
signal sALU_CHK : STD_LOGIC;
signal sMN : STD_LOGIC_VECTOR(0 to 15);
signal sM_P, sN_P : STD_LOGIC;
signal sS : STD_LOGIC_VECTOR(0 to 7);
signal sZ_BUS,sN_Z_BUS,sR : STD_LOGIC_VECTOR(0 to 8);
signal sS_REG_RST : STD_LOGIC;
signal sNTRUE, sCOMPLEMENT : STD_LOGIC;
signal sP_CONNECT, sP_CTRL_N, sN_CTRL_N, sN_CTRL_LM : STD_LOGIC;
signal sALU_CHK_LCH : STD_LOGIC;
signal sZ_BUS_LO_DIGIT_PARITY : STD_LOGIC;
signal sMN_PC : STD_LOGIC;
signal sPROTECT_LOC_CPU_OR_MPX : STD_LOGIC;
signal sXL,sXH,sXXH : STD_LOGIC;
signal SUPPR_CTRL_LCH,OP_OUT_SIG,MPX_OPN_LT_GATE,SX1_MASK,SX2_MASK,FAK,SET_BUS_O_CTRL_LCH : STD_LOGIC;
-- signal sMPX_BUS_O_REG : STD_LOGIC_VECTOR(0 to 8);
signal sFT2, sFT7 : STD_LOGIC;
begin
-- Clock
clock_sect: entity Clock (FMD) port map (
CLOCK_IN => CLOCK_IN,
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
P2 => sP2,
P3 => sP3,
P4 => sP4,
CLOCK_START => CLOCK_START,
CLOCK_ON => sCLOCK_ON,
CLOCK_OFF => sCLOCK_OFF,
MACH_RST_3 => MACH_RST_3,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => sP_CONV_OSC,
M_CONV_OSC_2 => sM_CONV_OSC_2,
OSC_T_LINE => OSC_T_LINE,
Sw_Slow => Sw_Slow
);
T1 <= sT1;
T2 <= sT2;
T3 <= sT3;
T4 <= sT4;
P1 <= sP1;
P2 <= sP2;
P3 <= sP3;
P4 <= sP4;
M_CONV_OSC <= sM_CONV_OSC;
P_CONV_OSC <= sP_CONV_OSC;
M_CONV_OSC_2 <= sM_CONV_OSC_2;
CLOCK_ON <= sCLOCK_ON;
CLOCK_OFF <= sCLOCK_OFF;
MpxInd_sect: entity MpxInd (FMD) port map (
FO => sFO,
FO_P => sFO_P,
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => ADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT,
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
TEST_LAMP => LAMP_TEST
);
A_BUS <= A_BUS1 and A_BUS2; -- Combine buses - input buses are 11111111 when inactive, values are inverted
ALU: entity ABALU port map(
-- Inputs
LAMP_TEST => LAMP_TEST,
SALS => SALS,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
S_REG_3 => sS(3),
SERV_IN_SIG => SERV_IN_SIG,
STAT_IN_SIG => STAT_IN_SIG,
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
T_REQUEST => T_REQUEST,
A_BUS => A_BUS,
B_BUS => B_BUS,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
S_REG_0 => sS(0),
CTRL => CTRL,
DIAG_SW => DIAG_SW,
S_REG_RST => sS_REG_RST,
GT_Z_BUS_TO_S_REG => GATE_Z_BUS_TO_S_REG,
ROS_SCAN => ROS_SCAN,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
RST_LOAD => RST_LOAD,
SYSTEM_RST_PRIORITY_LCH => SYSTEM_RST_PRIORITY_LCH,
-- Outputs
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
A_REG_PC => sA_REG_PC,
B_REG_PC => sB_REG_PC,
OPNL_IN_LCHD => OPNL_IN_LCHD,
STATUS_IN_LCHD => STATUS_IN_LCHD,
Z0_BUS_0 => Z0_BUS_0,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
CARRY_0 => sCARRY_0,
CARRY_1_LCHD => CARRY_1_LCHD,
CARRY_0_LATCHED => CARRY_0_LATCHED,
ALU_CHK => sALU_CHK,
NTRUE => sNTRUE,
COMPLEMENT => sCOMPLEMENT,
P_CONNECT => sP_CONNECT,
P_CTRL_N => sP_CTRL_N,
N_CTRL_N => sN_CTRL_N,
N_CTRL_LM => sN_CTRL_LM,
P_Z_BUS => sZ_BUS,
N_Z_BUS => sN_Z_BUS,
Z_HI_0 => Z_HI_0,
Z_LO_0 => Z_LO_0,
Z_0 => sZ_0,
Z_BUS_LO_DIGIT_PARITY => sZ_BUS_LO_DIGIT_PARITY,
MACH_RST_2A => sMACH_RST_2A,
MACH_RST_2B => sMACH_RST_2B,
MACH_RST_2C => MACH_RST_2C,
ALU_CHK_LCH => sALU_CHK_LCH,
ODD => ODD,
GT_CARRY_TO_S3 => GT_CARRY_TO_S3,
DECIMAL => DECIMAL,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
-- Debug
-- DEBUG => DEBUG,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
Clk => Clk
);
A_REG_PC <= sA_REG_PC;
-- B_REG_PC <= sB_REG_PC;
ALU_CHK <= sALU_CHK;
Z_BUS <= sZ_BUS;
-- S_REG_RST <= sS_REG_RST;
NTRUE <= sNTRUE;
COMPLEMENT <= sCOMPLEMENT;
P_CONNECT <= sP_CONNECT;
P_CTRL_N <= sP_CTRL_N;
N_CTRL_N <= sN_CTRL_N;
N_CTRL_LM <= sN_CTRL_LM;
ALU_CHK_LCH <= sALU_CHK_LCH;
MACH_RST_2A <= sMACH_RST_2A;
MACH_RST_2B <= sMACH_RST_2B;
CARRY_0 <= sCARRY_0;
Z_0 <= sZ_0;
r_reg: entity RREG_STG port map (
-- Inputs
SALS => SALS,
CTRL => CTRL,
SX2_RD_CYCLE => SX2_RD_CYCLE,
SEL_T3 => SEL_T3,
GT_DETECTORS_TO_HR => GT_DETECTORS_TO_HR,
SEL_DATA_READY => SEL_DATA_READY,
SEL_R_W_CTRL => SEL_R_W_CTRL,
SX2_WR_CYCLE => SX2_WR_CYCLE,
SX1_RD_CYCLE => SX1_RD_CYCLE,
SX1_WR_CYCLE => SX1_WR_CYCLE,
GT_DETECTORS_TO_GR => GT_DETECTORS_TO_GR,
EVEN_HR_0_7_BITS => EVEN_HR_0_7_BITS,
EVEN_GR_0_7_BITS => EVEN_GR_0_7_BITS,
HR_REG_0_7 => HR_REG_0_7,
GR_REG_0_7 => GR_REG_0_7,
DR_CORR_P_BIT => DR_CORR_P_BIT,
HR_REG_P_BIT => HR_REG_P_BIT,
GR_REG_P_BIT => GR_REG_P_BIT,
STORE_HR => STORE_HR,
STORE_GR => STORE_GR,
STORE_R => STORE_R,
MEM_SELECT => STG_MEM_SELECT,
MAN_STORE_PWR => MANUAL_STORE,
E_SW_SEL_R => E_BUS.R_SEL,
GT_HSMPX_INTO_R_REG => GT_HSMPX_INTO_R_REG,
COMPUTE_CY_LCH => CTRL.COMPUTE_CY_LCH,
CLOCK_OFF => sCLOCK_OFF,
ALLOW_WRITE_1 => ALLOW_WRITE_DLYD,
PROT_LOC_CPU_OR_MPX => sPROTECT_LOC_CPU_OR_MPX,
USE_R => USE_R,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAN_STORE => MANUAL_STORE,
DATA_READY => DATA_READY,
MACH_RST_2A => sMACH_RST_2A,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
MN_REG_CHK_SMPLD => MN_REG_CHK_SMPLD,
MEM_WRAP => MEM_WRAP,
MAIN_STG => MAIN_STG,
MACH_RST_6 => MACH_RST_6,
ALLOW_WRITE => ALLOW_WRITE,
ALLOW_PROTECT => ALLOW_PROTECT,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
N1401_MODE => N1401_MODE,
MACH_RST_SW => MACH_RST_SW,
MN => sMN,
N_Z_BUS => sN_Z_BUS,
USE_MAIN_MEM => USE_MAIN_MEM,
USE_LOC_MAIN_MEM => USE_LOC_MAIN_MEM,
PHASE_RD_1 => READ_ECHO_1,
PHASE_RD_2 => READ_ECHO_2,
PHASE_WR_1 => WRITE_ECHO_1,
PHASE_WR_2 => WRITE_ECHO_2,
-- Outputs
STORE_BITS => STORE_BITS,
R_0 => R_0,
R_REG_BUS => sR,
P_8F_DETECTED => P_8F_DETECTED,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3, -- not really needed
T4 => sT4,
clk => clk
);
R <= sR;
SAR_SA : entity SARSA port map (
M_ASSM_BUS => M_ASSM_BUS,
N_ASSM_BUS => N_ASSM_BUS,
MACH_RST_SW => MACH_RST_SW,
MACH_RESET_SET_LCH_DLY => MACH_RST_SET_LCH_DLY ,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
CPU_RD_PWR => CPU_RD_PWR,
SEL_RDWR_CTRL => SEL_R_W_CTRL,
GT_MAN_SET_MN => GT_MAN_SET_MN,
CHNL_RD_CALL => CHNL_RD_CALL,
XH => sXH,
XL => sXL,
XXH => sXXH,
MAIN_STORAGE_CP => MAIN_STORAGE_CP,
MPX_CP => MPX_CP,
MN => sMN,
M_P => sM_P,
N_P => sN_P,
MACH_RST_PROTECT => MACH_RST_PROT,
EARLY_M0 => EARLY_M0,
M_REG_0 => M_REG_0,
SA_REG => SA,
SEL_T1 => SEL_T1,
T1 => sT1
);
S_Reg : entity SReg port map (
CS => CTRL.CTRL_CS,
SA => SALS.SALS_SA,
CD => CTRL.CTRL_CD,
N_Z_BUS => sN_Z_BUS(0 to 7),
Z_BUS0 => sZ_0,
CARRY_0 => sCARRY_0,
Z_BUS_HI_0 => Z_HI_0,
Z_BUS_LO_0 => Z_LO_0,
GT_CARRY_TO_S3 => GT_CARRY_TO_S3,
CTRL_REG_RST => CTRL_REG_RST,
MAN_STOR_PWR => MAN_STOR_PWR,
STORE_S_REG_RST => STORE_S_REG_RST,
E_SW_SEL_S => E_SW_SEL_S,
MACH_RST_2C => MACH_RST_2C,
T_REQUEST => T_REQUEST,
GT_Z_BUS_TO_S => GATE_Z_BUS_TO_S_REG,
S_REG_RST => sS_REG_RST,
FB_K_T2_PULSE => FB_K_T2_PULSE,
CS_DECODE_X001 => CS_DECODE_X001,
BASIC_CS_0 => BASIC_CS0,
P1 => sP1,
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
S => sS,
clk => clk
);
S <= sS;
MN_Ind : entity MNInd port map (
-- Inputs
MN => sMN,
M_P => sM_P,
N_P => sN_P,
LAMP_TEST => LAMP_TEST,
MAIN_STG => MAIN_STG,
LOCAL_STG => LOCAL_STG,
N1401_MODE => N1401_MODE,
-- Outputs
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
MN_PC => sMN_PC
);
MN <= sMN;
-- M_P <= sM_P;
-- N_P <= sN_P;
MN_PC <= sMN_PC;
ChkReg_Ind : entity ChkRegInd port map (
-- Inputs
LAMP_TEST => LAMP_TEST,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
CA_SALS => SALS.SALS_CA,
ROS_SCAN => ROS_SCAN,
MACH_CHK_PULSE => MACH_CHK_PULSE,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
MACH_RST_SW => MACH_RST_SW,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
SET_IND_ROSAR => SET_IND_ROSAR,
MACH_RST_6 => MACH_RST_6,
WX_CHK => WX_CHK,
A_REG_PC => sA_REG_PC,
B_REG_PC => sB_REG_PC,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
ALLOW_WRITE => ALLOW_WRITE,
CTRL_REG_CHK => CTRL_REG_CHK,
SALS_PC => SALS_PC,
R_REG_PC => R_REG_PC,
ALU_CHK => sALU_CHK,
CHK_SW_PROC_SW => CHK_SW_PROC_SW,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
CPU_WR_IN_R_REG => CPU_WR_IN_R_REG,
GT_Q_REG_TO_A_BUS => GT_Q_REG_TO_A_BUS,
STACK_PC => STACK_PC,
MEM_PROT_REQUEST => MEM_PROT_REQUEST,
SEL_CHNL_CHK => SEL_CHNL_CHK,
MACH_CHK_RST => MACH_CHK_RST,
AK_SAL_BIT => SALS.SALS_AK,
CK_SALS => SALS.SALS_CK,
MN_PC => sMN_PC,
N1401_MODE => N1401_MODE,
-- Outputs
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
ALLOW_PC_SALS => ALLOW_PC_SALS,
MN_REG_CHK_SMPLD => MN_REG_CHK_SMPLD,
FIRST_MACH_CHK => FIRST_MACH_CHK,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
ANY_MACH_CHK => ANY_MACH_CHK,
IND_MC_A_REG => IND_CHK_A_REG,
IND_MC_B_REG => IND_CHK_B_REG,
IND_MC_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_MC_CTRL_REG => IND_CHK_CTRL_REG,
IND_MC_ROS_SALS => IND_CHK_ROS_SALS,
IND_MC_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_MC_STOR_DATA => IND_CHK_STOR_DATA,
IND_MC_ALU => IND_CHK_ALU,
MC => MC,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
clk => clk
);
STP : entity QReg_STP port map (
-- Inputs
SA_REG => SA,
Z_BUS => sZ_BUS,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
MAIN_STG => MAIN_STG,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_REG_TO_MN => GT_T_REG_TO_MN,
GT_CK_TO_MN => GT_CK_TO_MN,
MAIN_STG_CP_1 => MAIN_STG_CP_1,
N_STACK_MEMORY_SELECT => N_STACK_MEMORY_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
E_SW_SEL_Q => E_BUS.Q_SEL,
MAN_STORE_PWR => MANUAL_STORE,
T4 => sT4,
MACH_RST_2B => sMACH_RST_2B,
Z_BUS_LO_DIG_PARITY => sZ_BUS_LO_DIGIT_PARITY,
CD_REG => CTRL.CTRL_CD,
CLOCK_OFF => sCLOCK_OFF,
N_SEL_SHARE_HOLD => N_SEL_SHARE_HOLD,
N_MEM_SELECT => N_STACK_MEM_SELECT,
GK => GK,
HK => HK,
CLK => CLOCK_IN,
-- Outputs
Q_REG_BUS => Q_REG_BUS,
SEL_CPU_BUMP => SEL_CPU_BUMP,
STACK_PC => STACK_PC,
MPX_CP => MPX_CP,
MAIN_STG_CP => MAIN_STORAGE_CP,
PROTECT_LOC_CPU_OR_MPX => sPROTECT_LOC_CPU_OR_MPX,
PROTECT_LOC_SEL_CHNL => PROTECT_LOC_SEL_CHNL
);
PROTECT_LOC_CPU_OR_MPX <= sPROTECT_LOC_CPU_OR_MPX;
ARegA : entity ARegAssm port map (
-- Inputs
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
E_SEL_SW_BUS => E_BUS,
GTD_CA_BITS => GATED_CA_BITS,
CHK_SW_DISABLE => CHK_SW_DISABLE,
S => sS,
MC_CTRL_REG => MC,
Q_REG => Q_REG_BUS,
-- Outputs
A_BUS => A_BUS2,
GT_Q_REG_TO_A_BUS => GT_Q_REG_TO_A_BUS
);
MpxReg1 : entity MpxFOFB port map (
-- Inputs
MPX_ROS_LCH => MPX_ROS_LCH, -- 02A
S_REG_0 => sS(0), -- 07B
SET_FW => SET_FW, -- 01B
S_REG_1 => sS(1), -- 07B
S_REG_2 => sS(2), -- 07B
T3 => sT3,
CK_SALS => SALS.SALS_CK,
PK_SALS => SALS.SALS_PK,
FBK_T2 => FB_K_T2_PULSE, -- 07B
MACH_RST_SET_LCH => MACH_RST_SET_LCH, -- 04B
SALS_CS => SALS.SALS_CS,
SALS_SA => SALS.SALS_SA,
CK_0_PWR => SALS.SALS_CK(0), -- 01C
R_REG => sR, -- 06C
T1 => sT1,
T2 => sT2,
-- Outputs
XXH => sXXH, -- 05B 07B
XH => sXH, -- 05B 07B
XL => sXL, -- 05B 07B
FT_7_BIT_MPX_CHNL_INTRP => sFT7, -- 05C 08D
FT_2_BIT_MPX_OPN_LCH => FT2, -- 04A 05C
SUPPR_CTRL_LCH => SUPPR_CTRL_LCH, -- 08D
OP_OUT_SIG => OP_OUT_SIG, -- 08D
MPX_OPN_LT_GATE => MPX_OPN_LT_GATE, -- 10B
MACH_RST_MPX => MACH_RST_MPX, -- 01C
MPX_INTRPT => MPX_INTERRUPT, -- 02A
SX1_MASK => SX1_MASK, -- 12D
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON, -- 04C
SX2_MASK => SX2_MASK, -- 14D
FAK => FAK, -- 08D
SET_BUS_O_CTRL_LCH => SET_BUS_O_CTRL_LCH, -- 08D
MPX_BUS_O_REG(0 to 7) => sFO,-- 08A 08D 05C 11D 13D
MPX_BUS_O_REG(8) => sFO_P,
clk => clk
);
XL <= sXL;
XH <= sXH;
XXH <= sXXH;
FO <= sFO & sFO_P;
FT7 <= sFT7;
MpxChnlCtrls: entity MpxFA port map (
BUS_O_REG(0 to 7) => sFO,
BUS_O_REG(8) => sFO_P,
DIAG_SW => DIAG_SW,
-- MPX physical I/O
MPX_BUS_OUT_BITS => MPX_BUS_O,
MPX_BUS_IN_BITS => MPX_BUS_I,
TAGS_OUT => MPX_TAGS_O,
TAGS_IN => MPX_TAGS_I,
FAK => FAK,
RECYCLE_RST => RECYCLE_RST,
CK_P_BIT => SALS.SALS_PK,
ALU_CHK_LCH => sALU_CHK_LCH,
CHK_SW_PROC_SW => CHK_SW_PROC_SW,
ROS_SCAN => ROS_SCAN,
FBK_T2 => FB_K_T2_PULSE,
FT5_BIT_SEL_IN => FT5,
SERV_IN_SIGNAL => SERV_IN_SIG,
STATUS_IN_SIGNAL => STAT_IN_SIG,
FT3_BIT_MPX_SHARE_REQ => FT3,
MPX_SHARE_REQ => MPX_SHARE_REQ,
T1 => sT1,
T2 => sT2,
T3 => sT3,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
CK_SALS_PWR => SALS.SALS_CK,
SET_BUS_O_CTRL_LCH => SET_BUS_O_CTRL_LCH,
N1401_MODE => N1401_MODE,
-- 1050 attachment
N1050_INSTALLED => '1',
N1050_REQ_IN => '0',
N1050_OP_IN => '0',
N1050_CE_MODE => '0',
N1050_SEL_IN => '0',
N1050_SEL_O => '0',
MPX_METERING_IN => MPX_METERING_IN,
FT7_MPX_CHNL_IN => sFT7,
LOAD_IND => LOAD_IND,
SUPPR_CTRL_LCH => SUPPR_CTRL_LCH,
OP_OUT_SIGNAL => OP_OUT_SIG,
RECYCLE_RESET => RECYCLE_RST,
OP_OUT_SIG => OP_OUT_SIG,
SEL_O_FT6 => FT6,
-- N1050_SEL_OUT => N1050_SEL_OUT,
-- SUPPR_O => SUPPR_O ,
SUPPR_O_FT0 => FT0,
-- OP_OUT => OP_OUT,
METERING_OUT => METERING_OUT,
CLOCK_OUT => CLOCK_OUT,
CLK => CLK,
-- Mpx Indicators
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => ADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT
);
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: gates2030.vhd
-- Creation Date:
-- Description:
-- Definitions of the various types of gate, latches and flipflops used in the 2030.
--
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0
--
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Gates_package is
component PH is port(D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component PHV4 is port(D : in STD_LOGIC_VECTOR(0 to 3); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 3)); end component;
component PHV5 is port(D : in STD_LOGIC_VECTOR(0 to 4); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 4)); end component;
component PHV8 is port(D : in STD_LOGIC_VECTOR(0 to 7); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 7)); end component;
component PHV9 is port(D : in STD_LOGIC_VECTOR(0 to 8); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 8)); end component;
component PHV13 is port(D : in STD_LOGIC_VECTOR(0 to 12); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 12)); end component;
component PHR is port(D,L,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component PHRV is port(D : in STD_LOGIC_VECTOR; L,R: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end component;
component PHSR is port(D,L,S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component FLE is port(S,R,clock: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component FLV is port(S,R: in STD_LOGIC_VECTOR; clock: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end component;
component FLVL is port(S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end component;
--component FLAO is port( S1,S2,S3,R1,R2: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
function mux(sel : in STD_LOGIC; D : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function EvenParity(v : in STD_LOGIC_VECTOR) return STD_LOGIC;
component AR is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DEGLITCH is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DEGLITCH2 is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DelayRisingEdge is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
end Gates_package;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity FLE is port(S,R,clock: in STD_LOGIC; signal Q:out STD_LOGIC); end;
-- FL is no longer an edge-triggered SR flip-flop
architecture slt of FLE is
begin
process (S,R)
begin
if (R='1') then -- Reset takes priority
Q<='0' after 1ns;
elsif (S='1') then
Q<='1' after 1ns;
end if;
end process;
end slt;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end;
-- FLL is a level-triggered SR flip-flop
architecture slt of FLL is
begin
process(S,R)
begin
if (S='1') then -- Set takes priority
Q<='1' after 1ns;
elsif (R='1') then
Q<='0' after 1ns;
end if;
end process;
end slt;
package body Gates_package is
-- Variable width AND-OR multiplexor component
function mux(sel : in STD_LOGIC; D : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias D2:STD_LOGIC_VECTOR(1 to D'LENGTH) is D;
variable Q : STD_LOGIC_VECTOR(1 to D'LENGTH);
begin
if (sel = '1') then
Q := D;
else
Q := (others=>'0');
end if;
return Q;
end function mux;
function EvenParity(v : in STD_LOGIC_VECTOR) return STD_LOGIC is
variable p : STD_LOGIC;
begin
p := '1';
for m in v'range loop
p := p xor v(m);
end loop;
return p;
end;
end Gates_package;
-- Simple PH (polarity hold) latch
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PH is port( D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of PH is
begin
process(L,D)
begin
if (L='1') then
Q <= D;
end if;
end process;
end slt;
-- Simple PH (polarity hold) latch, 4 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV4 is port(D: in STD_LOGIC_VECTOR(0 to 3); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 3)); end;
architecture slt of PHV4 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 5 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV5 is port(D: in STD_LOGIC_VECTOR(0 to 4); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 4)); end;
architecture slt of PHV5 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 8 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV8 is port(D: in STD_LOGIC_VECTOR(0 to 7); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 7)); end;
architecture slt of PHV8 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 9 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV9 is port(D: in STD_LOGIC_VECTOR(0 to 8); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 8)); end;
architecture slt of PHV9 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 13 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV13 is port(D: in STD_LOGIC_VECTOR(0 to 12); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 12)); end;
architecture slt of PHV13 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- PH Latch with reset
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHR is port( D: in STD_LOGIC; L,R: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of PHR is
begin
process (L,D,R)
begin
if (R='1') then
Q <= '0';
elsif (L='1') then
Q <= D;
end if;
end process;
end slt;
-- PH Latch with reset, STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHRV is port(D: in STD_LOGIC_VECTOR; L,R: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end;
architecture slt of PHRV is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,R,D1)
begin
for i in Q'range loop
if (R='1') then
Q(i) <= '0';
elsif (L='1') then
Q(i)<=D1(i);
end if;
end loop;
end process;
end slt;
--- PH Latch with set & reset
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHSR is port(D,L,S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of PHSR is
begin
process (L,D,S,R)
begin
if (R='1') then
Q <= '0';
elsif (S='1') then
Q <= '1';
elsif (L='1') then
Q <= D;
end if;
end process;
end slt;
-- Simple FL (SR) flipflops
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity FLV is port( S,R: in STD_LOGIC_VECTOR; signal clock: STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end;
architecture slt of FLV is
alias S1 : STD_LOGIC_VECTOR(Q'range) is S;
alias R1 : STD_LOGIC_VECTOR(Q'range) is R;
signal S2,R2 : STD_LOGIC_VECTOR(Q'range) := (others=>'0');
begin
process (S1,R1,clock)
begin
if (rising_edge(clock)) then
for i in Q'range loop
if (R(i)/=R2(i) and R(i)='1') then
Q(i) <= '0';
elsif (S(i)/=S2(i) and S(i)='1') then
Q(i) <= '1';
end if;
R2 <= R1;
S2 <= S1;
end loop;
end if;
end process;
end slt;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity FLVL is port( S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end;
architecture slt of FLVL is
alias S1 : STD_LOGIC_VECTOR(Q'range) is S;
alias R1 : STD_LOGIC_VECTOR(Q'range) is R;
begin
process (S1,R1)
begin
for i in Q'range loop
if (S1(i)='1') then -- Set takes priority
Q(i)<='1';
elsif (R1(i)='1') then
Q(i)<='0';
end if;
end loop;
end process;
end slt;
-- Simple 1 cycle delay from line driver (AR)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity AR is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of AR is
signal Q1 : std_logic;
begin
process(D,Clk)
begin
if (rising_edge(Clk)) then
Q <= Q1;
Q1 <= D;
end if;
end process;
end slt;
-- Simple 1 cycle de-glitch
-- LIBRARY ieee;
-- USE ieee.std_logic_1164.all;
-- entity DEGLITCH is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
-- architecture slt of DEGLITCH is
-- signal DD : std_logic_vector(0 to 1);
-- begin
-- process(D,Clk)
-- begin
-- if (rising_edge(Clk)) then
-- DD <= DD(1) & D;
-- end if;
-- end process;
-- with DD select
-- Q <= '0' when "00"|"01", '1' when others ;
-- end slt;
-- Simple 2 cycle de-glitch
-- LIBRARY ieee;
-- USE ieee.std_logic_1164.all;
-- entity DEGLITCH2 is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
-- architecture slt of DEGLITCH2 is
-- signal DD : std_logic_vector(0 to 2);
-- begin
-- process(D,Clk)
-- begin
-- if (rising_edge(Clk)) then
-- DD <= DD(1 to 2) & D;
-- end if;
-- end process;
-- with DD select
-- Q <= '0' when "000"|"001"|"010"|"011", '1' when others ;
-- end slt;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DelayRisingEdgeX is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of DelayRisingEdgeX is
signal Q1 : std_logic_vector(1 to 3) := "000";
begin
process(D,Clk)
begin
if (rising_edge(Clk)) then
if (D='0') then
Q <= '0';
Q1 <= "000";
else if (D='1') and (Q1="111") then
Q <= '1';
Q1 <= "111";
else
Q <= '0';
Q1 <= Q1(2 to 3) & '1';
end if;
end if;
end if;
end process;
end slt;

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LJW2030
An IBM System/360 Model 30 in VHDL
There are two main components to this release:
VHDL for the CPU (with 8k storage) and Multiplexer channel
The microcode image (4k x 55)
I am not claiming copyright to the microcode image - this is based on IBM manuals from 1964-1965 which may or may not be copyrighted themselves.
The VHDL is based on the IBM Maintenance Diagram Manual (MDM), which can be found on Bitsavers.
As supplied, the compiled system is suitable for a Digilent Spartan 3 board with a 1000K device, see http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD
It uses the following I/O:
VGA output (8-colour, 3-bit)
Parallel I/O for switch scanning (10 out, 14 in)
On-board pushbutton inputs (4)
On-board slide switch inputs (8)
On-board LED outputs (8)
If using an alternative board, it may be sufficient to modify the UCF file to reallocate inputs and outputs
These files can be compiled using the Xilinx ISE Webpack (and presumably other versions of the Xilinx suite). I have not tried compiling them with other VHDL compilers.
Apologies for the varied quality of the VHDL. This project has taken over 5 years and I have not necessarily re-visited code that was written early on. So there is a variety of styles and conventions. In my defence, it works (or seems to).
Lawrence Wilkinson
lawrence@ljw.me.uk
2010/07/16

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: cpu.vhd
-- Creation Date: 22:15:23 2010-06-30
-- Description:
-- Top level of the CPU proper, combining all the various modules
-- including Processor, Storage, Multiplexor and (eventually) Selector(s)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity cpu is
Port (
WX_IND : OUT std_logic_vector(0 to 12);
W_IND_P : OUT std_logic;
X_IND_P : OUT std_logic;
IND_SALS : OUT SALS_Bus;
IND_EX,IND_CY_MATCH,IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : OUT STD_LOGIC;
IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
IND_MSDR_P : OUT STD_LOGIC;
IND_OPNL_IN : OUT STD_LOGIC;
IND_ADDR_IN : OUT STD_LOGIC;
IND_STATUS_IN : OUT STD_LOGIC;
IND_SERV_IN : OUT STD_LOGIC;
IND_SEL_OUT : OUT STD_LOGIC;
IND_ADDR_OUT : OUT STD_LOGIC;
IND_CMMD_OUT : OUT STD_LOGIC;
IND_SERV_OUT : OUT STD_LOGIC;
IND_SUPPR_OUT : OUT STD_LOGIC;
IND_FO : OUT STD_LOGIC_VECTOR(0 to 7);
IND_FO_P: OUT STD_LOGIC;
IND_A : OUT STD_LOGIC_VECTOR(0 to 8);
IND_B : OUT STD_LOGIC_VECTOR(0 to 8);
IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8);
IND_M : OUT STD_LOGIC_VECTOR(0 to 8);
IND_N : OUT STD_LOGIC_VECTOR(0 to 8);
IND_MAIN_STG : OUT STD_LOGIC;
IND_LOC_STG : OUT STD_LOGIC;
IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG : OUT STD_LOGIC;
IND_CHK_B_REG : OUT STD_LOGIC;
IND_CHK_STOR_ADDR : OUT STD_LOGIC;
IND_CHK_CTRL_REG : OUT STD_LOGIC;
IND_CHK_ROS_SALS : OUT STD_LOGIC;
IND_CHK_ROS_ADDR : OUT STD_LOGIC;
IND_CHK_STOR_DATA : OUT STD_LOGIC;
IND_CHK_ALU : OUT STD_LOGIC;
IND_SYST : OUT STD_LOGIC;
IND_MAN : OUT STD_LOGIC;
IND_WAIT : OUT STD_LOGIC;
IND_TEST : OUT STD_LOGIC;
IND_LOAD : OUT STD_LOGIC;
SW_START,SW_LOAD,SW_SET_IC,SW_STOP,SW_POWER_OFF : IN std_logic;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
SW_LAMP_TEST,SW_DSPLY,SW_STORE,SW_SYS_RST : IN STD_LOGIC;
SW_CHK_RST,SW_ROAR_RST,SW_CHK_RESTART,SW_DIAGNOSTIC : IN STD_LOGIC;
SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE,SW_ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,SW_ROAR_STOP : IN STD_LOGIC;
SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : IN STD_LOGIC;
SW_INTRP_TIMER, SW_CONS_INTRP : IN STD_LOGIC;
SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
E_SW : E_SW_BUS_Type;
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
MPX_TAGS_I : IN MPX_TAGS_IN;
DEBUG : OUT STD_LOGIC;
USE_MAN_DECODER_PWR : OUT STD_LOGIC;
N60_CY_TIMER_PULSE : IN STD_LOGIC;
M_CONV_OSC : OUT STD_LOGIC;
SwSlow : in std_logic;
clk : in std_logic);
end cpu;
architecture FMD of cpu is
-- Outputs from UDC1 (5-01 through 5-05)
signal sSALS : SALS_Bus;
signal CTRL : CTRL_REG;
signal T1,T2,T3,T4 : std_logic;
signal SEL_T1, SEL_T3, SEL_T4 : std_logic;
signal P1,P2,P3,P4 : std_logic;
signal A_BUS, B_BUS : std_logic_vector(0 to 8);
signal CLOCK_START : std_logic;
signal CLOCK_ON : std_logic;
signal STORE_S_REG_RST : std_logic; -- 03DC2
signal CTRL_REG_RST : std_logic; -- 01CB2
signal TO_KEY_SW : std_logic;
signal METERING_OUT : std_logic;
signal GT_1050_TAGS : std_logic;
signal GT_1050_BUS : std_logic;
signal SET_IND_ROSAR : STD_LOGIC;
signal GT_LOCAL_STORAGE : STD_LOGIC;
signal GT_T_REG_TO_MN : STD_LOGIC;
signal GT_CK_TO_MN : STD_LOGIC;
signal N_STACK_MEM_SELECT : STD_LOGIC;
signal WX_CHK : STD_LOGIC;
-- Outputs from UDC2 (5-06 through 5-09C)
signal Z_BUS,R : std_logic_vector(0 to 8);
signal MN : std_logic_vector(0 to 15);
signal CLOCK_OFF : std_logic;
signal A_REG_PC : std_logic;
signal MN_PC : std_logic;
signal Z0_BUS_0 : std_logic;
signal Z_0 : std_logic;
signal N_CTRL_N : std_logic;
signal ALU_CHK_LCH : std_logic;
signal SELECT_CPU_BUMP : std_logic;
signal sMPX_BUS_O : std_logic_vector(0 to 8);
-- Outputs from UDC3 (5-10A through 5-14D)
signal SEL_WR_CALL : STD_LOGIC := '0';
signal SX1_SHARE_CYCLE : STD_LOGIC := '0';
signal SX2_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_AUX_WR_CALL : STD_LOGIC := '0';
signal SEL_AUX_RD_CALL : STD_LOGIC := '0';
signal SEL_CONV_OSC : STD_LOGIC;
signal SEL_BASIC_CLOCK_OFF : STD_LOGIC;
signal SEL_SHARE_HOLD : STD_LOGIC := '0';
signal SEL_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_CHNL_DATA_XFER : STD_LOGIC := '0';
signal SEL_ROS_REQ : STD_LOGIC := '0';
signal SEL_READ_CALL : STD_LOGIC := '0';
signal SEL_RD_WR_CTRL : STD_LOGIC := '0';
signal SEL_RD_CALL_TO_STP : STD_LOGIC := '0';
signal SEL_CC_ROS_REQ : STD_LOGIC := '0';
signal MAN_DSPLY_GUV_HUV : STD_LOGIC := '0';
signal HSMPX_TRAP : STD_LOGIC := '0';
-- Inputs to UDC3
signal SEL_DATA_READY : STD_LOGIC;
signal SEL_CHNL_CPU_CLOCK_STOP : STD_LOGIC;
signal RST_SEL_CHNL_DIAG_LCHS : STD_LOGIC;
signal LOAD_REQ_LCH : STD_LOGIC;
signal USE_GR_OR_HR : STD_LOGIC;
signal SX_CHAIN_PULSE_1 : STD_LOGIC;
signal CHK_RST_SW : STD_LOGIC;
signal S : std_logic_vector(0 to 7);
signal sM_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : std_logic;
signal MACH_RST_2A,MACH_RST_2B,MACH_RST_3, MACH_RST_6 : std_logic;
signal CARRY_0 : STD_LOGIC;
signal COMPLEMENT,NTRUE : STD_LOGIC;
signal FT0,FT1,FT2,FT3,FT5,FT6,FT7 : STD_LOGIC;
signal M_ASSM_BUS1, N_ASSM_BUS1 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS2, N_ASSM_BUS2 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS3, N_ASSM_BUS3 : STD_LOGIC_VECTOR(0 to 8) := "000000000";
signal N1050_INTRV_REQ : STD_LOGIC := '0';
signal TT6_POS_ATTN : STD_LOGIC := '0';
signal FT2_MPX_OPNL : STD_LOGIC := '0';
signal MPX_METERING_IN,METER_IN_SX1,METER_IN_SX2 : STD_LOGIC;
signal KEY_SW : STD_LOGIC;
signal GT_SWS_TO_WX_PWR : STD_LOGIC;
signal GT_MAN_SET_MN : STD_LOGIC;
signal EXT_TRAP_MASK_ON : STD_LOGIC;
signal MANUAL_STORE,MAN_STOR_OR_DSPLY : STD_LOGIC;
signal RECYCLE_RST : STD_LOGIC;
signal T_REQUEST : STD_LOGIC := '0';
signal MACH_RST_SET_LCH : STD_LOGIC;
signal RST_LOAD : STD_LOGIC;
signal CARRY_0_LCHD,CARRY_1_LCHD : STD_LOGIC;
signal ALU_CHK : STD_LOGIC;
signal CTRL_N,N_CTRL_LM : STD_LOGIC;
signal SX1_RD_CYCLE,SX2_RD_CYCLE : STD_LOGIC;
signal SX1_WR_CYCLE,SX2_WR_CYCLE : STD_LOGIC;
signal GT_DETECTORS_TO_HR : STD_LOGIC;
signal CPU_RD_PWR : STD_LOGIC;
signal XH,XL,XXH : STD_LOGIC;
signal SET_FW : STD_LOGIC;
signal keyboard_data : STD_LOGIC_VECTOR(7 downto 0);
signal keyboard_error : STD_LOGIC;
signal USE_MANUAL_DECODER : STD_LOGIC;
signal sUSE_MAN_DECODER_PWR : STD_LOGIC;
signal LOCAL_STORAGE_CP, MAIN_STORAGE_CP : STD_LOGIC;
signal STACK_RD_WR_CONTROL : STD_LOGIC;
signal H_REG_5_PWR : STD_LOGIC;
signal FORCE_M_REG_123 : STD_LOGIC;
signal N_SEL_SHARE_HOLD : STD_LOGIC;
signal GK,HK : STD_LOGIC_VECTOR(0 to 3);
signal PROT_LOC_CPU_OR_MPX : STD_LOGIC;
signal PROT_LOC_SEL_CHNL : STD_LOGIC;
signal EARLY_M_REG_0 : STD_LOGIC;
signal ODD : STD_LOGIC; -- 06B to 04A
signal SUPPR_A_REG_CHK : STD_LOGIC;
signal STATUS_IN_LCHD : STD_LOGIC;
signal M_REG_0 : STD_LOGIC;
signal SYS_RST_PRIORITY_LCH : STD_LOGIC;
signal STORE_R : STD_LOGIC;
signal SAL_PC : STD_LOGIC;
signal R_REG_PC : STD_LOGIC;
signal N2ND_ERROR_STOP : STD_LOGIC;
signal MEM_WRAP : STD_LOGIC;
signal MACH_RST_PROT : STD_LOGIC;
signal MACH_RST_MPX : STD_LOGIC;
signal GM_WM_DETECTED : STD_LOGIC;
signal FIRST_MACH_CHK_REQ : STD_LOGIC;
signal FIRST_MACH_CHK : STD_LOGIC;
signal DECIMAL : STD_LOGIC;
signal INTRODUCE_ALU_CHK : STD_LOGIC;
signal SERV_IN_LCHD, ADDR_IN_LCHD, OPNL_IN_LCHD : STD_LOGIC;
signal MPX_SHARE_REQ, MPX_INTERRUPT : STD_LOGIC;
signal CS_DECODE_X001 : STD_LOGIC;
signal SX1_INTERRUPT, SX2_INTERRUPT : STD_LOGIC;
signal SX_1_GATE, SX_2_GATE : STD_LOGIC;
signal SX_1_R_W_CTRL, SX_2_R_W_CTRL : STD_LOGIC;
signal SX_2_BUMP_SW_GT : STD_LOGIC;
signal FT3_MPX_SHARE_REQ : STD_LOGIC;
signal CONNECT : STD_LOGIC;
signal P_8F_DETECTED : STD_LOGIC;
signal BASIC_CS0 : STD_LOGIC;
signal USE_R : STD_LOGIC;
signal ANY_MACH_CHK : STD_LOGIC;
signal USE_MAIN_MEMORY, USE_LOCAL_MAIN_MEMORY : STD_LOGIC;
signal ALLOW_PROTECT : STD_LOGIC;
signal USE_BASIC_CA_DECO, USE_ALT_CA_DECODER : STD_LOGIC;
signal ALLOW_PC_SALS : STD_LOGIC;
signal SUPPR_MACH_CHK_TRAP : STD_LOGIC;
signal N1401_MODE : STD_LOGIC;
signal MEM_PROTECT_REQUEST : STD_LOGIC;
signal MANUAL_DISPLAY : STD_LOGIC;
signal MAIN_STORAGE : STD_LOGIC;
signal MACH_RST_SET_LCH_DLY : STD_LOGIC;
signal MACH_RST_SW : STD_LOGIC;
signal MACH_CHK_RST : STD_LOGIC;
signal MACH_CHK_PULSE : STD_LOGIC;
signal GT_D_REG_TO_A_BUS : STD_LOGIC;
signal GT_CA_TO_W_REG : STD_LOGIC;
signal DATA_READY : STD_LOGIC;
signal CTRL_REG_CHK : STD_LOGIC;
signal CPU_WRITE_IN_R_REG : STD_LOGIC;
signal CPU_SET_ALLOW_WR_LCH : STD_LOGIC;
signal ANY_PRIORITY_LCH : STD_LOGIC;
signal ALLOW_WRITE_DLYD : STD_LOGIC;
signal ALLOW_WRITE : STD_LOGIC;
signal STORE_HR : STD_LOGIC;
signal STORE_GR : STD_LOGIC;
signal SEL_R_W_CTRL : STD_LOGIC;
signal SEL_CHNL_CHK : STD_LOGIC;
signal HR_REG_0_7, GR_REG_0_7 : STD_LOGIC_VECTOR(0 to 7);
signal STORE_BITS : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal HR_REG_P_BIT : STD_LOGIC;
signal GR_REG_P_BIT : STD_LOGIC;
signal GT_DETECTORS_TO_GR : STD_LOGIC;
signal EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : STD_LOGIC;
signal CHANNEL_RD_CALL : STD_LOGIC;
signal MPX_ROS_LCH : STD_LOGIC;
signal CK_SAL_P_BIT_TO_MPX : STD_LOGIC;
signal STG_MEM_SEL : STD_LOGIC;
signal GATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal CLOCK_START_LCH : STD_LOGIC;
signal LOAD_IND : STD_LOGIC;
signal CLOCK_OUT : STD_LOGIC;
signal READ_ECHO_1, READ_ECHO_2, WRITE_ECHO_1, WRITE_ECHO_2 : STD_LOGIC;
signal DIAGNOSTIC_SW : STD_LOGIC;
begin
firstBit: entity udc1 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
WX_IND => WX_IND,
X_IND_P => X_IND_P,
W_IND_P => W_IND_P,
A_BUS => A_BUS,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
MPX_BUS => sMPX_BUS_O,
S => S,
R => R,
MN => MN,
M_ASSM_BUS => M_ASSM_BUS1,
N_ASSM_BUS => N_ASSM_BUS1,
SW_START => SW_START,
SW_LOAD => SW_LOAD,
SW_SET_IC => SW_SET_IC,
SW_STOP => SW_STOP,
SW_INH_CF_STOP => SW_INH_CF_STOP,
SW_PROC => SW_PROC,
SW_SCAN => SW_SCAN,
SW_SINGLE_CYCLE => SW_SINGLE_CYCLE,
SW_INSTRUCTION_STEP => SW_INSTRUCTION_STEP,
SW_RATE_SW_PROCESS => SW_RATE_SW_PROCESS,
SW_PWR_OFF => SW_POWER_OFF,
SW_LAMP_TEST => SW_LAMP_TEST,
SW_DSPLY => SW_DSPLY,
SW_STORE => SW_STORE,
SW_SYS_RST => SW_SYS_RST,
SW_CHK_RST => SW_CHK_RST,
SW_ROAR_RST => SW_ROAR_RST,
SW_CHK_RESTART => SW_CHK_RESTART,
SW_DIAGNOSTIC => SW_DIAGNOSTIC,
SW_CHK_STOP => SW_CHK_STOP,
SW_CHK_SW_PROCESS => SW_CHK_SW_PROCESS,
SW_CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
SW_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SW_ROAR_RESTT => SW_ROAR_RESTT,
SW_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
SW_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
SW_ROAR_STOP => SW_ROAR_STOP,
SW_ROAR_SYNC => SW_ROAR_SYNC,
SW_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
SW_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
SW_SAR_STOP => SW_SAR_STOP,
SW_SAR_RESTART => SW_SAR_RESTART,
SW_INTRP_TIMER => SW_INTRP_TIMER,
SW_CONS_INTRP => SW_CONS_INTRP,
SW_A => SW_A,SW_B => SW_B,SW_C => SW_C,SW_D => SW_D,
SW_F => SW_F,SW_G => SW_G,SW_H => SW_H,SW_J => SW_J,
SW_AP => SW_AP,SW_BP => SW_BP,SW_CP => SW_CP,SW_DP => SW_DP,
SW_FP => SW_FP,SW_GP => SW_GP,SW_HP => SW_HP,SW_JP => SW_JP,
TO_KEY_SW => TO_KEY_SW,
E_SW => E_SW, -- Main E switch bus
IND_SYST => IND_SYST,
IND_MAN => IND_MAN,
IND_WAIT => IND_WAIT,
IND_TEST => IND_TEST,
IND_LOAD => IND_LOAD,
IND_EX => IND_EX,
IND_CY_MATCH => IND_CY_MATCH,
IND_ALLOW_WR => IND_ALLOW_WR,
IND_1050_INTRV => IND_1050_INTRV,
IND_1050_REQ => IND_1050_REQ,
IND_MPX => IND_MPX,
IND_SEL_CHNL => IND_SEL_CHNL,
IND_MSDR => IND_MSDR,
IND_MSDR_P => IND_MSDR_P,
CARRY_0 => CARRY_0,
CARRY_0_LCHD => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
COMPLEMENT => COMPLEMENT,
NTRUE => NTRUE,
MPX_METERING_IN => MPX_METERING_IN,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
METER_IN_SX1 => METER_IN_SX1,
METER_IN_SX2 => METER_IN_SX2,
KEY_SW => KEY_SW,
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE,
N1050_INTRV_REQ => N1050_INTRV_REQ,
GT_1050_TAGS => GT_1050_TAGS,
GT_1050_BUS => GT_1050_BUS,
TT6_POS_ATTN => TT6_POS_ATTN,
FT2_MPX_OPNL => FT2_MPX_OPNL,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
FT0 => FT0,
FT1 => FT1,
FT2 => FT2,
FT3 => FT3,
FT5 => FT5,
FT6 => FT6,
FT7 => FT7,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
ALU_CHK => ALU_CHK,
CTRL_N => CTRL_N,
N_CTRL_N => N_CTRL_N,
N_CTRL_LM => N_CTRL_LM,
STORE_S_REG_RST => STORE_S_REG_RST,
MAIN_STORAGE_CP => MAIN_STORAGE_CP,
LOCAL_STORAGE_CP => LOCAL_STORAGE_CP,
SET_IND_ROSAR => SET_IND_ROSAR,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_TO_MN_REG => GT_T_REG_TO_MN,
GT_CK_TO_MN_REG => GT_CK_TO_MN,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
PROT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
WX_CHK => WX_CHK,
EARLY_M_REG_0 => EARLY_M_REG_0,
ODD => ODD,
XH => XH,
XL => XL,
XXH => XXH,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
M_REG_0 => M_REG_0,
SYS_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
STORE_R => STORE_R,
SAL_PC => SAL_PC,
R_REG_PC => R_REG_PC,
RST_LOAD => RST_LOAD,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
MACH_RST_PROT => MACH_RST_PROT,
MACH_RST_MPX => MACH_RST_MPX,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
GM_WM_DETECTED => GM_WM_DETECTED,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
DECIMAL => DECIMAL,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MPX_SHARE_REQ => MPX_SHARE_REQ,
MPX_INTERRUPT => MPX_INTERRUPT,
CS_DECODE_X001 => CS_DECODE_X001,
CLOCK_OFF => CLOCK_OFF,
CONNECT => CONNECT,
P_8F_DETECTED => P_8F_DETECTED,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALU_CHK_LCH => ALU_CHK_LCH,
ALLOW_PROTECT => ALLOW_PROTECT,
ALLOW_PC_SALS => ALLOW_PC_SALS,
USE_R => USE_R,
USE_BASIC_CA_DECODER => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SEL => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STORAGE => MAIN_STORAGE,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WRITE_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE => ALLOW_WRITE,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
GT_MAN_SET_MN => GT_MAN_SET_MN,
MPX_ROS_LCH => MPX_ROS_LCH,
CTRL_REG_RST => CTRL_REG_RST,
CK_SAL_P_BIT_TO_MPX => CK_SAL_P_BIT_TO_MPX,
CHANNEL_RD_CALL => CHANNEL_RD_CALL,
GTD_CA_BITS => GATED_CA_BITS,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_MAIN_MEMORY => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
SELECT_CPU_BUMP => SELECT_CPU_BUMP,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
CPU_RD_PWR => CPU_RD_PWR,
LOAD_IND => LOAD_IND,
SET_FW => SET_FW,
MACH_RST_SW => MACH_RST_SW,
LOAD_REQ_LCH => LOAD_REQ_LCH,
USE_GR_OR_HR => USE_GR_OR_HR,
SX_CHAIN_PULSE_1 => SX_CHAIN_PULSE_1,
CHK_RST_SW => CHK_RST_SW,
DIAGNOSTIC_SW => DIAGNOSTIC_SW,
MAN_DSPLY_GUV_HUV => MAN_DSPLY_GUV_HUV,
HSMPX_TRAP => HSMPX_TRAP,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SX_1_R_W_CTRL => SX_1_R_W_CTRL,
SX_2_R_W_CTRL => SX_2_R_W_CTRL,
SX_2_BUMP_SW_GT => SX_2_BUMP_SW_GT,
SEL_WR_CALL => SEL_WR_CALL,
SEL_AUX_WR_CALL => SEL_AUX_WR_CALL,
SEL_AUX_RD_CALL => SEL_AUX_RD_CALL,
SEL_T1 => SEL_T1,
SEL_T4 => SEL_T4,
SEL_CONV_OSC => SEL_CONV_OSC,
SEL_BASIC_CLOCK_OFF => SEL_BASIC_CLOCK_OFF,
SEL_SHARE_HOLD => SEL_SHARE_HOLD,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_CHNL_DATA_XFER => SEL_CHNL_DATA_XFER,
SEL_ROS_REQ => SEL_ROS_REQ,
SEL_READ_CALL => SEL_READ_CALL,
SEL_RD_WR_CTRL => SEL_RD_WR_CTRL,
SEL_RD_CALL_TO_STP => SEL_RD_CALL_TO_STP,
SEL_CHNL_CPU_CLOCK_STOP => SEL_CHNL_CPU_CLOCK_STOP,
RST_SEL_CHNL_DIAG_LCHS => RST_SEL_CHNL_DIAG_LCHS,
SEL_CC_ROS_REQ => SEL_CC_ROS_REQ,
SX1_INTERRUPT => SX1_INTERRUPT,
SX2_INTERRUPT => SX2_INTERRUPT,
SX_1_GATE => SX_1_GATE,
SX_2_GATE => SX_2_GATE,
CLOCK_ON => CLOCK_ON,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_START => CLOCK_START,
CLOCK_START_LCH => CLOCK_START_LCH,
-- UDC1 Debug stuff
DEBUG => DEBUG,
-- End of Debug stuff
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P4 => P4,
CLK => CLK
);
IND_SALS <= sSALS;
USE_MAN_DECODER_PWR <= sUSE_MAN_DECODER_PWR;
secondBit: entity udc2 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
A_BUS1 => A_BUS,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
E_BUS => E_SW,
M_ASSM_BUS => M_ASSM_BUS2,
N_ASSM_BUS => N_ASSM_BUS2,
S => S,
R => R,
MN => MN,
Sw_Slow => SwSlow,
CLOCK_START => CLOCK_START,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
CLOCK_IN => clk,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_ON => CLOCK_ON,
LAMP_TEST => SW_LAMP_TEST,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
DIAG_SW => DIAGNOSTIC_SW,
CHK_SW_PROC_SW => SW_CHK_SW_PROCESS,
ROS_SCAN => SW_SCAN,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
RST_LOAD => RST_LOAD,
SYSTEM_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
CARRY_0_LATCHED => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
ALU_CHK => ALU_CHK,
NTRUE => NTRUE,
COMPLEMENT => COMPLEMENT,
P_CTRL_N => CTRL_N,
N_CTRL_LM => N_CTRL_LM,
SX1_RD_CYCLE => SX1_RD_CYCLE,
SX2_RD_CYCLE => SX2_RD_CYCLE,
SX1_WR_CYCLE => SX1_WR_CYCLE,
SX2_WR_CYCLE => SX2_WR_CYCLE,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
CPU_RD_PWR => CPU_RD_PWR,
GT_MAN_SET_MN => GT_MAN_SET_MN,
CHNL_RD_CALL => CHANNEL_RD_CALL,
XH => XH,
XL => XL,
XXH => XXH,
MAN_STOR_PWR => MANUAL_STORE,
STORE_S_REG_RST => STORE_S_REG_RST,
E_SW_SEL_S => E_SW.S_SEL,
CTRL_REG_RST => CTRL_REG_RST,
CLOCK_OFF => CLOCK_OFF,
A_REG_PC => A_REG_PC,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
P_CONNECT => CONNECT,
N_CTRL_N => N_CTRL_N,
ALU_CHK_LCH => ALU_CHK_LCH,
MN_PC => MN_PC,
SET_IND_ROSAR => SET_IND_ROSAR,
N_STACK_MEMORY_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_REG_TO_MN => GT_T_REG_TO_MN, -- from 05B
GT_CK_TO_MN => GT_CK_TO_MN,
MAIN_STG_CP_1 => MAIN_STORAGE_CP,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
SEL_CPU_BUMP => SELECT_CPU_BUMP,
PROTECT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
PROTECT_LOC_SEL_CHNL => PROT_LOC_SEL_CHNL,
WX_CHK => WX_CHK,
EARLY_M0 => EARLY_M_REG_0,
ODD => ODD,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
STORE_R => STORE_R,
SALS_PC => SAL_PC,
R_REG_PC => R_REG_PC,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
USE_R => USE_R,
USE_MAIN_MEM => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SELECT => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STG => MAIN_STORAGE,
MACH_RST_SW => MACH_RST_SW,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
LOCAL_STG => LOCAL_STORAGE_CP,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WR_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
ALLOW_WRITE => ALLOW_WRITE,
T_REQUEST => T_REQUEST,
P_8F_DETECTED => P_8F_DETECTED,
CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
GATED_CA_BITS => GATED_CA_BITS,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALLOW_PC_SALS => ALLOW_PC_SALS,
CARRY_0 => CARRY_0,
ALLOW_PROTECT => ALLOW_PROTECT,
CS_DECODE_X001 => CS_DECODE_X001,
DECIMAL => DECIMAL,
M_REG_0 => M_REG_0,
MACH_RST_PROT => MACH_RST_PROT,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
MPX_ROS_LCH => MPX_ROS_LCH,
FT7 => FT7,
FT6 => FT6,
FT5 => FT5,
FT2 => FT2,
FT0 => FT0,
FT3 => FT3,
MPX_INTERRUPT => MPX_INTERRUPT,
MPX_METERING_IN => MPX_METERING_IN,
STORE_BITS => STORE_BITS,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MACH_RST_MPX => MACH_RST_MPX,
SET_FW => SET_FW,
MPX_SHARE_REQ => MPX_SHARE_REQ,
LOAD_IND => LOAD_IND,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
-- Signals from UDC3
N_SEL_SHARE_HOLD => N_SEL_SHARE_HOLD, -- from 12D
GK => GK, -- from 11B
HK => HK, -- from 13B
STORE_HR => STORE_HR,
STORE_GR => STORE_GR,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_R_W_CTRL => SEL_R_W_CTRL,
SEL_CHNL_CHK => SEL_CHNL_CHK,
HR_REG_0_7 => HR_REG_0_7,
GR_REG_0_7 => GR_REG_0_7,
HR_REG_P_BIT => HR_REG_P_BIT,
GR_REG_P_BIT => GR_REG_P_BIT,
GT_HSMPX_INTO_R_REG => '0',
DR_CORR_P_BIT => '0',
GT_DETECTORS_TO_HR => GT_DETECTORS_TO_HR,
GT_DETECTORS_TO_GR => GT_DETECTORS_TO_GR,
EVEN_HR_0_7_BITS => EVEN_HR_0_7_BITS,
EVEN_GR_0_7_BITS => EVEN_GR_0_7_BITS,
-- Indicators
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
IND_CHK_A_REG => IND_CHK_A_REG,
IND_CHK_B_REG => IND_CHK_B_REG,
IND_CHK_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_CHK_CTRL_REG => IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS => IND_CHK_ROS_SALS,
IND_CHK_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_CHK_STOR_DATA => IND_CHK_STOR_DATA,
IND_CHK_ALU => IND_CHK_ALU,
-- Selector & Mpx channels
MPX_BUS_O => sMPX_BUS_O,
MPX_BUS_I => MPX_BUS_I,
MPX_TAGS_O => MPX_TAGS_O,
MPX_TAGS_I => MPX_TAGS_I,
-- UDC2 Debug stuff
-- DEBUG => DEBUG,
SEL_T1 => SEL_T1,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
SEL_T3 => SEL_T3,
Clk => Clk
);
M_CONV_OSC <= sM_CONV_OSC;
-- Temporary substitutes for UDC3
SEL_CONV_OSC <= P_CONV_OSC; -- 12A
SEL_BASIC_CLOCK_OFF <= not CLOCK_ON and not CLOCK_START_LCH; -- 12A
-- Combining buses
M_ASSM_BUS2 <= M_ASSM_BUS1 or M_ASSM_BUS3;
N_ASSM_BUS2 <= N_ASSM_BUS1 or N_ASSM_BUS3;
end FMD;

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# Spartan-3 Starter Board, Digilent
# pin locations
# Original by Pierre Langlois, 2004/07/22
# minimal translation by Capt. LeSauvage 2004/09/23
# LJW2030 version by Lawrence Wilkinson, 2010/07/16
#
# Remove the comment symbols (#) in front of the desired lines.
# The names of the ports must match exactly between this file and the design.
# clock
NET "clk" LOC = "T9"; # 50 MHz
# LEDs
NET "led<7>" LOC = "P11";
NET "led<6>" LOC = "P12";
NET "led<5>" LOC = "N12";
NET "led<4>" LOC = "P13";
NET "led<3>" LOC = "N14";
NET "led<2>" LOC = "L12";
NET "led<1>" LOC = "P14";
NET "led<0>" LOC = "K12";
# slide switches
NET "sw<7>" LOC = "K13";
NET "sw<6>" LOC = "K14";
NET "sw<5>" LOC = "J13";
NET "sw<4>" LOC = "J14";
NET "sw<3>" LOC = "H13";
NET "sw<2>" LOC = "H14";
NET "sw<1>" LOC = "G12";
NET "sw<0>" LOC = "F12";
# push buttons
NET "pb<3>" LOC = "L14";
NET "pb<2>" LOC = "L13";
NET "pb<1>" LOC = "M14";
NET "pb<0>" LOC = "M13";
# seven segment display - shared segments
#NET "ssd<7>" LOC = "P16";
#NET "ssd<6>" LOC = "N16";
#NET "ssd<5>" LOC = "F13";
#NET "ssd<4>" LOC = "R16";
#NET "ssd<3>" LOC = "P15";
#NET "ssd<2>" LOC = "N15";
#NET "ssd<1>" LOC = "G13";
#NET "ssd<0>" LOC = "E14";
# seven segment display - anodes
#NET "ssdan<3>" LOC = "E13";
#NET "ssdan<2>" LOC = "F14";
#NET "ssdan<1>" LOC = "G14";
#NET "ssdan<0>" LOC = "D14";
# VGA port
NET "vga_r" LOC = "R12";
NET "vga_g" LOC = "T12";
NET "vga_b" LOC = "R11";
NET "vga_hs" LOC = "R9";
NET "vga_vs" LOC = "T10";
# PS/2 port
#NET "ps2_clk" LOC="M16";
#NET "ps2_data" LOC="M15";
# Expansion ports
#A1
#A2
# 1 Gnd
# 2 VU (+5V)
# 3 Vcco (+3.3V)
NET "pa_io1" LOC="E6"; # HexSw Bit0
NET "pa_io1" PULLDOWN;
NET "pa_io2" LOC="D5"; # HexSw Bit1
NET "pa_io2" PULLDOWN;
NET "pa_io3" LOC="C5"; # HexSw Bit2
NET "pa_io3" PULLDOWN;
NET "pa_io4" LOC="D6"; # HexSw Bit3
NET "pa_io4" PULLDOWN;
NET "pa_io5" LOC="C6"; # HexSwA
NET "pa_io6" LOC="E7"; # HexSwB
# 10:
NET "pa_io7" LOC="C7"; # HexSwC
NET "pa_io8" LOC="D7"; # HexSwD
NET "pa_io9" LOC="C8"; # HexSwE
NET "pa_io10" LOC="D8"; # HexSwF
NET "pa_io11" LOC="C9"; # HexSwG
NET "pa_io12" LOC="D10"; # HexSwH
NET "pa_io13" LOC="A3"; # HexSwJ
NET "pa_io14" LOC="B4"; # HexSwAdrComp
NET "pa_io15" LOC="A4"; # SwE Inner
NET "pa_io15" PULLDOWN;
NET "pa_io16" LOC="B5"; # SwE Outer
NET "pa_io16" PULLDOWN;
# 20:
NET "pa_io17" LOC="A5"; # ROS Ctl INH_CF_STOP
NET "pa_io17" PULLDOWN;
NET "pa_io18" LOC="B6"; # ROS Ctl SCAN
NET "pa_io18" PULLDOWN;
NET "ma2_db0" LOC="B7"; # Rate INST_STEP
NET "ma2_db0" PULLDOWN;
NET "ma2_db1" LOC="A7"; # Rate SINGLE_CYCLE
NET "ma2_db1" PULLDOWN;
NET "ma2_db2" LOC="B8"; # Chk Ctk DIAGNOSTIC
NET "ma2_db2" PULLDOWN;
NET "ma2_db3" LOC="A8"; # Chk Ctl DISABLE
NET "ma2_db3" PULLDOWN;
NET "ma2_db4" LOC="A9"; # Chk Ctl STOP
NET "ma2_db4" PULLDOWN;
NET "ma2_db5" LOC="B10"; # Chk Ctl RESTART
NET "ma2_db5" PULLDOWN;
#NET "ma2_db6" LOC="A10"; # Sys Reset
#NET "ma2_db6" PULLDOWN;
#NET "ma2_db7" LOC="B11"; # ROAR Reset
#NET "ma2_db7" PULLDOWN;
# 30:
#NET "ma2_astb" LOC="B12"; # Start
#NET "ma2_astb" PULLDOWN;
#NET "ma2_dstb" LOC="A12"; # Stop
#NET "ma2_dstb" PULLDOWN;
#NET "ma2_write" LOC="B13"; # Display
#NET "ma2_write" PULLDOWN;
#NET "ma2_wait" LOC="A13"; # Store
#NET "ma2_wait" PULLDOWN;
#NET "ma2_reset" LOC="B14"; # Set IC
#NET "ma2_reset" PULLDOWN;
#NET "ma2_int" LOC="D9"; # Check Reset
#NET "ma2_int" PULLDOWN;
#NET "progb" LOC="B3";
#NET "fpgadone" LOC="R14";
#NET "fpgainitb" LOC="N9";
#NET "fpgacclk" LOC="T15";
#NET "din" LOC="M11";
#A3
# SRAM
# NET "sramaddr<17>" LOC="L3";
# NET "sramaddr<16>" LOC="K5";
# NET "sramaddr<15>" LOC="K3";
# NET "sramaddr<14>" LOC="J3";
# NET "sramaddr<13>" LOC="J4";
# NET "sramaddr<12>" LOC="H4";
# NET "sramaddr<11>" LOC="H3";
# NET "sramaddr<10>" LOC="G5";
# NET "sramaddr<09>" LOC="E4";
# NET "sramaddr<08>" LOC="E3";
# NET "sramaddr<07>" LOC="F4";
# NET "sramaddr<06>" LOC="F3";
# NET "sramaddr<05>" LOC="G4";
# NET "sramaddr<04>" LOC="L4";
# NET "sramaddr<03>" LOC="M3";
# NET "sramaddr<02>" LOC="M4";
# NET "sramaddr<01>" LOC="N3";
# NET "sramaddr<00>" LOC="L5";
# NET "srama<15>" LOC="R1";
# NET "srama<14>" LOC="P1";
# NET "srama<13>" LOC="L2";
# NET "srama<12>" LOC="J2";
# NET "srama<11>" LOC="H1";
# NET "srama<10>" LOC="F2";
# NET "srama<09>" LOC="P8";
# NET "srama<08>" LOC="D3";
# NET "srama<07>" LOC="B1";
# NET "srama<06>" LOC="C1";
# NET "srama<05>" LOC="C2";
# NET "srama<04>" LOC="R5";
# NET "srama<03>" LOC="T5";
# NET "srama<02>" LOC="R6";
# NET "srama<01>" LOC="T8";
# NET "srama<00>" LOC="N7";
# NET "sramace" LOC="P7";
# NET "sramaub" LOC="T4";
# NET "sramalb" LOC="P6";
# NET "sramb<15>" LOC="N1";
# NET "sramb<14>" LOC="M1";
# NET "sramb<13>" LOC="K2";
# NET "sramb<12>" LOC="C3";
# NET "sramb<11>" LOC="F5";
# NET "sramb<10>" LOC="G1";
# NET "sramb<09>" LOC="E2";
# NET "sramb<08>" LOC="D2";
# NET "sramb<07>" LOC="D1";
# NET "sramb<06>" LOC="E1";
# NET "sramb<05>" LOC="G2";
# NET "sramb<04>" LOC="J1";
# NET "sramb<03>" LOC="K1";
# NET "sramb<02>" LOC="M2";
# NET "sramb<01>" LOC="N2";
# NET "sramb<00>" LOC="P2";
# NET "srambce" LOC="N5";
# NET "srambub" LOC="R4";
# NET "sramblb" LOC="P5";
# For the other peripherals and ports listed here,
# consult the Xilinx documentation.
# RS-232 port
# expansion connectors

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030.vhd
-- Creation Date: 21:17:39 2005-04-18
-- Description:
-- Top-level System360/30, including CPU, Panel Lamps and Panel Switches
-- Does not yet include I/O
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial release - no I/O
--
--
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity ibm2030 is
Port ( -- Physical I/O on Digilent S3 Board
-- ssd : out std_logic_vector(7 downto 0); -- 7-segment segment cathodes (not used)
-- ssdan : out std_logic_vector(3 downto 0); -- 7-segment digit anodes (not used)
led : out std_logic_vector(7 downto 0); -- 8 LEDs
pb : in std_logic_vector(3 downto 0); -- 4 pushbuttons
sw : in std_logic_vector(7 downto 0); -- 8 slide switches
pa_io1,pa_io2,pa_io3,pa_io4 : in std_logic := '0'; -- 4 digital inputs
pa_io5,pa_io6,pa_io7,pa_io8,pa_io9,
pa_io10,pa_io11,pa_io12,pa_io13,pa_io14 : out std_logic; -- 10 digital switch scanning outputs
pa_io15,pa_io16,pa_io17,pa_io18,ma2_db0,ma2_db1,
ma2_db2,ma2_db3,ma2_db4,ma2_db5: in std_logic := '0'; -- 10 digital switch scan inputs
-- ma2_db6,ma2_db7,ma2_astb,ma2_dstb,ma2_write, ma2_wait, ma2_reset, ma2_int : in std_logic := '0'; -- 8 digital inputs (not used)
-- ps2_clk : inout std_logic; -- Keyboard/Mouse clock (not used)
-- ps2_data : inout std_logic; -- Keyboard/Mouse data (not used)
vga_r,vga_g,vga_b,vga_hs,vga_vs : out std_logic; -- VGA output RGB+Sync
clk : in std_logic);
end ibm2030;
architecture FMD of ibm2030 is
-- Indicator outputs from CPU
signal WX_IND : std_logic_vector(0 to 12);
signal W_IND_P : std_logic;
signal X_IND_P : std_logic;
signal IND_SALS : SALS_BUS;
signal IND_EX,IND_CY_MATCH,IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : STD_LOGIC;
signal IND_MSDR : STD_LOGIC_VECTOR(0 to 7);
signal IND_MSDR_P : STD_LOGIC;
signal IND_OPNL_IN : STD_LOGIC;
signal IND_ADDR_IN : STD_LOGIC;
signal IND_STATUS_IN : STD_LOGIC;
signal IND_SERV_IN : STD_LOGIC;
signal IND_SEL_OUT : STD_LOGIC;
signal IND_ADDR_OUT : STD_LOGIC;
signal IND_CMMD_OUT : STD_LOGIC;
signal IND_SERV_OUT : STD_LOGIC;
signal IND_SUPPR_OUT : STD_LOGIC;
signal IND_FO : STD_LOGIC_VECTOR(0 to 7);
signal IND_FO_P: STD_LOGIC;
signal IND_A : STD_LOGIC_VECTOR(0 to 8);
signal IND_B : STD_LOGIC_VECTOR(0 to 8);
signal IND_ALU : STD_LOGIC_VECTOR(0 to 8);
signal IND_M : STD_LOGIC_VECTOR(0 to 8);
signal IND_N : STD_LOGIC_VECTOR(0 to 8);
signal IND_MAIN_STG : STD_LOGIC;
signal IND_LOC_STG : STD_LOGIC;
signal IND_COMP_MODE : STD_LOGIC;
signal IND_CHK_A_REG : STD_LOGIC;
signal IND_CHK_B_REG : STD_LOGIC;
signal IND_CHK_STOR_ADDR : STD_LOGIC;
signal IND_CHK_CTRL_REG : STD_LOGIC;
signal IND_CHK_ROS_SALS : STD_LOGIC;
signal IND_CHK_ROS_ADDR : STD_LOGIC;
signal IND_CHK_STOR_DATA : STD_LOGIC;
signal IND_CHK_ALU : STD_LOGIC;
signal IND_SYST : STD_LOGIC;
signal IND_MAN : STD_LOGIC;
signal IND_WAIT : STD_LOGIC;
signal IND_TEST : STD_LOGIC;
signal IND_LOAD : STD_LOGIC;
-- Switch inputs to CPU
signal SW_START,SW_LOAD,SW_SET_IC,SW_STOP,SW_POWER_OFF : STD_LOGIC;
signal SW_INH_CF_STOP,SW_PROC,SW_SCAN : STD_LOGIC;
signal SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : STD_LOGIC;
signal SW_LAMP_TEST,SW_DSPLY,SW_STORE,SW_SYS_RST : STD_LOGIC;
signal SW_CHK_RST,SW_ROAR_RST,SW_CHK_RESTART,SW_DIAGNOSTIC : STD_LOGIC;
signal SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE,SW_ROAR_RESTT_STOR_BYPASS : STD_LOGIC;
signal SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,SW_ROAR_STOP : STD_LOGIC;
signal SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : STD_LOGIC;
signal SW_INTRP_TIMER, SW_CONS_INTRP : STD_LOGIC;
signal SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : STD_LOGIC_VECTOR(0 to 3);
signal SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : STD_LOGIC;
signal E_SW : E_SW_BUS_Type;
-- Misc stuff
signal SwSlow : STD_LOGIC := '0'; -- Set to '1' to slow clock down to 1Hz, not used
signal N60_CY_TIMER_PULSE : STD_LOGIC; -- Used for the Interval Timer
signal DEBUG : STD_LOGIC := '0'; -- Spare variable for debug purposes
begin
cpu : entity cpu port map (
WX_IND => WX_IND,
W_IND_P => W_IND_P,
X_IND_P => X_IND_P,
IND_SALS => IND_SALS,
IND_EX => IND_EX,
IND_CY_MATCH => IND_CY_MATCH,
IND_ALLOW_WR => IND_ALLOW_WR,
IND_1050_INTRV => IND_1050_INTRV,
IND_1050_REQ => IND_1050_REQ,
IND_MPX => IND_MPX,
IND_SEL_CHNL => IND_SEL_CHNL,
IND_MSDR => IND_MSDR,
IND_MSDR_P => IND_MSDR_P,
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
IND_CHK_A_REG => IND_CHK_A_REG,
IND_CHK_B_REG => IND_CHK_B_REG,
IND_CHK_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_CHK_CTRL_REG => IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS => IND_CHK_ROS_SALS,
IND_CHK_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_CHK_STOR_DATA => IND_CHK_STOR_DATA,
IND_CHK_ALU => IND_CHK_ALU,
IND_LOAD => IND_LOAD,
IND_WAIT => IND_WAIT,
IND_TEST => IND_TEST,
IND_MAN => IND_MAN,
IND_SYST => IND_SYST,
SW_START => SW_START,
SW_LOAD => SW_LOAD,
SW_SET_IC => SW_SET_IC,
SW_STOP => SW_STOP,
SW_POWER_OFF => SW_POWER_OFF,
SW_INH_CF_STOP => SW_INH_CF_STOP,
SW_PROC => SW_PROC,
SW_SCAN => SW_SCAN,
SW_SINGLE_CYCLE => SW_SINGLE_CYCLE,
SW_INSTRUCTION_STEP => SW_INSTRUCTION_STEP,
SW_RATE_SW_PROCESS => SW_RATE_SW_PROCESS,
SW_LAMP_TEST => SW_LAMP_TEST,
SW_DSPLY => SW_DSPLY,
SW_STORE => SW_STORE,
SW_SYS_RST => SW_SYS_RST,
SW_CHK_RST => SW_CHK_RST,
SW_ROAR_RST => SW_ROAR_RST,
SW_CHK_RESTART => SW_CHK_RESTART,
SW_DIAGNOSTIC => SW_DIAGNOSTIC,
SW_CHK_STOP => SW_CHK_STOP,
SW_CHK_SW_PROCESS => SW_CHK_SW_PROCESS,
SW_CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
SW_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SW_ROAR_RESTT => SW_ROAR_RESTT,
SW_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
SW_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
SW_ROAR_STOP => SW_ROAR_STOP,
SW_ROAR_SYNC => SW_ROAR_SYNC,
SW_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
SW_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
SW_SAR_STOP => SW_SAR_STOP,
SW_SAR_RESTART => SW_SAR_RESTART,
SW_INTRP_TIMER => SW_INTRP_TIMER,
SW_CONS_INTRP => SW_CONS_INTRP,
SW_A => SW_A,
SW_B => SW_B,
SW_C => SW_C,
SW_D => SW_D,
SW_F => SW_F,
SW_G => SW_G,
SW_H => SW_H,
SW_J => SW_J,
SW_AP => SW_AP,
SW_BP => SW_BP,
SW_CP => SW_CP,
SW_DP => SW_DP,
SW_FP => SW_FP,
SW_GP => SW_GP,
SW_HP => SW_HP,
SW_JP => SW_JP,
E_SW => E_SW,
-- Multiplexor interface not connected to anything yet
MPX_BUS_O => open,
MPX_BUS_I => (others=>'0'),
MPX_TAGS_O => open,
MPX_TAGS_I => (others=>'0'),
DEBUG => DEBUG, -- Used to pass debug signals up to the top level for output
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE, -- Actually 50Hz
SwSlow => SwSlow,
clk => clk -- 50Mhz clock
);
frontPanel : entity vga_panel port map (
Clock50 => clk,
Red => vga_r, Green => vga_g, Blue => vga_b,
HS => vga_hs, VS => vga_vs,
Indicators( 0) => '0', -- Constant
Indicators( 1) => IND_SALS.SALS_PN,
Indicators( 2 to 7) => IND_SALS.SALS_CN,
Indicators( 8) => IND_SALS.SALS_PA,
Indicators( 9) => '0', -- LP
Indicators( 10) => W_IND_P,
Indicators( 11 to 15) => WX_IND(0 to 4),
Indicators( 16) => X_IND_P,
Indicators( 17 to 24) => WX_IND(5 to 12),
Indicators( 25) => IND_SALS.SALS_PS,
Indicators( 26 to 29) => IND_SALS.SALS_CH,
Indicators( 30 to 33) => IND_SALS.SALS_CL,
Indicators( 34) => IND_SALS.SALS_AA,
Indicators( 35 to 38) => IND_SALS.SALS_CA,
Indicators( 39 to 40) => IND_SALS.SALS_CB,
Indicators( 41 to 43) => IND_SALS.SALS_CM,
Indicators( 44 to 45) => IND_SALS.SALS_CU,
Indicators( 46) => IND_SALS.SALS_AK,
Indicators( 47) => IND_SALS.SALS_PK,
Indicators( 48 to 51) => IND_SALS.SALS_CK,
Indicators( 52) => IND_SALS.SALS_PC,
Indicators( 53 to 56) => IND_SALS.SALS_CD,
Indicators( 57 to 59) => IND_SALS.SALS_CF,
Indicators( 60 to 61) => IND_SALS.SALS_CG,
Indicators( 62 to 63) => IND_SALS.SALS_CV,
Indicators( 64 to 66) => IND_SALS.SALS_CC,
Indicators( 67) => IND_SALS.SALS_SA,
Indicators( 68 to 71) => IND_SALS.SALS_CS,
-- Skip 18 + 9 + 9 + 5 + 9 + 6 = 56 for SX1 (72 to 127)
Indicators( 72 to 127) => "00000000000000000000000000000000000000000000000000000000",
-- If we had SX2 there would be another 56 here
-- MPX
Indicators( 128) => IND_OPNL_IN,
Indicators( 129) => IND_ADDR_IN,
Indicators( 130) => IND_STATUS_IN,
Indicators( 131) => IND_SERV_IN,
Indicators( 132) => IND_SEL_OUT,
Indicators( 133) => IND_ADDR_OUT,
Indicators( 134) => IND_CMMD_OUT,
Indicators( 135) => IND_SERV_OUT,
Indicators( 136) => IND_SUPPR_OUT,
Indicators( 137) => IND_FO_P,
Indicators(138 to 145) => IND_FO,
-- MSAR
Indicators( 146) => IND_MAIN_STG,
Indicators( 147) => IND_M(8),
Indicators(148 to 155) => IND_M(0 to 7),
Indicators( 156) => IND_N(8),
Indicators(157 to 164) => IND_N(0 to 7),
Indicators( 165) => IND_LOC_STG,
-- MSDR
Indicators( 166) => IND_MSDR_P,
Indicators(167 to 174) => IND_MSDR,
-- ALU
Indicators( 175) => IND_ALU(8),
Indicators(176 to 183) => IND_ALU(0 to 7),
Indicators( 184) => IND_EX,
Indicators( 185) => IND_CY_MATCH,
Indicators( 186) => IND_ALLOW_WR,
Indicators( 187) => IND_CHK_STOR_ADDR,
Indicators( 188) => IND_CHK_STOR_DATA,
Indicators( 189) => IND_1050_INTRV,
Indicators( 190) => IND_1050_REQ,
Indicators( 191) => IND_CHK_B_REG,
Indicators( 192) => IND_CHK_A_REG,
Indicators( 193) => IND_CHK_ALU,
-- A,B
Indicators( 194) => IND_A(8),
Indicators(195 to 202) => IND_A(0 to 7),
Indicators( 203) => IND_B(8),
Indicators(204 to 211) => IND_B(0 to 7),
Indicators( 212) => IND_MPX,
Indicators( 213) => IND_SEL_CHNL,
Indicators( 214) => IND_COMP_MODE,
Indicators( 215) => IND_CHK_ROS_ADDR,
Indicators( 216) => IND_CHK_ROS_SALS,
Indicators( 217) => IND_CHK_CTRL_REG,
-- The following indicators mimic the 8 Hex rotary switches to make it easier to set them
Indicators(218 to 221) => SW_A(0 to 3),
Indicators(222 to 225) => SW_B(0 to 3),
Indicators(226 to 229) => SW_C(0 to 3),
Indicators(230 to 233) => SW_D(0 to 3),
Indicators(234 to 237) => SW_F(0 to 3),
Indicators(238 to 241) => SW_G(0 to 3),
Indicators(242 to 245) => SW_H(0 to 3),
Indicators(246 to 249) => SW_J(0 to 3)
);
-- LEDs are set here
led(0) <= IND_LOAD;
led(1) <= IND_TEST;
led(2) <= IND_WAIT;
led(3) <= IND_MAN;
led(4) <= IND_SYST;
led(5) <= '0';
led(6) <= '0';
led(7) <= DEBUG;
frontPanel_switches: entity switches port map (
-- Hardware switch inputs and scan outputs
SwA_scan => pa_io5,
SwB_scan => pa_io6,
SwC_scan => pa_io7,
SwD_scan => pa_io8,
SwE_scan => pa_io9,
SwF_scan => pa_io10,
SwG_scan => pa_io11,
SwH_scan => pa_io12,
SwJ_scan => pa_io13,
SwAC_scan => pa_io14,
Hex_in(0) => pa_io1,
Hex_in(1) => pa_io2,
Hex_in(2) => pa_io3,
Hex_in(3) => pa_io4,
SW_E_INNER => pa_io15,
SW_E_OUTER => pa_io16,
RawSw_Proc_Inh_CF_Stop => pa_io17,
RawSw_Proc_Scan => pa_io18,
RawSw_Rate_Single_Cycle => ma2_db1,
RawSw_Rate_Instruction_Step => ma2_db0,
RawSw_Chk_Chk_Restart => ma2_db5,
RawSw_Chk_Diagnostic => ma2_db2,
RawSw_Chk_Stop => ma2_db4,
RawSw_Chk_Disable => ma2_db3,
sw => sw,
pb => pb,
-- Switches fed to CPU
SwA => SW_A, SwAP => SW_AP,
SwB => SW_B, SwBP => SW_BP,
SwC => SW_C, SwCP => SW_CP,
SwD => SW_D, SwDP => SW_DP,
SwE => E_SW,
SwF => SW_F, SwFP => SW_FP,
SwG => SW_G, SwGP => SW_GP,
SwH => SW_H, SwHP => SW_HP,
SwJ => SW_J, SwJP => SW_JP,
Sw_PowerOff => SW_POWER_OFF,
Sw_Interrupt => SW_CONS_INTRP,
Sw_Load => SW_LOAD,
Sw_SystemReset => SW_SYS_RST,
Sw_RoarReset => SW_ROAR_RST,
Sw_Start => SW_START,
Sw_SetIC => SW_SET_IC,
Sw_CheckReset => SW_CHK_RST,
Sw_Stop => SW_STOP,
Sw_IntTmr => SW_INTRP_TIMER,
Sw_Store => SW_STORE,
Sw_LampTest => SW_LAMP_TEST,
Sw_Display => SW_DSPLY,
Sw_Proc_Inh_CF_Stop => SW_INH_CF_STOP,
Sw_Proc_Proc => SW_PROC,
Sw_Proc_Scan => SW_SCAN,
Sw_Rate_Single_Cycle => SW_SINGLE_CYCLE,
Sw_Rate_Instruction_Step => SW_INSTRUCTION_STEP,
Sw_Rate_Process => SW_RATE_SW_PROCESS,
Sw_Chk_Chk_Restart => SW_CHK_RESTART,
Sw_Chk_Diagnostic => SW_DIAGNOSTIC,
Sw_Chk_Stop => SW_CHK_STOP,
Sw_Chk_Process => SW_CHK_SW_PROCESS,
Sw_Chk_Disable => SW_CHK_SW_DISABLE,
Sw_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
Sw_ROAR_RESTT => SW_ROAR_RESTT,
Sw_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
Sw_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
Sw_ROAR_STOP => SW_ROAR_STOP,
Sw_ROAR_SYNC => SW_ROAR_SYNC,
Sw_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
Sw_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
Sw_SAR_STOP => SW_SAR_STOP,
Sw_SAR_RESTART => SW_SAR_RESTART,
-- Clocks etc.
clk => clk, -- 50MHz clock
Timer => N60_CY_TIMER_PULSE -- Output from Switches is actually 50Hz
);
end FMD;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: switches.vhd
-- Creation Date: 21:49:37 20/01/2010
-- Description:
-- 360/30 Front Panel switch handling
-- Some switches are provided by the pushbuttons and sliders on the S3BOARD
-- Rotary switches are connected externally with a mixture of scanning and
-- discrete inputs. In all cases the "Process" position is not connected so
-- omitting the switches entirely allows the system to run normally.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.EvenParity;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity switches is
Port ( -- Raw switch inputs: (These can be modified to suit the board being used)
SwA_scan : out STD_LOGIC;
SwB_scan : out STD_LOGIC;
SwC_scan : out STD_LOGIC;
SwD_scan : out STD_LOGIC;
SwE_scan : out STD_LOGIC;
SwF_scan : out STD_LOGIC;
SwG_scan : out STD_LOGIC;
SwH_scan : out STD_LOGIC;
SwJ_scan : out STD_LOGIC;
SwAC_scan : out STD_LOGIC; -- Address Compare
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
SW_E_Inner, SW_E_Outer : in STD_LOGIC;
RawSw_Proc_Inh_CF_Stop, RawSw_Proc_Scan : in STD_LOGIC; -- ROS Control
RawSw_Rate_Single_Cycle, RawSw_Rate_Instruction_Step : in STD_LOGIC; -- Rate
RawSw_Chk_Chk_Restart, RawSw_Chk_Diagnostic, RawSw_Chk_Stop, RawSw_Chk_Disable : in STD_LOGIC; -- Check Control
pb : in std_logic_vector(3 downto 0); -- On-board pushbuttons
sw : in std_logic_vector(7 downto 0); -- On-board slide switches
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
-- USE_MAN_DECODER_PWR : in STD_LOGIC;
-- Conditioned switch outputs:
SwA,SwB,SwC,SwD,SwF,SwG,SwH,SwJ : out STD_LOGIC_VECTOR(3 downto 0);
SwAP,SwBP,SwCP,SwDP,SwFP,SwGP,SwHP,SwJP : out STD_LOGIC;
SwE : out E_SW_BUS_Type;
Sw_PowerOff, Sw_Interrupt, Sw_Load : out STD_LOGIC; -- Right-hand pushbuttons
Sw_SystemReset, Sw_RoarReset, Sw_Start, Sw_SetIC, Sw_CheckReset,
Sw_Stop, Sw_IntTmr, Sw_Store, Sw_LampTest, Sw_Display : out STD_LOGIC; -- Left-hand pushbuttons
Sw_Proc_Inh_CF_Stop, Sw_Proc_Proc, Sw_Proc_Scan : out STD_LOGIC; -- ROS Control
Sw_Rate_Single_Cycle, Sw_Rate_Instruction_Step, Sw_Rate_Process : out STD_LOGIC; -- Rate
Sw_Chk_Chk_Restart, Sw_Chk_Diagnostic, Sw_Chk_Stop, Sw_Chk_Process, Sw_Chk_Disable : out STD_LOGIC; -- Check Control
Sw_ROAR_RESTT,Sw_ROAR_RESTT_WITHOUT_RST,Sw_EARLY_ROAR_STOP,Sw_ROAR_STOP, Sw_ROAR_RESTT_STOR_BYPASS,
Sw_ROAR_SYNC,Sw_ADDR_COMP_PROC,Sw_SAR_DLYD_STOP,Sw_SAR_STOP,Sw_SAR_RESTART : out STD_LOGIC; -- Address Compare
-- 50Hz Timer signal
Timer : out STD_LOGIC
);
end switches;
architecture Behavioral of switches is
subtype debounce is std_logic_vector(0 to 3);
signal scan : std_logic_vector(3 downto 0) := "0000";
signal counter : std_logic_vector(14 downto 0) := (others=>'0');
signal timerCounter : std_logic_vector(5 downto 0) := (others=>'0');
signal SwE_raw : std_logic_vector(3 downto 0) := "0000";
signal SwAC : std_logic_vector(3 downto 0) := "0000"; -- Address Compare switch
signal Parity_in : std_logic;
signal RawSw_PowerOff, RawSw_Interrupt, RawSw_Load, RawSw_SystemReset, RawSw_RoarReset, RawSw_Start,
RawSw_SetIC, RawSw_CheckReset, RawSw_Stop, RawSw_IntTmr, RawSw_Store, RawSw_LampTest,
RawSw_Display : STD_LOGIC; -- Right-hand pushbuttons
signal debouncePowerOff, debounceInterrupt, debounceLoad,
debounceSystemReset, debounceRoarReset, debounceStart, debounceSetIC, debounceCheckReset,
debounceStop, debounceIntTmr, debounceStore, debounceLampTest, debounceDisplay : debounce;
signal timerOut : std_logic := '0';
constant divider : std_logic_vector(14 downto 0) := "100111000100000"; -- 20,000 gives 2.5kHz
constant sample : std_logic_vector(14 downto 0) := "100111000011110"; -- 19,999
constant divider100 : std_logic_vector(4 downto 0) := "11001"; --- 25 converts 2.5kHz to 100Hz for timer
begin
Parity_in <= EvenParity(Hex_in);
scan_counter: process(clk)
begin
if (rising_edge(clk)) then
if counter=sample then
if scan="0000" then SwA <= Hex_in; SwAP <= Parity_in; end if;
if scan="0001" then SwB <= Hex_in; SwBP <= Parity_in; end if;
if scan="0010" then SwC <= Hex_in; SwCP <= Parity_in; end if;
if scan="0011" then SwD <= Hex_in; SwDP <= Parity_in; end if;
if scan="0100" then SwE_raw <= Hex_in; end if;
if scan="0101" then SwF <= Hex_in; SwFP <= Parity_in; end if;
if scan="0110" then SwG <= Hex_in; SwGP <= Parity_in; end if;
if scan="0111" then SwH <= Hex_in; SwHP <= Parity_in; end if;
if scan="1000" then SwJ <= Hex_in; SwJP <= Parity_in; end if;
if scan="1001" then SwAC <= Hex_in; end if;
end if;
if counter=divider then
counter<=(others=>'0');
if scan="1001" then
scan <= "0000";
else
scan <= scan + 1;
end if;
debouncePowerOff <= debouncePowerOff(1 to 3) & rawSw_PowerOff;
debounceInterrupt <= debounceInterrupt(1 to 3) & rawSw_Interrupt;
debounceLoad <= debounceLoad(1 to 3) & rawSw_Load;
debounceSystemReset <= debounceSystemReset(1 to 3) & rawSw_SystemReset;
debounceRoarReset <= debounceRoarReset(1 to 3) & rawSw_RoarReset;
debounceStart <= debounceStart(1 to 3) & rawSw_Start;
debounceSetIC <= debounceSetIC(1 to 3) & rawSw_SetIC;
debounceCheckReset <= debounceCheckReset(1 to 3) & rawSw_CheckReset;
debounceStop <= debounceStop(1 to 3) & rawSw_Stop;
debounceIntTmr <= debounceIntTmr(1 to 3) & rawSw_IntTmr;
debounceStore <= debounceStore(1 to 3) & rawSw_Store;
debounceLampTest <= debounceLampTest(1 to 3) & rawSw_LampTest;
debounceDisplay <= debounceDisplay(1 to 3) & rawSw_Display;
if (debouncePowerOff = "0000") then Sw_PowerOff <= '0'; else if (debouncePowerOff = "1111") then Sw_PowerOff <= '1'; end if; end if;
if (debounceInterrupt = "0000") then Sw_Interrupt <= '0'; else if (debounceInterrupt = "1111") then Sw_Interrupt <= '1'; end if; end if;
if (debounceLoad = "0000") then Sw_Load <= '0'; else if (debounceLoad = "1111") then Sw_Load <= '1'; end if; end if;
if (debounceSystemReset = "0000") then Sw_SystemReset <= '0'; else if (debounceSystemReset = "1111") then Sw_SystemReset <= '1'; end if; end if;
if (debounceRoarReset = "0000") then Sw_RoarReset <= '0'; else if (debounceRoarReset = "1111") then Sw_RoarReset <= '1'; end if; end if;
if (debounceStart = "0000") then Sw_Start <= '0'; else if (debounceStart = "1111") then Sw_Start <= '1'; end if; end if;
if (debounceSetIC = "0000") then Sw_SetIC <= '0'; else if (debounceSetIC = "1111") then Sw_SetIC <= '1'; end if; end if;
if (debounceCheckReset = "0000") then Sw_CheckReset <= '0'; else if (debounceCheckReset = "1111") then Sw_CheckReset <= '1'; end if; end if;
if (debounceStop = "0000") then Sw_Stop <= '0'; else if (debounceStop = "1111") then Sw_Stop <= '1'; end if; end if;
if (debounceIntTmr = "0000") then Sw_IntTmr <= '0'; else if (debounceIntTmr = "1111") then Sw_IntTmr <= '1'; end if; end if;
if (debounceStore = "0000") then Sw_Store <= '0'; else if (debounceStore = "1111") then Sw_Store <= '1'; end if; end if;
if (debounceLampTest = "0000") then Sw_LampTest <= '0'; else if (debounceLampTest = "1111") then Sw_LampTest <= '1'; end if; end if;
if (debounceDisplay = "0000") then Sw_Display <= '0'; else if (debounceDisplay = "1111") then Sw_Display <= '1'; end if; end if;
if (timerCounter = divider100) then
timerOut <= not timerOut;
Timer <= timerOut;
timerCounter <= (others=>'0');
else
timerCounter <= timerCounter + 1;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
SwA_scan <= '1' when scan="0000" else '0';
SwB_scan <= '1' when scan="0001" else '0';
SwC_scan <= '1' when scan="0010" else '0';
SwD_scan <= '1' when scan="0011" else '0';
SwE_scan <= '1' when scan="0100" else '0';
SwF_scan <= '1' when scan="0101" else '0';
SwG_scan <= '1' when scan="0110" else '0';
SwH_scan <= '1' when scan="0111" else '0';
SwJ_scan <= '1' when scan="1000" else '0';
SwAC_scan <= '1' when scan="1001" else '0';
-- Inner ring
SwE.I_SEL <= '1' when SwE_raw="0000" and SW_E_INNER='1' else '0';
SwE.J_SEL <= '1' when SwE_raw="0001" and SW_E_INNER='1' else '0';
SwE.U_SEL <= '1' when SwE_raw="0010" and SW_E_INNER='1' else '0';
SwE.V_SEL <= '1' when SwE_raw="0011" and SW_E_INNER='1' else '0';
SwE.L_SEL <= '1' when SwE_raw="0100" and SW_E_INNER='1' else '0';
SwE.T_SEL <= '1' when SwE_raw="0101" and SW_E_INNER='1' else '0';
SwE.D_SEL <= '1' when SwE_raw="0110" and SW_E_INNER='1' else '0';
SwE.R_SEL <= '1' when SwE_raw="0111" and SW_E_INNER='1' else '0';
SwE.S_SEL <= '1' when SwE_raw="1000" and SW_E_INNER='1' else '0';
SwE.G_SEL <= '1' when SwE_raw="1001" and SW_E_INNER='1' else '0';
SwE.H_SEL <= '1' when SwE_raw="1010" and SW_E_INNER='1' else '0';
SwE.FI_SEL <= '1' when SwE_raw="1011" and SW_E_INNER='1' else '0';
SwE.FT_SEL <= '1' when SwE_raw="1100" and SW_E_INNER='1' else '0';
-- Mid ring
SwE.MS_SEL <= '1' when SwE_raw="0000" and SW_E_INNER='0' and SW_E_OUTER='0' else '0';
SwE.LS_SEL <= '1' when SwE_raw="0001" and SW_E_INNER='0' and SW_E_OUTER='0' else '0';
-- Outer ring
SwE.E_SEL_SW_GS <= '1' when SwE_raw="0000" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_GT <= '1' when SwE_raw="0001" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_GUV_GCD <= '1' when SwE_raw="0010" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_HS <= '1' when SwE_raw="0011" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_HT <= '1' when SwE_raw="0100" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_HUV_HCD <= '1' when SwE_raw="0101" and SW_E_OUTER='1' else '0';
SwE.Q_SEL <= '1' when SwE_raw="0110" and SW_E_OUTER='1' else '0';
SwE.C_SEL <= '1' when SwE_raw="0111" and SW_E_OUTER='1' else '0';
SwE.F_SEL <= '1' when SwE_raw="1000" and SW_E_OUTER='1' else '0';
SwE.TT_SEL <= '1' when SwE_raw="1001" and SW_E_OUTER='1' else '0';
SwE.TI_SEL <= '1' when SwE_raw="1010" and SW_E_OUTER='1' else '0';
SwE.JI_SEL <= '1' when SwE_raw="1011" and SW_E_OUTER='1' else '0';
-- SwE.IJ_SEL <= '1' when (SwE_raw="0000" or SwE_raw="0001") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- SwE.UV_SEL <= '1' when (SwE_raw="0010" or SwE_raw="0011") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- Address Compare
Sw_ADDR_COMP_PROC <= '1' when SwAC="0000" else '0';
Sw_SAR_DLYD_STOP <= '1' when SwAC="0001" else '0';
Sw_SAR_STOP <= '1' when SwAC="0010" else '0';
Sw_SAR_RESTART <= '1' when SwAC="0011" else '0';
Sw_ROAR_RESTT_STOR_BYPASS <= '1' when SwAC="0100" else '0';
Sw_ROAR_RESTT <= '1' when SwAC="0101" else '0';
Sw_ROAR_RESTT_WITHOUT_RST <= '1' when SwAC="0110" else '0';
Sw_EARLY_ROAR_STOP <= '1' when SwAC="0111" else '0';
Sw_ROAR_STOP <= '1' when SwAC="1000" else '0';
Sw_ROAR_SYNC <= '1' when SwAC="1001" else '0';
-- ROS Control
Sw_Proc_Inh_CF_Stop <= '1' when RawSw_Proc_Inh_CF_Stop='1' else '0';
Sw_Proc_Proc <= '1' when RawSw_Proc_Inh_CF_Stop='0' and RawSw_Proc_Scan='0' else '0';
Sw_Proc_Scan <= '1' when RawSw_Proc_Scan='1' else '0';
-- Rate
Sw_Rate_Single_Cycle <= '1' when RawSw_Rate_Single_Cycle='1' else '0';
Sw_Rate_Process <= '1' when RawSw_Rate_Single_Cycle='0' and RawSw_Rate_Instruction_Step='0' else '0';
Sw_Rate_Instruction_Step <= '1' when RawSw_Rate_Instruction_Step='1' else '0';
-- Check Control
Sw_Chk_Chk_Restart <= '1' when RawSw_Chk_Chk_Restart='1' else '0';
Sw_Chk_Diagnostic <= '1' when RawSw_Chk_Diagnostic='1' else '0';
Sw_Chk_Stop <= '1' when RawSw_Chk_Stop='1' else '0';
Sw_Chk_Process <= '1' when RawSw_Chk_Chk_Restart='0' and RawSw_Chk_Diagnostic='0' and RawSw_Chk_Stop='0' and RawSw_Chk_Disable='0' else '0';
Sw_Chk_Disable <= '1' when RawSw_Chk_Disable='1' else '0';
-- Unimplemented switches
RawSw_PowerOff <= '0';
RawSw_IntTmr <= '0';
-- Pushbuttons
RawSw_SystemReset <= pb(0);
RawSw_Start <= pb(1);
RawSw_Load <= pb(2);
RawSw_Stop <= pb(3);
-- Slide switches
RawSw_Display <= sw(1);
RawSw_Store <= sw(2);
RawSw_Interrupt <= sw(3);
RawSw_RoarReset <= sw(4);
RawSw_SetIC <= sw(5);
RawSw_CheckReset <= sw(6);
RawSw_LampTest <= sw(7);
end behavioral;