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263 lines
8.1 KiB
VHDL
263 lines
8.1 KiB
VHDL
--*****************************************************************************************
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--**
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--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
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--** provided to you "as is". Xilinx and its licensors make and you
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--** receive no warranties or conditions, express, implied, statutory
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--** or otherwise, and Xilinx specifically disclaims any implied
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--** warranties of merchantability, non-infringement, or fitness for a
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--** particular purpose. Xilinx does not warrant that the functions
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--** contained in these designs will meet your requirements, or that the
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--** operation of these designs will be uninterrupted or error free, or
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--** that defects in the Designs will be corrected. Furthermore, Xilinx
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--** does not warrant or make any representations regarding use or the
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--** results of the use of the designs in terms of correctness, accuracy,
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--** reliability, or otherwise.
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--**
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--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
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--** liable for any loss of data, lost profits, cost or procurement of
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--** substitute goods or services, or for any special, incidental,
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--** consequential, or indirect damages arising from the use or operation
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--** of the designs or accompanying documentation, however caused and on
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--** any theory of liability. This limitation will apply even if Xilinx
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--** has been advised of the possibility of such damage. This limitation
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--** shall apply not-withstanding the failure of the essential purpose of
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--** any limited remedies herein.
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--**
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--*****************************************************************************************
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-- MODULE : PROM_reader_serial.vhd
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-- AUTHOR : Stephan Neuhold
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-- VERSION : v1.00
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--
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--
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-- REVISION HISTORY:
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-- -----------------
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-- No revisions
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--
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--
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-- FUNCTION DESCRIPTION:
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-- ---------------------
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-- This module provides the control state machine
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-- for reading data from the PROM. This includes
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-- searching for synchronisation patterns, retrieving
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-- data, resetting the PROMs address counter.
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--***************************
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--* Library declarations
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--***************************
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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--***********************
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--* Entity declaration
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--***********************
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entity PROM_reader_serial is
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generic(
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length : integer := 5;
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frequency : integer := 50
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);
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port(
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clock : in std_logic;
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reset : in std_logic; --active high
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read : in std_logic; --active low
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next_sync : in std_logic; --active low
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din : in std_logic;
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sync_pattern : in std_logic_vector((2**length) - 1 downto 0);
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cclk : out std_logic;
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sync : out std_logic; --active low
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data_ready : out std_logic; --active low
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reset_prom : out std_logic; --active high
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dout : out std_logic_vector(7 downto 0)
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);
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end PROM_reader_serial;
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architecture Behavioral of PROM_reader_serial is
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component clock_management
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generic(
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length : integer := 5;
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frequency : integer := 50
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);
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port(
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clock : in std_logic;
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enable : in std_logic;
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read_enable : out std_logic;
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cclk : out std_logic
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);
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end component;
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component shift_compare_serial
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generic(
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length : integer := 5
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);
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port(
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clock : in std_logic;
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reset : in std_logic;
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enable : in std_logic;
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din : in std_logic;
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b : in std_logic_vector((2**length) - 1 downto 0);
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eq : out std_logic;
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din_shifted : out std_logic_vector(7 downto 0)
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);
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end component;
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type state_type is (Look4Sync, Wait4Active, GetData, PresentData);
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signal current_state : state_type;
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signal count : std_logic_vector(length downto 0);
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signal din_read_enable : std_logic;
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signal sync_found : std_logic;
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signal data : std_logic_vector(7 downto 0);
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signal sync_int : std_logic;
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signal cclk_on : std_logic;
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signal reset_n : std_logic;
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begin
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--Clock generation and clock enable generation
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Clock_Manager: clock_management
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generic map(
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length => length,
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frequency => frequency
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)
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port map(
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clock => clock,
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enable => cclk_on,
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read_enable => din_read_enable,
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cclk => cclk
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);
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--Shift and compare operation
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Shift_And_Compare: shift_compare_serial
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generic map(
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length => length
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)
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port map(
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clock => clock,
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reset => reset,
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enable => din_read_enable,
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din => din,
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b => sync_pattern,
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eq => sync_found,
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din_shifted => data
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);
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--State machine
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process (clock, reset, current_state, sync_int, read, count,
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data, sync_found)
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begin
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if (reset = '1') then
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current_state <= Look4Sync; --this can be changed to Wait4Active so that the FPGA doesnt go looking for data immediately after config
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dout <= (others => '0');
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count <= (others => '0');
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sync_int <= '0';
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data_ready <= '1';
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reset_PROM <= '0';
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cclk_on <= '1';
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elsif rising_edge(clock) then
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case current_state is
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--*************************************************************
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--* This state clocks in one bit of data at a time from the
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--* PROM. With every new bit clocked in a comparison is done
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--* to check whether it matches the synchronisation pattern.
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--* If the pattern is found then a further bits are read
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--* from the PROM to provide the first byte of data appearing
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--* after the synchronisation pattern.
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--*************************************************************
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when Look4Sync =>
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count <= (others => '0');
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data_ready <= '1';
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sync_int <= '0';
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reset_PROM <= '1';
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if (sync_found = '1') then
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current_state <= Wait4Active;
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sync_int <= '1';
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cclk_on <= '0';
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end if;
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--*********************************************************
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--* At this point the state machine waits for user input.
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--* If the user pulses the "read" signal then 8 bits of
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--* are retrieved from the PROM. If the user wants to
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--* look for another synchronisation pattern and pulses
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--* the "next_sync" signal, then the state machine goes
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--* into the "Look4Sync" state.
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--*********************************************************
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when Wait4Active =>
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count <= (others => '0');
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data_ready <= '1';
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if (read = '0' or sync_int = '1') then
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current_state <= GetData;
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cclk_on <= '1';
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end if;
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if (next_sync = '0') then
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current_state <= Look4Sync;
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cclk_on <= '1';
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end if;
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--*********************************************************
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--* This state gets the data from the PROM. If the
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--* synchronisation pattern has just been found then
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--* enough data is retrieved to present the first
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--* 8 bits after the pattern. This is dependant on the
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--* synchronisation pattern length.
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--* If the synchronisation pattern has already been found
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--* previously then only the next 8 bits of data are
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--* retrieved.
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--*********************************************************
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when GetData =>
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if (din_read_enable = '1') then
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count <= count + 1;
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if (sync_int = '1') then
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if (count = (2**length) - 1) then
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current_state <= PresentData;
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sync_int <= '0';
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cclk_on <= '0';
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end if;
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else
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if (count = 7) then
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current_state <= PresentData;
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sync_int <= '0';
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cclk_on <= '0';
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end if;
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end if;
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end if;
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--*******************************************************
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--* This state tells the user that 8 bits of data have
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--* been retrieved and is presented on the "dout" port.
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--* The "Wait4Active" state is then entered to wait for
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--* another user request.
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--*******************************************************
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when PresentData =>
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dout <= data;
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data_ready <= '0';
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current_state <= Wait4Active;
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when others =>
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null;
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end case;
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end if;
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sync <= not sync_found;
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end process;
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end Behavioral;
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