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195 lines
9.6 KiB
VHDL
195 lines
9.6 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-05C.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- I,J,U,V,T,G,L & D registers and A,B bus assembly
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY RegsABAssm IS
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port
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(
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-- Inputs
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-- A_BUS_IN : INOUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
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SALS : IN SALS_BUS;
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MACH_RST_SET_LCH : IN STD_LOGIC; -- 03B
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SEL_SHARE_CYCLE : IN STD_LOGIC; -- ?
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USE_MAN_DECODER : IN STD_LOGIC; -- 03D
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MAN_STOR_PWR : IN STD_LOGIC; -- 03D
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USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
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FG_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 04C
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FG_SW_P : IN STD_LOGIC;
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HJ_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 8 is P
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HJ_SW_P : IN STD_LOGIC;
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USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A
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USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
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MPX_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08C 8 is P
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FT0,FT3,FT5,FT6 : IN STD_LOGIC; -- 08D
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FT1 : IN STD_LOGIC; -- 07C
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FT2,FT7 : IN STD_LOGIC; -- 08C
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FT4 : IN STD_LOGIC; -- 03C
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E_SW_SEL_BUS : IN E_SW_BUS_TYPE; -- 04C
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CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3);
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CD_REG_2 : IN STD_LOGIC; -- 04C Unused
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MACH_RST_2A_B : IN STD_LOGIC; -- 06B
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Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
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R_REG : IN STD_LOGIC_VECTOR(0 to 8); -- 06C 8 is P
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-- Outputs
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USE_CPU_DECODER : OUT STD_LOGIC; -- 05B,04D
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GATED_CA_BITS : OUT STD_LOGIC_VECTOR(0 to 3); -- 07C,10C
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GT_J_TO_A,GT_D_TO_A : OUT STD_LOGIC; -- 03C
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I,J,U,V,T,G,L : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
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A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
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B_BUS_OUT : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
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-- Clocks
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T4 : IN STD_LOGIC
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);
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END RegsABAssm;
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ARCHITECTURE FMD OF RegsABAssm IS
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alias CA : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CA;
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alias CK : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CK;
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alias CB : STD_LOGIC_VECTOR(0 to 1) is SALS.SALS_CB;
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alias AK_SAL_BIT : STD_LOGIC is SALS.SALS_AK;
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signal GT_HJ_SWS_TO_B_BUS : STD_LOGIC;
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signal GT_R_TO_B,GT_L_TO_B,GT_D_TO_B,GT_CK_TO_B : STD_LOGIC;
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signal GT_FG_TO_A, GT_MPX_TAGS_TO_A, GT_MPX_BUS_TO_A,GT_I_TO_A,GT_U_TO_A, GT_V_TO_A,GT_T_TO_A,GT_G_TO_A,GT_L_TO_A,GT_R_TO_A : STD_LOGIC;
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signal LCH_I,LCH_J,LCH_U,LCH_V,LCH_T,LCH_G,LCH_L,LCH_D : STD_LOGIC;
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signal sUSE_CPU_DECODER : STD_LOGIC;
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signal sGATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
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signal sGT_J_TO_A, sGT_D_TO_A : STD_LOGIC;
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signal sI,sJ,sU,sV,sT,sG,sL,sD : STD_LOGIC_VECTOR(0 to 8);
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BEGIN
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-- Fig 5-05C
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sUSE_CPU_DECODER <= not MACH_RST_SET_LCH and not SEL_SHARE_CYCLE and not USE_MAN_DECODER; -- AB3C5
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USE_CPU_DECODER <= sUSE_CPU_DECODER;
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sGATED_CA_BITS <= CA and (0 to 3 => sUSE_CPU_DECODER); -- AA2J6,AA2J2
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GATED_CA_BITS <= sGATED_CA_BITS;
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GT_HJ_SWS_TO_B_BUS <= (not CK(0) and CK(1) and not CK(2) and not CK(3) and AK_SAL_BIT) or (MAN_STOR_PWR and USE_MAN_DECODER_PWR); -- AB3H7
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GT_R_TO_B <= not CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
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GT_L_TO_B <= not CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
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GT_D_TO_B <= CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
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GT_CK_TO_B <= CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
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B_BUS_OUT <= ((0 to 8 => GT_R_TO_B) and R_REG) or -- AB1K5
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((0 to 8 => GT_L_TO_B) and sL) or -- AB1K5
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((0 to 8 => GT_D_TO_B) and sD) or -- AB1K5
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((0 to 8 => GT_CK_TO_B) and CK & CK & '1') or -- AB1L5
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((0 to 8 => GT_HJ_SWS_TO_B_BUS) and HJ_SWS & HJ_SW_P); -- AB1L5
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GT_FG_TO_A <= '1' when sGATED_CA_BITS="0001" and USE_ALT_CA_DECODER='1' else '0'; -- AB1F5
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GT_MPX_TAGS_TO_A <= '1' when (sGATED_CA_BITS="0000" and USE_BASIC_CA_DECODER='1' and sUSE_CPU_DECODER='1') or (E_SW_SEL_BUS.FT_SEL='1' and USE_MAN_DECODER_PWR='1') else '0'; -- AA2C6 ?? and sUSE_CPU_DECODER required to prevent FT (CA=0000) from being put on A bus when not wanted
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GT_MPX_BUS_TO_A <= '1' when (sGATED_CA_BITS="0110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.FI_SEL='1') else '0'; -- AB3C3
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GT_I_TO_A <= '1' when (sGATED_CA_BITS="1111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.I_SEL='1') else '0'; -- AB1F4
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sGT_J_TO_A <= '1' when (sGATED_CA_BITS="1110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.J_SEL='1') else '0'; -- AB1F4
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GT_J_TO_A <= sGT_J_TO_A;
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GT_U_TO_A <= '1' when (sGATED_CA_BITS="1101" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.U_SEL='1') else '0'; -- AB1F4
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GT_V_TO_A <= '1' when (sGATED_CA_BITS="1100" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.V_SEL='1') else '0'; -- AB1F4
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GT_T_TO_A <= '1' when (sGATED_CA_BITS="1011" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.T_SEL='1') else '0'; -- AB1F4
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GT_G_TO_A <= '1' when (sGATED_CA_BITS="1010" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.G_SEL='1') else '0'; -- AB1F4
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GT_L_TO_A <= '1' when (sGATED_CA_BITS="1001" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.L_SEL='1') else '0'; -- AB3C3
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sGT_D_TO_A <= '1' when (sGATED_CA_BITS="1000" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.D_SEL='1') else '0'; -- AB3C3
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GT_D_TO_A <= sGT_D_TO_A;
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GT_R_TO_A <= '1' when (sGATED_CA_BITS="0111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.R_SEL='1') else '0'; -- AB3C3
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A_BUS <= not(FG_SWS & FG_SW_P) when GT_FG_TO_A='1' else
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not(FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') when GT_MPX_TAGS_TO_A='1' else
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not MPX_BUS when GT_MPX_BUS_TO_A='1' else
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not sI when GT_I_TO_A='1' else
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not sJ when sGT_J_TO_A='1' else
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not sU when GT_U_TO_A='1' else
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not sV when GT_V_TO_A='1' else
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not sT when GT_T_TO_A='1' else
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not sG when GT_G_TO_A='1' else
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not sL when GT_L_TO_A='1' else
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not sD when sGT_D_TO_A='1' else
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not R_REG when GT_R_TO_A='1' else
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"111111111";
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-- A_BUS_OUT <= A_BUS_IN or
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-- ((0 to 8 => GT_FG_TO_A) and FG_SWS & FG_SW_P) or -- AB1D6
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-- ((0 to 8 => GT_MPX_TAGS_TO_A) and FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') or -- AB1D6
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-- ((0 to 8 => GT_MPX_BUS_TO_A) and MPX_BUS) or -- AB1D6
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-- ((0 to 8 => GT_I_TO_A) and sI) or -- AB1F4
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-- ((0 to 8 => sGT_J_TO_A) and sJ) or -- AB1F4
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-- ((0 to 8 => GT_U_TO_A) and sU) or -- AB1F4
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-- ((0 to 8 => GT_V_TO_A) and sV) or -- AB1C7
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-- ((0 to 8 => GT_T_TO_A) and sT) or -- AB1C7
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-- ((0 to 8 => GT_G_TO_A) and sG) or -- AB1C7
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-- ((0 to 8 => GT_L_TO_A) and sL) or -- AB3C3
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-- ((0 to 8 => sGT_D_TO_A) and sD) or -- AB3C3
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-- ((0 to 8 => GT_R_TO_A) and R_REG); -- AB3C3
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LCH_I <= '1' when (CD_CTRL_REG="1111" and T4='1') or (E_SW_SEL_BUS.I_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
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LCH_J <= '1' when (CD_CTRL_REG="1110" and T4='1') or (E_SW_SEL_BUS.J_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
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LCH_U <= '1' when (CD_CTRL_REG="1101" and T4='1') or (E_SW_SEL_BUS.U_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
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LCH_V <= '1' when (CD_CTRL_REG="1100" and T4='1') or (E_SW_SEL_BUS.V_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
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LCH_T <= '1' when (CD_CTRL_REG="1011" and T4='1') or (E_SW_SEL_BUS.T_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
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LCH_G <= '1' when (CD_CTRL_REG="1010" and T4='1') or (E_SW_SEL_BUS.G_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
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LCH_L <= '1' when (CD_CTRL_REG="1001" and T4='1') or (E_SW_SEL_BUS.L_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
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LCH_D <= '1' when (CD_CTRL_REG="1000" and T4='1') or (E_SW_SEL_BUS.D_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
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I_REG: PHV9 port map(Z_BUS,LCH_I,sI); -- AB1G3
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I <= sI;
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J_REG: PHV9 port map(Z_BUS,LCH_J,sJ); -- AB1G4
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J <= sJ;
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U_REG: PHV9 port map(Z_BUS,LCH_U,sU); -- AB1H3
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U <= sU;
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V_REG: PHV9 port map(Z_BUS,LCH_V,sV); -- AB1H4
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V <= sV;
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T_REG: PHV9 port map(Z_BUS,LCH_T,sT); -- AB1J4
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T <= sT;
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G_REG: PHV9 port map(Z_BUS,LCH_G,sG); -- AB1K4
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G <= sG;
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L_REG: PHV9 port map(Z_BUS,LCH_L,sL); -- AB1J2
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L <= sL;
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D_REG: PHV9 port map(Z_BUS,LCH_D,sD); -- AB1K3
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END FMD;
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