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97 lines
4.1 KiB
VHDL
97 lines
4.1 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-07C.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- A Register Assembly
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY ARegAssm IS
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port
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(
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-- Inputs
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USE_MANUAL_DECODER : IN STD_LOGIC; -- 03D
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USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
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USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02A
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E_SEL_SW_BUS : IN E_SW_BUS_Type; -- 04C
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GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
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CHK_SW_DISABLE : IN STD_LOGIC; -- 04A
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S : IN STD_LOGIC_VECTOR(0 to 7); -- 07B
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MC_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 7); -- 07A
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Q_REG : IN STD_LOGIC_VECTOR(0 to 8); -- 08B
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SEL_CHNL_GJ_BUS : IN STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- 11B
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GT_GJ_TO_A_REG : IN STD_LOGIC := '0'; -- 12C
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-- Outputs
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-- GT_DDC_TO_A_BUS : OUT STD_LOGIC; -- 07A
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GT_Q_REG_TO_A_BUS : OUT STD_LOGIC; -- 07A
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A_BUS : INOUT STD_LOGIC_VECTOR(0 to 8)
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);
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END ARegAssm;
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ARCHITECTURE FMD OF ARegAssm IS
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signal GT_MC_REG_TO_A_BUS : STD_LOGIC;
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signal sGT_Q_REG_TO_A_BUS : STD_LOGIC;
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signal sGT_DDC_TO_A_BUS : STD_LOGIC;
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signal GT_S_REG_TO_A : STD_LOGIC;
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signal JI_REG : STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- BE3D5
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BEGIN
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-- Fig 5-07C
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GT_MC_REG_TO_A_BUS <= '1' when USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0010" else '0'; -- AB1F5
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sGT_Q_REG_TO_A_BUS <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.Q_SEL='1') or (USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0101") else '0'; -- AB3C7
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GT_Q_REG_TO_A_BUS <= sGT_Q_REG_TO_A_BUS;
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sGT_DDC_TO_A_BUS <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.JI_SEL='1') or (USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0110") else '0'; -- AB3C7
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-- GT_DDC_TO_A_BUS <= sGT_DDC_TO_A_BUS;
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GT_S_REG_TO_A <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.S_SEL='1') or (USE_BASIC_CA_DECO='1' and GTD_CA_BITS="0100") else '0'; -- AB3C3
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A_BUS <= not(S & '0') when GT_S_REG_TO_A='1' else
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not(MC_CTRL_REG & '0') when GT_MC_REG_TO_A_BUS='1' and CHK_SW_DISABLE='0' else -- ABJK6 AB3L6
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not JI_REG when sGT_DDC_TO_A_BUS='1' else
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not SEL_CHNL_GJ_BUS when GT_GJ_TO_A_REG='1' else
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not Q_REG when sGT_Q_REG_TO_A_BUS='1' else -- AC2D2
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"111111111";
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-- A_REG_BUS_2 <= ((S & '0') and (A_REG_BUS_2'range => GT_S_REG_TO_A)) or ((MC_CTRL_REG & '0') and (A_REG_BUS_2'range => (GT_MC_REG_TO_A_BUS and not CHK_SW_DISABLE))); -- ABJK6 AB3L6
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-- A_REG_BUS_3 <= (JI_REG and (A_REG_BUS_3'range => sGT_DDC_TO_A_BUS)) or (SEL_CHNL_GJ_BUS and (A_REG_BUS_3'range => GT_GJ_TO_A_REG)) or (Q_REG and (A_REG_BUS_3'range => GT_Q_REG_TO_A_BUS)); -- AC2D2
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END FMD;
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