ibm2030.IBM2030/clock_management.vhd

--*****************************************************************************************
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--*****************************************************************************************
--	MODULE  : clock_management.vhd
--	AUTHOR  : Stephan Neuhold
--	VERSION : v1.00
--
--
--	REVISION HISTORY:
--	-----------------
--	No revisions
--
--
--	FUNCTION DESCRIPTION:
--	---------------------
--	This module generates an enable signal for
--	the shift register and comparator. It also
--	generates the clock signal that is connected
--	to the PROM.
--	The enable and clock signals are generated
--	based on the "frequency" generic entered for
--	the system clock.
--	The clock signal is only generated at the
--	appropriate times. All other states the clock
--	signal is kept at a logic high. The PROMs
--	address counter only increments on a rising
--	edge of this clock.


--***************************
--*	Library declarations
--***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;


--***********************
--*	Entity declaration
--***********************
entity clock_management is
	generic(
		length : integer := 5;
		frequency : integer := 50
		);
	port(
		clock : in std_logic;
		enable : in std_logic;
		read_enable : out std_logic;
		cclk : out std_logic
		);
end clock_management;


architecture Behavioral of clock_management is


signal cclk_int : std_logic := '1';
signal enable_cclk : std_logic;
signal SRL_length : std_logic_vector(3 downto 0);
signal temp : integer := (frequency / 20) - 1;


begin


--***************************************************
--*	The length of the SRL16 is based on the system
--*	clock frequency entered. This frequency is then
--*	"divided" down to approximately 10MHz.
--***************************************************
SRL_length <= conv_std_logic_vector(temp, length - 1);

Divider0: SRL16
	generic map(
		init => X"0001"
		)
	port map(
		clk => clock,
		d => enable_cclk,
		a0 => SRL_length(0),
		a1 => SRL_length(1),
		a2 => SRL_length(2),
		a3 => SRL_length(3),
		q => enable_cclk
		);


--***************************************************
--*	This process generates the enable signal for
--*	the shift register and the comparator. It also
--*	generates the clock signal used to increment
--*	the PROMs address counter.
--***************************************************
process(clock, enable_cclk, enable, cclk_int)
begin
	if rising_edge(clock) then
		if (enable = '1') then
			if (enable_cclk = '1') then
				cclk_int <= not cclk_int;
			end if;
			if (enable_cclk = '1' and cclk_int = '1') then
				read_enable <= '1';
			else
				read_enable <= '0';
			end if;
		else
			cclk_int <= '1';
		end if;
	end if;
	cclk <= cclk_int;
end process;


end Behavioral;