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141 lines
5.0 KiB
VHDL
141 lines
5.0 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: buses2030.vhd
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-- Creation Date:
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-- Description:
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-- This file defines various system-wide buses
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--
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-- Revision History:
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-- Revision 1.0 2010-07-09
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- This package defines various common buses and structures
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package Buses_package is
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-- SALS Bus is the microcode word
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type SALS_Bus is record
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SALS_PN : STD_LOGIC;
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SALS_CN : STD_LOGIC_VECTOR(0 to 5);
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SALS_PS : STD_LOGIC;
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SALS_PA : STD_LOGIC;
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SALS_CH : STD_LOGIC_VECTOR(0 to 3);
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SALS_CL : STD_LOGIC_VECTOR(0 to 3);
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SALS_CM : STD_LOGIC_VECTOR(0 to 2);
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SALS_CU : STD_LOGIC_VECTOR(0 to 1);
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SALS_CA : STD_LOGIC_VECTOR(0 to 3);
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SALS_CB : STD_LOGIC_VECTOR(0 to 1);
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SALS_CK : STD_LOGIC_VECTOR(0 to 3);
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SALS_PK : STD_LOGIC;
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SALS_PC : STD_LOGIC;
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SALS_CD : STD_LOGIC_VECTOR(0 to 3);
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SALS_CF : STD_LOGIC_VECTOR(0 to 2);
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SALS_CG : STD_LOGIC_VECTOR(0 to 1);
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SALS_CV : STD_LOGIC_VECTOR(0 to 1);
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SALS_CC : STD_LOGIC_VECTOR(0 to 2);
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SALS_CS : STD_LOGIC_VECTOR(0 to 3);
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SALS_AA : STD_LOGIC;
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SALS_SA : STD_LOGIC;
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SALS_AK : STD_LOGIC;
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end record SALS_Bus;
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-- The CTRL register is a subset of the SALS which is maintained
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-- after the rest of the SALS is cleared as the next word is read
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type CTRL_REG is record
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CTRL_CD : STD_LOGIC_VECTOR(0 to 3); -- 05C
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STRAIGHT : STD_LOGIC; -- Similar to CF(0) inverted
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CROSSED : STD_LOGIC; -- Same as CF(0)
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CTRL_CC : STD_LOGIC_VECTOR(0 to 2); -- CTRL REG BUS
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GT_A_REG_HI : STD_LOGIC; -- Same as CF(1)
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GT_A_REG_LO : STD_LOGIC; -- Same as CF(2)
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COMPUTE_CY_LCH : STD_LOGIC; -- 06C & CTRL REG BUS
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CTRL_CG : STD_LOGIC_VECTOR(0 to 1); -- 03B,06B & CTRL_REG_BUS
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GT_B_REG_HI : STD_LOGIC; -- 06B, same as CG(0)
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GT_B_REG_LO : STD_LOGIC; -- 06B, same as CG(1)
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CTRL_CV : STD_LOGIC_VECTOR(0 to 1); -- CTRL REG BUS
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CTRL_CS : STD_LOGIC_VECTOR(0 to 3); -- CTRL REG BUS
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end record CTRL_REG;
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-- The Priority bus is used to vector the microcode address when an external
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-- interrupt occurs
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type PRIORITY_BUS_Type is record
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STOP_PULSE : STD_LOGIC; -- X0
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PROTECT_PULSE : STD_LOGIC; -- X1
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WRAP_PULSE : STD_LOGIC; -- X2
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MPX_SHARE_PULSE : STD_LOGIC; -- X3
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SX_CHAIN_PULSE : STD_LOGIC; -- X4
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MACH_CHK_PULSE : STD_LOGIC; -- X5
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IPL_PULSE : STD_LOGIC; -- X6
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FORCE_IJ_PULSE : STD_LOGIC; -- X7
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PRIORITY_PULSE : STD_LOGIC; -- XP
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end record PRIORITY_BUS_Type;
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-- The E Switch bus contains the various signals corresponding to the legends on the
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-- selector switch. Only one of these signals will be true.
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type E_SW_BUS_Type is record
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-- Inner ring
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I_SEL,J_SEL,U_SEL,V_SEL,L_SEL,T_SEL,D_SEL,R_SEL,S_SEL,G_SEL,H_SEL,FI_SEL,FT_SEL : STD_LOGIC;
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-- Mid ring
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MS_SEL, LS_SEL : STD_LOGIC; -- LS marked as AS on dial
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-- Outer ring
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Q_SEL,C_SEL,F_SEL,TT_SEL,TI_SEL,JI_SEL,
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E_SEL_SW_GS,E_SEL_SW_GT,E_SEL_SW_GUV_GCD,
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E_SEL_SW_HS,E_SEL_SW_HT,E_SEL_SW_HUV_HCD : STD_LOGIC;
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end record E_SW_BUS_Type;
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-- Mpx Tags Out are the tag signals from the CPU to a peripheral
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type MPX_TAGS_OUT is record
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OPL_OUT,
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ADR_OUT,
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ADR_OUT2, -- What is this?
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CMD_OUT,
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STA_OUT,
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SRV_OUT,
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HLD_OUT,
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SEL_OUT,
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SUP_OUT,
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MTR_OUT,
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CLK_OUT : STD_LOGIC;
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end record MPX_TAGS_OUT;
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-- Mpx Tags In are the tag signals from a peripheral to the CPU
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type MPX_TAGS_IN is record
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OPL_IN,
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ADR_IN,
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STA_IN,
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SRV_IN,
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SEL_IN,
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REQ_IN,
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MTR_IN : STD_LOGIC;
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end record MPX_TAGS_IN;
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-- List of front panel indicators
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subtype IndicatorRange is integer range 0 to 249; -- 218 through 249 are temp debug items
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end package Buses_package;
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