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78 lines
2.7 KiB
VHDL
78 lines
2.7 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-07A1.vhd
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-- Creation Date: 22:26:31 18/04/05
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-- Description:
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-- MN (MSAR) indicators
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY MNInd IS
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port
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(
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-- Inputs
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MN : IN STD_LOGIC_VECTOR(0 to 15);
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M_P, N_P : IN STD_LOGIC;
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LAMP_TEST : IN STD_LOGIC; -- 04A
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MAIN_STG,LOCAL_STG : IN STD_LOGIC; -- 04D
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N1401_MODE : IN STD_LOGIC; -- 05A
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-- Outputs
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IND_M : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
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IND_N : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
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IND_MAIN_STG,IND_LOC_STG,IND_COMP_MODE : OUT STD_LOGIC;
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MN_PC : OUT STD_LOGIC -- 06C,11A,13A
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);
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END MNInd;
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ARCHITECTURE FMD OF MNInd IS
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BEGIN
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-- Fig 5-07A
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IND_M <= "111111111" when LAMP_TEST='1' else MN(0 to 7) & M_P;
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IND_N <= "111111111" when LAMP_TEST='1' else MN(8 to 15) & N_P;
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IND_MAIN_STG <= MAIN_STG or LAMP_TEST;
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IND_LOC_STG <= LOCAL_STG or LAMP_TEST;
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IND_COMP_MODE <= N1401_MODE or LAMP_TEST;
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MN_PC <= (EvenParity(MN(0 to 7) & M_P) or EvenParity(MN(8 to 15) & N_P)) and not LOCAL_STG; -- AA1C4,AA1C5,AA1E5,AA1E6,AA1C3,AA1J3
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END FMD;
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