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110 lines
4.3 KiB
VHDL
110 lines
4.3 KiB
VHDL
---------------------------------------------------------------------------
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-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: FMD2030_5-07B1.vhd
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-- Creation Date: 11/01/09
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-- Description:
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-- SAR (MSAR) and SA (Protection Stack Address) registers
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-13
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-- Initial Release
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--
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--
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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library work;
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use work.Gates_package.all;
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use work.Buses_package.all;
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ENTITY SARSA IS
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port
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(
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-- Inputs
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M_ASSM_BUS,N_ASSM_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 05B
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MACH_RST_SW : IN STD_LOGIC; -- 03D
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MACH_RESET_SET_LCH_DLY : IN STD_LOGIC; -- 04B
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MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
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CPU_RD_PWR : IN STD_LOGIC; -- 04D
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SEL_RDWR_CTRL : IN STD_LOGIC; -- 12C
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GT_MAN_SET_MN : IN STD_LOGIC; -- 03D
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CHNL_RD_CALL : IN STD_LOGIC; -- 04D
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XH,XL,XXH : IN STD_LOGIC; -- 08C
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MAIN_STORAGE_CP : IN STD_LOGIC; -- 08B
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MPX_CP : IN STD_LOGIC; -- 08B
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-- Outputs
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MN, MN_ST3 : OUT STD_LOGIC_VECTOR(0 to 15);
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M_P, N_P , M_ST3_P, N_ST3_P: OUT STD_LOGIC;
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SA_REG : OUT STD_LOGIC_VECTOR(0 to 7);
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EARLY_M0, M_REG_0 : OUT STD_LOGIC;
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MACH_RST_PROTECT : OUT STD_LOGIC;
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-- Clocks
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T1 : IN STD_LOGIC;
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SEL_T1 : IN STD_LOGIC
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);
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END SARSA;
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ARCHITECTURE FMD OF SARSA IS
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signal LATCH_MN, LATCH_MN_ST3 : STD_LOGIC;
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signal sMACH_RST_PROTECT : STD_LOGIC;
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signal STACK_ADDR_REG_SET: STD_LOGIC;
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signal SA_REG_IN, SA_REG_IN1, SA_REG_IN2 : STD_LOGIC_VECTOR(0 to 7);
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signal sMN : STD_LOGIC_VECTOR(0 to 15);
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BEGIN
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-- Fig 5-07B
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sMACH_RST_PROTECT <= MACH_RST_SW; -- AA3H3
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MACH_RST_PROTECT <= sMACH_RST_PROTECT;
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LATCH_MN <= MACH_RESET_SET_LCH_DLY or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1D4
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LATCH_MN_ST3 <= sMACH_RST_PROTECT or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1E4
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REG_M: PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN,sMN(0 to 7)); -- AA1D2
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REG_MP: PH port map(M_ASSM_BUS(8),LATCH_MN,M_P); -- AA1D2
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REG_N: PHV8 port map(N_ASSM_BUS(0 to 7),LATCH_MN,sMN(8 to 15) ); -- AA1D3
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REG_NP: PH port map(N_ASSM_BUS(8),LATCH_MN,N_P); -- AA1D3
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REG_MST3: PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN_ST3,MN_ST3(0 to 7)); -- AA1D5
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REG_MST3P: PH port map(M_ASSM_BUS(8),LATCH_MN_ST3,M_ST3_P); -- AA1D5
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REG_NST3: PHV8 port map(N_ASSM_BUS(0 TO 7),LATCH_MN_ST3,MN_ST3(8 to 15)); -- AA1D6
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REG_NST3P: PH port map(N_ASSM_BUS(8),LATCH_MN_ST3,N_ST3_P); -- AA1D6
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STACK_ADDR_REG_SET <= CHNL_RD_CALL or (CPU_RD_PWR and T1) or GT_MAN_SET_MN or sMACH_RST_PROTECT; -- BE3H7
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SA_REG_IN1 <= "111" & M_ASSM_BUS(0 to 4) when MAIN_STORAGE_CP='1' else "00000000"; -- PE3J6
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SA_REG_IN2 <= XXH & XL & XH & N_ASSM_BUS(0 to 4) when MPX_CP='1' else "00000000"; -- PE3J6
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SA_REG_IN <= SA_REG_IN1 or SA_REG_IN2; -- PE3J6
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REG_SA: PHV8 port map(SA_REG_IN,STACK_ADDR_REG_SET,SA_REG); -- PE3J6
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MN <= sMN;
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EARLY_M0 <= M_ASSM_BUS(0);
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M_REG_0 <= sMN(0);
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end FMD;
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