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Minor change to pinouts for v1.1 board

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This commit is contained in:
J 2019-03-26 12:05:44 -04:00
parent d21f78598e
commit 4d896e726c
3 changed files with 32 additions and 40 deletions
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3
cpu_up5k_42s.vhd
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@ -22,7 +22,6 @@ entity cpu_up5k is port (
mso : inout std_logic;
mio2: inout std_logic;
mio3: inout std_logic;
x1 : inout std_logic_vector(7 downto 0);
lcs : inout std_logic;
la0 : inout std_logic;
lscl : inout std_logic;
@ -220,8 +219,6 @@ begin
y <= (others => 'Z'); -- high Z input
x <= to_open_drain(pio_data_o.d(5 downto 0));
end if;
x1 <= pio_data_o.d(7 downto 0);
-- x1 <= x"55"; -- pio_data_o.d(7 downto 0);
end if;
if data_slaves_o(DEV_UART0).wr = '1' and data_slaves_o(DEV_UART0).a = x"ABCD0104" then
c := character'val(to_integer(unsigned(data_slaves_o(DEV_UART0).d(7 downto 0))));

64
free42.pcf
View File

@ -1,36 +1,32 @@
#set_io x[1] 42
#set_io x[2] 38
#set_io x[3] 37
#set_io x[4] 36
#set_io x[5] 35
#set_io x[6] 34
#
#set_io y[1] 32
#set_io y[2] 31
#set_io y[3] 28
#set_io y[4] 27
#set_io y[5] 26
#set_io y[6] 25
#set_io y[7] 23
#
#set_io pon 43
#
#set_io lcs 21
#set_io lscl 19
#set_io lsi 18
#set_io la0 20
#
set_io lcs 45
set_io lscl 47
set_io lsi 46
set_io la0 2
set_io x[1] 42
set_io x[2] 38
set_io x[3] 37
set_io x[4] 36
set_io x[5] 35
set_io x[6] 34
set_io x1[0] 26
set_io x1[1] 27
set_io x1[2] 32
set_io x1[3] 35
set_io x1[4] 31
set_io x1[5] 37
set_io x1[6] 34
set_io x1[7] 43
set_io y[1] 32
set_io y[2] 31
set_io y[3] 28
set_io y[4] 27
set_io y[5] 26
set_io y[6] 25
set_io y[7] 23
set_io pon 43
set_io lcs 21
set_io lscl 19
set_io lsi 18
set_io la0 20
set_io mio2 11
set_io mio3 10
set_io mrcs 4
set_io mfcs 16
set_io msck 15
set_io mso 17
set_io msi 14

5
up5k_tb.vhd
View File

@ -21,7 +21,6 @@ architecture beh of up5k_tb is
end to_hex_string;
signal x : std_logic_vector(6 downto 1);
signal x1 : std_logic_vector(7 downto 0);
signal y : std_logic_vector(7 downto 1);
signal pon : std_logic;
signal mfsc : std_logic;
@ -45,7 +44,7 @@ signal x1 : std_logic_vector(7 downto 0);
port map( x => x, y => y, pon => pon,
mfcs => mfcs, mrcs => mrcs, msck => msck, msi => msi, mso => mso,
mio2 => mio2, mio3 => mio3,
lcs => lcs, la0 => la0, lscl => lscl, lsi => lsi , x1 => x1);
lcs => lcs, la0 => la0, lscl => lscl, lsi => lsi);
pon <= '1';
y <= (others => 'H');
@ -67,7 +66,7 @@ signal x1 : std_logic_vector(7 downto 0);
if ox /= x then
ox <= x;
write(l, string'("X: Write"));
write(l, to_hex_string(x1));
write(l, to_hex_string(x));
writeline(output, l);
end if;
if oy /= y then