Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used

cpu2j0_pkg.vhd

@@ -37,7 +37,7 @@ package cpu2j0_pack is
       rdy  : std_logic;
    end record;
 
-   type cpu_debug_cmd_t is (BREAK, STEP, INSERT, CONTINUE);
+   type cpu_debug_cmd_t is (BRK, STEP, INSERT, CONTINUE);
 
    type cpu_debug_i_t is record
       en   : std_logic;
@@ -46,9 +46,9 @@ package cpu2j0_pack is
       d    : std_logic_vector(31 downto 0);
       d_en : std_logic;
    end record;
-   constant CPU_DEBUG_NOP : cpu_debug_i_t := (en => '0', cmd => BREAK, ir => (others => '0'), d => (others => '0'), d_en => '0');
+   constant CPU_DEBUG_NOP : cpu_debug_i_t := (en => '0', cmd => BRK, ir => (others => '0'), d => (others => '0'), d_en => '0');
 
-   type cpu_event_cmd_t is (INTERRUPT, ERROR, BREAK, RESET_CPU);
+   type cpu_event_cmd_t is (INT, ERR, BREAK, RST);
 
    type cpu_event_i_t is record
       en   : std_logic;
@@ -58,7 +58,7 @@ package cpu2j0_pack is
       lvl  : std_logic_vector(3 downto 0);
    end record;
    constant NULL_CPU_EVENT_I : cpu_event_i_t := (en => '0',
-                                                 cmd => INTERRUPT,
+                                                 cmd => INT,
                                                  vec => (others => '0'),
                                                  msk => '0',
                                                  lvl => (others => '1'));

cpu_pure_tb.vhh

@@ -103,7 +103,7 @@ begin
 
   with debug_i_cmd select
     debug_i.cmd <=
-    BREAK when "00",
+    BRK when "00",
     STEP when "01",
     INSERT when "10",
     CONTINUE when others;

datapath.vhd

@@ -223,7 +223,7 @@ begin
             next_state := AWAIT_IF;
             -- stop requesting debug mode once we're in debug mode
             this.enter_debug := (others => '0');
-          elsif this.debug_state = RUN and debug_i.en = '1' and debug_i.cmd = BREAK then
+          elsif this.debug_state = RUN and debug_i.en = '1' and debug_i.cmd = BRK then
             -- schedule entering debug mode
             -- TODO: we could probably set enter_debug(0) = '1' to
             -- immediately enter, but need to be careful that mask_int is
@@ -248,7 +248,7 @@ begin
           elsif this.debug_state = READY and debug_i.en = '1' then
             -- handle debug command
             case debug_i.cmd is
-              when BREAK =>
+              when BRK =>
                 -- A BREAK cmd when already in the READY state does nothing
                 this.debug_o.ack := '1';
               when INSERT =>

decode_core.vhd

@@ -158,16 +158,18 @@ begin
     system_op(event_i)
     -- Interrupts, (address) errors, reset and break
       when delay_slot = '0' and event_i.en = '1' and (
-           ( maskint = '0' and event_i.cmd = INTERRUPT and ( ibit < event_i.lvl or event_i.msk = '1' ) ) or
-           ( event_i.cmd = ERROR or event_i.cmd = RESET_CPU or event_i.cmd = BREAK ) ) else
+           ( maskint = '0' and event_i.cmd = INT and ( ibit < event_i.lvl or event_i.msk = '1' ) ) 
+-- or
+--           ( event_i.cmd = ERR or event_i.cmd = RST or event_i.cmd = BREAK ) 
+) else
     -- Slot Illegal Instruction
-    system_op(SLOT_ILLEGAL)
+    system_op(SLOT_ILLEGAL_I)
       when delay_slot = '1' and (illegal_delay_slot or illegal_instr) = '1' else
     -- General Illegal Instruction
-    system_op(GENERAL_ILLEGAL)
+    system_op(GENERAL_ILLEGAL_I)
       when illegal_instr = '1' else
     -- Break Instruction
-    system_op(BREAK)
+    system_op(BREAK_I)
       when delay_slot = '0' and enter_debug = '1' else
     -- Normal instruction
     normal_op(if_dr);

decode_pkg.vhd

@@ -275,13 +275,13 @@ package decode_pack is
     constant DEC_CORE_RESET : decode_core_reg_t := (maskint => '0', delay_slot => '0', id_stall => '0', instr_seq_zero => '0', op => (plane => SYSTEM_INSTR, code => x"0300", addr => x"01"), ilevel => x"0");
     -- Reset vector specific to the microcode ROM. Uses a different starting addr.
     constant DEC_CORE_ROM_RESET : decode_core_reg_t := (maskint => '0', delay_slot => '0', id_stall => '0', instr_seq_zero => '0', op => (plane => SYSTEM_INSTR, code => x"0300", addr => x"da"), ilevel => x"0");
-    type system_instr_t is (BREAK, ERROR, GENERAL_ILLEGAL, INTERRUPT, RESET_CPU, SLOT_ILLEGAL);
+    type system_instr_t is (BREAK_I, ERROR_I, GENERAL_ILLEGAL_I, INTERRUPT_I, RESET_CPU_I, SLOT_ILLEGAL_I);
     type system_instr_addr_array is array (system_instr_t range <>) of std_logic_vector(7 downto 0);
-    constant system_instr_rom_addrs : system_instr_addr_array := (BREAK => x"f2", ERROR => x"e9", GENERAL_ILLEGAL => x"c9", INTERRUPT => x"e0", RESET_CPU => x"d9", SLOT_ILLEGAL => x"d1");
+    constant system_instr_rom_addrs : system_instr_addr_array := (BREAK_I => x"f2", ERROR_I => x"e9", GENERAL_ILLEGAL_I => x"c9", INTERRUPT_I => x"e0", RESET_CPU_I => x"d9", SLOT_ILLEGAL_I => x"d1");
     type system_instr_code_array is array (system_instr_t range <>) of std_logic_vector(11 downto 8);
-    constant system_instr_codes : system_instr_code_array := (BREAK => x"2", ERROR => x"1", GENERAL_ILLEGAL => x"7", INTERRUPT => x"0", RESET_CPU => x"3", SLOT_ILLEGAL => x"6");
+    constant system_instr_codes : system_instr_code_array := (BREAK_I => x"2", ERROR_I => x"1", GENERAL_ILLEGAL_I => x"7", INTERRUPT_I => x"0", RESET_CPU_I => x"3", SLOT_ILLEGAL_I => x"6");
     type system_event_code_array is array (cpu_event_cmd_t range <>) of std_logic_vector(11 downto 8);
-    constant system_event_codes : system_event_code_array := (INTERRUPT => x"0", ERROR => x"1", BREAK => x"2", RESET_CPU => x"3");
+    constant system_event_codes : system_event_code_array := (INT => x"0", ERR => x"1", BREAK => x"2", RST => x"3");
     type system_event_instr_array is array (cpu_event_cmd_t range <>) of system_instr_t;
-    constant system_event_instrs : system_event_instr_array := (INTERRUPT => INTERRUPT, ERROR => ERROR, BREAK => BREAK, RESET_CPU => RESET_CPU);
+    constant system_event_instrs : system_event_instr_array := (INT => INTERRUPT_I, ERR => ERROR_I, BREAK => BREAK_I, RST => RESET_CPU_I);
 end;