mirror of
https://github.com/j-core/j-core-ice40.git
synced 2026-03-05 18:59:03 +00:00
move back to ghdl because nvc can't trace records yet, even though it simulates them
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15
ghdl_lattice.sh
Normal file
15
ghdl_lattice.sh
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@@ -0,0 +1,15 @@
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#!/bin/sh
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rm *.o *.cf
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ghdl -a cpu2j0_pkg.vhd components_pkg.vhd mult_pkg.vhd decode_pkg.vhd decode_body.vhd datapath_pkg.vhd cpu.vhd decode.vhd decode_core.vhd decode_table.vhd decode_table_reverse.vhd datapath.vhd register_file.vhd mult.vhd
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ghdl -a data_bus_pkg.vhd monitor_pkg.vhd ram_init.vhd lattice_ebr.vhd bus_monitor.vhd timeout_cnt.vhd cpu_simple_sram.vhd
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ghdl -a --work=sb_ice40_components_syn clk_sim.vhd
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ghdl -a cpu_lattice.vhd lattice_tb.vhd
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ghdl -e lattice_tb
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./lattice_tb --stop-time=2700ns --wave=out.ghw
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20
ram_init.vhd
20
ram_init.vhd
@@ -1161,17 +1161,17 @@ package bootrom is
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x"616e6765",
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x"7365743a",
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x"20202031",
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x"303a6530",
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x"66303765",
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x"32323466",
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x"65320a62",
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x"313a6161",
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x"34323266",
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x"33346365",
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x"34630a62",
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x"75696c64",
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x"3a204672",
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x"69204d61",
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x"72202038",
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x"2030313a",
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x"31313a34",
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x"35204553",
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x"3a205361",
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x"74204d61",
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x"72202039",
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x"2031383a",
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x"33393a32",
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x"31204553",
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x"54203230",
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x"31390a00",
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others => x"00000000" );
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@@ -106,7 +106,7 @@ architecture two_bank of register_file is
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constant ZERO_ADDR : addr_t := (others => '0');
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type ram_type is array(0 to NUM_REGS - 1) of data_t;
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signal bank_a, bank_b : ram_type;
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signal bank_a, bank_b : ram_type := (others => (others => '0'));
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signal reg0 : data_t;
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signal da : std_logic_vector(REG_WIDTH-1 downto 0);
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@@ -175,4 +175,4 @@ begin
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ex_pipes(1) <= ex_pipes(0);
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end if;
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end process;
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end architecture;
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end architecture;
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