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47 lines
1.1 KiB
VHDL
47 lines
1.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.cpu2j0_pack.all;
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entity cpu_sram is
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port (
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clk : in std_logic;
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ibus_i : in cpu_instruction_o_t;
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ibus_o : out cpu_instruction_i_t;
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db_i : in cpu_data_o_t;
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db_o : out cpu_data_i_t
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);
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end;
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architecture struc of cpu_sram is
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signal db_we : std_logic_vector(3 downto 0);
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signal iclk : std_logic;
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begin
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db_we <= (db_i.wr and db_i.we(3)) &
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(db_i.wr and db_i.we(2)) &
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(db_i.wr and db_i.we(1)) &
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(db_i.wr and db_i.we(0));
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-- clk memory on negative edge to avoid wait states
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iclk <= not clk;
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r : entity work.asymmetric_ram
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generic map (ADDR_WIDTH => 12)
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port map(clkA => iclk,
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clkB => iclk,
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enA => ibus_i.en,
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addrA => ibus_i.a(12 downto 1),
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doA => ibus_o.d,
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enB => db_i.en,
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weB => db_we,
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addrB => db_i.a(12 downto 2),
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diB => db_i.d,
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doB => db_o.d);
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-- simply ack immediately. Should this simulate different delays?
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db_o.ack <= db_i.en;
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ibus_o.ack <= ibus_i.en;
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end architecture struc;
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