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43 lines
1.0 KiB
VHDL
43 lines
1.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity lattice_tb is
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end lattice_tb;
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architecture beh of lattice_tb is
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function to_hex_string(s: in std_logic_vector) return string is
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constant hex : string (1 to 16) := "0123456789ABCDEF";
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variable ss : std_logic_vector(31 downto 0) := (others => '0');
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variable ret : string (1 to ss'left/4+1);
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begin
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ss(s'range) := s;
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for i in 0 to ss'left/4 loop
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ret(i+1) := hex(to_integer(unsigned(ss(ss'left - i*4 downto ss'left - i*4 -3)))+1);
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end loop;
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return ret;
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end to_hex_string;
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signal led : std_logic_vector(7 downto 0) := x"00";
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signal ol : std_logic_vector(7 downto 0) := x"00";
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begin
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fp: entity work.cpu_lattice
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port map(led => led);
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p0: process(led)
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variable l : line;
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begin
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if led /= ol then
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ol <= led;
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write(l, string'("LED: Write "));
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write(l, to_hex_string(led));
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write(l, " at " & time'image(now));
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writeline(output, l);
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end if;
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end process;
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end beh;
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