Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk

cpu_lattice.vhd

@@ -55,14 +55,6 @@ architecture behaviour of cpu_lattice is
 begin
   rst <= '1', '0' after 10 ns;
 
---  clk_gen : process
---  begin
---    clk <= '0';
---    wait for 10 ns;
---    clk <= '1';
---    wait for 10 ns;
---  end process;
-
   vh <= '1';
 
   ck: SB_HFOSC generic map (clkhf_div => "0b10")
@@ -132,20 +124,7 @@ begin
 
   -- intercept and print PIO and UART writes
 
-  led(7 downto 3) <= le(7 downto 3);
-
-  rgb: SB_RGBA_DRV generic map ( CURRENT_MODE => "0b1",
-                                 RGB0_CURRENT => "0b000001",
-                                 RGB1_CURRENT => "0b000001",
-                                 RGB2_CURRENT => "0b000001")
-              port map ( curren => '1',
-                         rgbleden => '1',
-                         rgb0pwm => le(0),
-                         rgb1pwm => le(1),
-                         rgb2pwm => le(2),
-                         rgb0    => led(0),
-                         rgb1    => led(1),
-                         rgb2    => led(2));
+  led <= le;
 
   l0: process(clk)
     variable uart_line : line;
@@ -157,7 +136,7 @@ begin
 --        write(l, string'("LED: Write "));
 --        write(l, " at " & time'image(now));
 --        writeline(output, l);
-      le <= pio_data_o.d(7 downto 0);
+          le <= pio_data_o.d(7 downto 0);
       end if;
       if data_slaves_o(DEV_UART0).wr = '1' and data_slaves_o(DEV_UART0).a = x"ABCD0104" then
 --        c := character'val(to_integer(unsigned(data_slaves_o(DEV_UART0).d(7 downto 0))));

lattice_tb.vhd

@@ -20,21 +20,12 @@ architecture beh of lattice_tb is
    return ret;
   end to_hex_string;
 
-  signal clk : std_logic;
   signal led : std_logic_vector(7 downto 0) := x"00";
   signal ol  : std_logic_vector(7 downto 0) := x"00";
 begin
 
-   c0: process
-   begin 
-      clk <= '0';
-      wait for 10 ns;
-      clk <= '1';
-      wait for 10 ns;
-   end process;
-
    fp: entity work.cpu_lattice
-      port map(clk => clk, led => led);
+      port map(led => led);
 
    p0: process(led)
    variable l : line;

nvc_lattice.sh

@@ -1,9 +1,13 @@
 #!/bin/sh
 
+rm -r work sb_ice40_components_syn  
+
 nvc -a cpu2j0_pkg.vhd components_pkg.vhd mult_pkg.vhd decode_pkg.vhd decode_body.vhd datapath_pkg.vhd cpu.vhd decode.vhd decode_core.vhd decode_table.vhd decode_table_reverse.vhd datapath.vhd register_file.vhd mult.vhd 
 
-nvc -a  data_bus_pkg.vhd monitor_pkg.vhd ram_init.vhd lattice_ebr.vhd bus_monitor.vhd timeout_cnt.vhd cpu_simple_sram.vhd cpu_lattice.vhd
+nvc -a  data_bus_pkg.vhd monitor_pkg.vhd ram_init.vhd lattice_ebr.vhd bus_monitor.vhd timeout_cnt.vhd cpu_simple_sram.vhd
 
-nvc -a lattice_tb.vhd
+nvc --work=sb_ice40_components_syn -a clk_sim.vhd
 
-nvc -e -V lattice_tb
+nvc -L . -a cpu_lattice.vhd lattice_tb.vhd
+
+nvc -L . -e -V lattice_tb

ram_init.vhd

@@ -1160,17 +1160,17 @@ package bootrom is
     x"3a206368",
     x"616e6765",
     x"7365743a",
-    x"20202036",
-    x"3a653964",
-    x"66303262",
-    x"33313236",
-    x"640a6275",
+    x"20202038",
+    x"3a613836",
+    x"38366236",
+    x"63393235",
+    x"310a6275",
     x"696c643a",
-    x"20547565",
+    x"20546875",
     x"204d6172",
-    x"20203520",
-    x"30303a33",
-    x"373a3435",
+    x"20203720",
+    x"32323a32",
+    x"323a3534",
     x"20455354",
     x"20323031",
     x"390a0000",

up5k.pcf

@@ -1,8 +1,18 @@
-set_io led[0] 39
-set_io led[1] 40
-set_io led[2] 41
-set_io led[3] 44
-set_io led[4] 45
-set_io led[5] 46
-set_io led[6] 47
-set_io led[7] 48
+
+#set_io led[0] 39
+#set_io led[1] 40
+#set_io led[2] 41
+#set_io led[3] 44
+#set_io led[4] 45
+#set_io led[5] 46
+#set_io led[6] 47
+#set_io led[7] 48
+
+set_io led[0] 26
+set_io led[1] 27
+set_io led[2] 32
+set_io led[3] 35
+set_io led[4] 31
+set_io led[5] 37
+set_io led[6] 34
+set_io led[7] 43