mirror of
https://github.com/j-core/j-core-ice40.git
synced 2026-02-27 00:59:59 +00:00
118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
#define LEDPORT (*(volatile unsigned long *)0xabcd0000)
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extern char version_string[];
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char ram0[256]; /* working ram for CPU tests */
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void
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putstr (char *str)
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{
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while (*str)
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{
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if (*str == '\n')
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uart_tx ('\r');
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uart_tx (*(str++));
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}
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}
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#ifndef NO_DDR
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#define DDR_BASE 0x10000000
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#define MemoryRead(A) (*(volatile int*)(A))
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#define MemoryWrite(A,V) *(volatile int*)(A)=(V)
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//SD_A <= address_reg(25 downto 13); --address row
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//SD_BA <= address_reg(12 downto 11); --bank_address
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//cmd := address_reg(6 downto 4); --bits RAS & CAS & WE
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int DdrInitData[] = {
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// AddressLines Bank Command
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#ifndef LPDDR
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(0x000 << 13) | (0 << 11) | (7 << 4), //CKE=1; NOP="111"
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(0x400 << 13) | (0 << 11) | (2 << 4), //A10=1; PRECHARGE ALL="010"
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(0x001 << 13) | (1 << 11) | (0 << 4), //EMR disable DLL; BA="01"; LMR="000"
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#ifndef DDR_BL4
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(0x121 << 13) | (0 << 11) | (0 << 4), //SMR reset DLL, CL=2, BL=2; LMR="000"
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#else
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(0x122 << 13) | (0 << 11) | (0 << 4), //SMR reset DLL, CL=2, BL=4; LMR="000"
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#endif
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(0x400 << 13) | (0 << 11) | (2 << 4), //A10=1; PRECHARGE ALL="010"
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(0x000 << 13) | (0 << 11) | (1 << 4), //AUTO REFRESH="001"
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(0x000 << 13) | (0 << 11) | (1 << 4), //AUTO REFRESH="001
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#ifndef DDR_BL4
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(0x021 << 13) | (0 << 11) | (0 << 4) //clear DLL, CL=2, BL=2; LMR="000"
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#else
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(0x022 << 13) | (0 << 11) | (0 << 4) //clear DLL, CL=2, BL=4; LMR="000"
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#endif
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#else // LPDDR
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(0x000 << 13) | (0 << 11) | (7 << 4), //CKE=1; NOP="111"
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(0x000 << 13) | (0 << 11) | (7 << 4), //NOP="111" after 200 uS
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(0x400 << 13) | (0 << 11) | (2 << 4), //A10=1; PRECHARGE ALL="010"
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(0x000 << 13) | (0 << 11) | (1 << 4), //AUTO REFRESH="001"
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(0x000 << 13) | (0 << 11) | (1 << 4), //AUTO REFRESH="001"
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(0x021 << 13) | (0 << 11) | (0 << 4), //SMR CL=2, BL=2; LMR="000"
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(0x000 << 13) | (1 << 11) | (0 << 4), //EMR BA="01"; LMR="000" Full strength full array
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(0x000 << 13) | (0 << 11) | (7 << 4) //NOP="111" after ? uS
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#endif
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};
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int
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ddr_init (void)
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{
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volatile int i, j, k = 0;
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for (i = 0; i < sizeof (DdrInitData) / sizeof (int); ++i)
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{
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MemoryWrite (DDR_BASE + DdrInitData[i], 0);
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for (j = 0; j < 4; ++j)
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++k;
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}
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for (j = 0; j < 100; ++j)
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++k;
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k += MemoryRead (DDR_BASE); //Enable DDR
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return k;
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}
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#endif /* NO_DDR */
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void
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led(int v)
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{
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LEDPORT = v;
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}
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void
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main_sh (void)
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{
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volatile int i;
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led(0x40);
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uart_set_baudrate ();
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led(0x042);
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#ifndef NO_TESTS
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putstr ("CPU tests passed\n");
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led(0x043);
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#endif
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#ifndef NO_DDR
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putstr ("DDR Init\n");
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led(0x042);
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ddr_init ();
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#endif /* NO_DDR */
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putstr ("GDB Stub for HS-2J0 SH2 ROM\n");
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putstr (version_string);
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led(0x50);
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for (i=0; i<800; i++) {}
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led(0x55);
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for (i=0; i<800; i++) {}
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led(0xaa);
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for (;;) {
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for (i=0; i<1200000; i++) {}
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led(0x55);
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for (i=0; i<1200000; i++) {}
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led(0xaa);
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}
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}
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