J f16479b668 some more instruction colation

2019-09-26 21:15:44 -04:00

..

startup

some more instruction colation

2019-09-26 21:15:44 -04:00

tests

Change back to complete ROM tests. NOTE: may overflow FPGA

2019-09-22 23:06:25 -04:00

entry.c

Change back to complete ROM tests. NOTE: may overflow FPGA

2019-09-22 23:06:25 -04:00

font5x7.h

Drives LCD with ASCII renderer. Split main.c off for 42s

2019-03-18 17:39:56 -04:00

gdb.c

Add in the test rom

2019-03-03 19:35:20 -05:00

gdb.h

Add in the test rom

2019-03-03 19:35:20 -05:00

main_up5k_42s.c

Change back to complete ROM tests. NOTE: may overflow FPGA

2019-09-22 23:06:25 -04:00

main.c

Sync RAM register file implemntation

2019-03-13 17:05:56 -04:00

Makefile

some more instruction colation

2019-09-26 21:15:44 -04:00

march.c

With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.

2019-03-25 21:50:49 -04:00

sh2.c

Add in the test rom

2019-03-03 19:35:20 -05:00

sh2.h

Add in the test rom

2019-03-03 19:35:20 -05:00

syscalls.h

Add in the test rom

2019-03-03 19:35:20 -05:00

uart16550.c

Add in the test rom

2019-03-03 19:35:20 -05:00

uartlite.c

Add in the test rom

2019-03-03 19:35:20 -05:00