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https://github.com/j-core/j-core-ice40.git
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99 lines
3.0 KiB
VHDL
99 lines
3.0 KiB
VHDL
-- Interface Library for the HS-2J0 CPU core
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library ieee;
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use ieee.std_logic_1164.all;
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package cpu2j0_pack is
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type cpu_instruction_o_t is record
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en : std_logic;
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a : std_logic_vector(31 downto 1);
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jp : std_logic;
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end record;
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constant NULL_INST_O : cpu_instruction_o_t := (en => '0', a => (others => '0'), jp => '0');
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type cpu_instruction_i_t is record
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d : std_logic_vector(15 downto 0);
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ack : std_logic;
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end record;
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type cpu_data_o_t is record
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en : std_logic;
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a : std_logic_vector(31 downto 0);
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rd : std_logic;
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wr : std_logic;
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we : std_logic_vector(3 downto 0);
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d : std_logic_vector(31 downto 0);
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end record;
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constant NULL_DATA_O : cpu_data_o_t := (en => '0', a => (others => '0'), rd => '0', wr => '0', we => "0000", d => (others => '0'));
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type cpu_data_i_t is record
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d : std_logic_vector(31 downto 0);
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ack : std_logic;
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end record;
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type cpu_debug_o_t is record
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ack : std_logic;
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d : std_logic_vector(31 downto 0);
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rdy : std_logic;
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end record;
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type cpu_debug_cmd_t is (BRK, STEP, INSERT, CONTINUE);
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type cpu_debug_i_t is record
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en : std_logic;
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cmd : cpu_debug_cmd_t;
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ir : std_logic_vector(15 downto 0);
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d : std_logic_vector(31 downto 0);
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d_en : std_logic;
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end record;
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constant CPU_DEBUG_NOP : cpu_debug_i_t := (en => '0', cmd => BRK, ir => (others => '0'), d => (others => '0'), d_en => '0');
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type cpu_event_cmd_t is (INT, ERR, BREAK, RST);
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type cpu_event_i_t is record
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en : std_logic;
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cmd : cpu_event_cmd_t;
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vec : std_logic_vector(7 downto 0);
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msk : std_logic;
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lvl : std_logic_vector(3 downto 0);
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end record;
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constant NULL_CPU_EVENT_I : cpu_event_i_t := (en => '0',
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cmd => INT,
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vec => (others => '0'),
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msk => '0',
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lvl => (others => '1'));
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type cpu_event_o_t is record
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ack : std_logic;
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lvl : std_logic_vector(3 downto 0);
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slp : std_logic;
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dbg : std_logic;
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end record;
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component cpu is port (
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clk : in std_logic;
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rst : in std_logic;
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db_o : out cpu_data_o_t;
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db_lock : out std_logic;
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db_i : in cpu_data_i_t;
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inst_o : out cpu_instruction_o_t;
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inst_i : in cpu_instruction_i_t;
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debug_o : out cpu_debug_o_t;
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debug_i : in cpu_debug_i_t;
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event_o : out cpu_event_o_t;
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event_i : in cpu_event_i_t);
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end component cpu;
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function loopback_bus(b : cpu_data_o_t) return cpu_data_i_t;
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end cpu2j0_pack;
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package body cpu2j0_pack is
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function loopback_bus(b : cpu_data_o_t) return cpu_data_i_t is
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variable r : cpu_data_i_t;
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begin
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r.ack := b.en;
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r.d := (others => '0');
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return r;
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end function loopback_bus;
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end cpu2j0_pack;
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