mirror of
https://github.com/j-core/j-core-ice40.git
synced 2026-03-03 10:06:04 +00:00
288 lines
11 KiB
VHDL
288 lines
11 KiB
VHDL
-- ******************************************************************
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-- ******************************************************************
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-- ******************************************************************
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-- This file is generated. Changing this file directly is probably
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-- not what you want to do. Any changes will be overwritten next time
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-- the generator is run.
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-- ******************************************************************
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-- ******************************************************************
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-- ******************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use work.cpu2j0_components_pack.all;
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use work.mult_pkg.all;
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use work.cpu2j0_pack.all;
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package decode_pack is
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type aluinx_sel_t is (SEL_XBUS, SEL_FC, SEL_ROTCL, SEL_ZERO);
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type aluiny_sel_t is (SEL_YBUS, SEL_IMM, SEL_R0);
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type cpu_decode_type_t is (SIMPLE, REVERSE, MICROCODE);
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type immval_t is (IMM_ZERO, IMM_P1, IMM_P2, IMM_P4, IMM_P8, IMM_P16, IMM_N16, IMM_N8, IMM_N2, IMM_N1, IMM_U_4_0, IMM_U_4_1, IMM_U_4_2, IMM_U_8_0, IMM_U_8_1, IMM_U_8_2, IMM_S_8_1, IMM_S_12_1, IMM_S_8_0);
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type instruction_plane_t is (NORMAL_INSTR, SYSTEM_INSTR);
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type mac_busy_t is (NOT_BUSY, EX_NOT_STALL, WB_NOT_STALL, EX_BUSY, WB_BUSY);
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type macin1_sel_t is (SEL_XBUS, SEL_ZBUS, SEL_WBUS);
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type macin2_sel_t is (SEL_YBUS, SEL_ZBUS, SEL_WBUS);
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type mem_addr_sel_t is (SEL_XBUS, SEL_YBUS, SEL_ZBUS);
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type mem_wdata_sel_t is (SEL_ZBUS, SEL_YBUS);
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type reg_sel_t is (SEL_R0, SEL_R15, SEL_RA, SEL_RB);
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type sr_sel_t is (SEL_PREV, SEL_WBUS, SEL_ZBUS, SEL_DIV0U, SEL_ARITH, SEL_LOGIC, SEL_INT_MASK, SEL_SET_T);
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type t_sel_t is (SEL_CLEAR, SEL_SET, SEL_SHIFT, SEL_CARRY);
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type xbus_sel_t is (SEL_IMM, SEL_REG, SEL_PC);
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type ybus_sel_t is (SEL_IMM, SEL_REG, SEL_MACH, SEL_MACL, SEL_PC, SEL_SR);
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type zbus_sel_t is (SEL_ARITH, SEL_LOGIC, SEL_SHIFT, SEL_MANIP, SEL_YBUS, SEL_WBUS);
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type operation_t is
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record
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plane : instruction_plane_t;
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code : std_logic_vector(15 downto 0);
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addr : std_logic_vector(7 downto 0);
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end record;
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type alu_ctrl_t is
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record
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manip : alumanip_t;
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inx_sel : aluinx_sel_t;
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iny_sel : aluiny_sel_t;
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end record;
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type arith_ctrl_t is
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record
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func : arith_func_t;
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ci_en : std_logic;
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sr : arith_sr_func_t;
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end record;
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type buses_ctrl_t is
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record
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x_sel : xbus_sel_t;
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y_sel : ybus_sel_t;
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z_sel : zbus_sel_t;
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imm_val : std_logic_vector(31 downto 0);
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end record;
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type func_ctrl_t is
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record
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alu : alu_ctrl_t;
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shift : shiftfunc_t;
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arith : arith_ctrl_t;
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logic_func : logic_func_t;
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logic_sr : logic_sr_func_t;
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end record;
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type instr_ctrl_t is
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record
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issue : std_logic;
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addr_sel : std_logic;
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end record;
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type mac_ctrl_t is
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record
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com1 : std_logic;
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wrmach : std_logic;
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wrmacl : std_logic;
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s_latch : std_logic;
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sel1 : macin1_sel_t;
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sel2 : macin2_sel_t;
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com2 : mult_state_t;
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end record;
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type mem_ctrl_t is
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record
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issue : std_logic;
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wr : std_logic;
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lock : std_logic;
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size : mem_size_t;
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addr_sel : mem_addr_sel_t;
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wdata_sel : mem_wdata_sel_t;
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end record;
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type pc_ctrl_t is
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record
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wr_z : std_logic;
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wrpr : std_logic;
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inc : std_logic;
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end record;
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type reg_ctrl_t is
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record
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num_x : regnum_t;
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num_y : regnum_t;
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num_z : regnum_t;
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num_w : regnum_t;
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wr_z : std_logic;
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wr_w : std_logic;
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end record;
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type sr_ctrl_t is
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record
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sel : sr_sel_t;
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t : t_sel_t;
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ilevel : std_logic_vector(3 downto 0);
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end record;
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type pipeline_ex_stall_t is
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record
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wrpc_z : std_logic;
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wrsr_z : std_logic;
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ma_issue : std_logic;
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wrpr_pc : std_logic;
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zbus_sel : zbus_sel_t;
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sr_sel : sr_sel_t;
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t_sel : t_sel_t;
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mem_addr_sel : mem_addr_sel_t;
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mem_wdata_sel : mem_wdata_sel_t;
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wrreg_z : std_logic;
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wrmach, wrmacl : std_logic;
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shiftfunc : shiftfunc_t;
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mulcom1 : std_logic;
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mulcom2 : mult_state_t;
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macsel1 : macin1_sel_t;
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macsel2 : macin2_sel_t;
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end record;
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type pipeline_ex_t is
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record
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imm_val : std_logic_vector(31 downto 0);
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xbus_sel : xbus_sel_t;
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ybus_sel : ybus_sel_t;
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regnum_z, regnum_x, regnum_y : regnum_t;
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alumanip : alumanip_t;
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aluinx_sel : aluinx_sel_t;
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aluiny_sel : aluiny_sel_t;
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arith_func : arith_func_t;
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arith_ci_en : std_logic;
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arith_sr_func : arith_sr_func_t;
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logic_func : logic_func_t;
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logic_sr_func : logic_sr_func_t;
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mac_busy : std_logic;
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ma_wr : std_logic;
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mem_lock : std_logic;
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mem_size : mem_size_t;
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end record;
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type pipeline_id_t is
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record
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incpc : std_logic;
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if_issue : std_logic;
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ifadsel : std_logic;
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end record;
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type pipeline_wb_stall_t is
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record
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mulcom1 : std_logic;
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wrmach, wrmacl : std_logic;
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wrreg_w, wrsr_w : std_logic;
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macsel1 : macin1_sel_t;
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macsel2 : macin2_sel_t;
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mulcom2 : mult_state_t;
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end record;
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type pipeline_wb_t is
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record
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regnum_w : regnum_t;
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mac_busy : std_logic;
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end record;
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type pipeline_t is
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record
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ex1 : pipeline_ex_t;
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ex1_stall : pipeline_ex_stall_t;
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wb1 : pipeline_wb_t;
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wb2 : pipeline_wb_t;
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wb3 : pipeline_wb_t;
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wb1_stall : pipeline_wb_stall_t;
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wb2_stall : pipeline_wb_stall_t;
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wb3_stall : pipeline_wb_stall_t;
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end record;
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component decode
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port (
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clk : in std_logic;
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enter_debug : in std_logic;
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event_i : in cpu_event_i_t;
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ibit : in std_logic_vector(3 downto 0);
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if_dr : in std_logic_vector(15 downto 0);
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if_stall : in std_logic;
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illegal_delay_slot : in std_logic;
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illegal_instr : in std_logic;
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mac_busy : in std_logic;
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mask_int : in std_logic;
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rst : in std_logic;
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slot : in std_logic;
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t_bcc : in std_logic;
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buses : out buses_ctrl_t;
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debug : out std_logic;
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event_ack : out std_logic;
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func : out func_ctrl_t;
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instr : out instr_ctrl_t;
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mac : out mac_ctrl_t;
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mem : out mem_ctrl_t;
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pc : out pc_ctrl_t;
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reg : out reg_ctrl_t;
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slp : out std_logic;
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sr : out sr_ctrl_t
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);
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end component;
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component decode_core
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port (
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clk : in std_logic;
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debug : in std_logic;
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delay_jump : in std_logic;
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dispatch : in std_logic;
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enter_debug : in std_logic;
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event_ack_0 : in std_logic;
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event_i : in cpu_event_i_t;
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ex : in pipeline_ex_t;
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ex_stall : in pipeline_ex_stall_t;
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ibit : in std_logic_vector(3 downto 0);
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id : in pipeline_id_t;
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if_dr : in std_logic_vector(15 downto 0);
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if_stall : in std_logic;
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ilevel_cap : in std_logic;
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illegal_delay_slot : in std_logic;
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illegal_instr : in std_logic;
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mac_busy : in std_logic;
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mac_stall_sense : in std_logic;
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maskint_next : in std_logic;
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p : in pipeline_t;
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rst : in std_logic;
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slot : in std_logic;
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t_bcc : in std_logic;
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event_ack : out std_logic;
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if_issue : out std_logic;
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ifadsel : out std_logic;
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ilevel : out std_logic_vector(3 downto 0);
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incpc : out std_logic;
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next_id_stall : out std_logic;
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op : out operation_t
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);
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end component;
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component decode_table
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port (
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clk : in std_logic;
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next_id_stall : in std_logic;
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op : in operation_t;
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t_bcc : in std_logic;
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debug : out std_logic;
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delay_jump : out std_logic;
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dispatch : out std_logic;
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event_ack_0 : out std_logic;
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ex : out pipeline_ex_t;
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ex_stall : out pipeline_ex_stall_t;
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id : out pipeline_id_t;
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ilevel_cap : out std_logic;
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mac_s_latch : out std_logic;
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mac_stall_sense : out std_logic;
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maskint_next : out std_logic;
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slp : out std_logic;
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wb : out pipeline_wb_t;
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wb_stall : out pipeline_wb_stall_t
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);
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end component;
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function predecode_rom_addr (code : std_logic_vector(15 downto 0)) return std_logic_vector;
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function check_illegal_delay_slot (code : std_logic_vector(15 downto 0)) return std_logic;
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function check_illegal_instruction (code : std_logic_vector(15 downto 0)) return std_logic;
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type decode_core_reg_t is
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record
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maskint : std_logic;
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delay_slot : std_logic;
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id_stall : std_logic;
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instr_seq_zero : std_logic;
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op : operation_t;
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ilevel : std_logic_vector(3 downto 0);
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end record;
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constant DEC_CORE_RESET : decode_core_reg_t := (maskint => '0', delay_slot => '0', id_stall => '0', instr_seq_zero => '0', op => (plane => SYSTEM_INSTR, code => x"0300", addr => x"01"), ilevel => x"0");
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-- Reset vector specific to the microcode ROM. Uses a different starting addr.
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constant DEC_CORE_ROM_RESET : decode_core_reg_t := (maskint => '0', delay_slot => '0', id_stall => '0', instr_seq_zero => '0', op => (plane => SYSTEM_INSTR, code => x"0300", addr => x"da"), ilevel => x"0");
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type system_instr_t is (BREAK_I, ERROR_I, GENERAL_ILLEGAL_I, INTERRUPT_I, RESET_CPU_I, SLOT_ILLEGAL_I);
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type system_instr_addr_array is array (system_instr_t range <>) of std_logic_vector(7 downto 0);
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constant system_instr_rom_addrs : system_instr_addr_array := (BREAK_I => x"f2", ERROR_I => x"e9", GENERAL_ILLEGAL_I => x"c9", INTERRUPT_I => x"e0", RESET_CPU_I => x"d9", SLOT_ILLEGAL_I => x"d1");
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type system_instr_code_array is array (system_instr_t range <>) of std_logic_vector(11 downto 8);
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constant system_instr_codes : system_instr_code_array := (BREAK_I => x"2", ERROR_I => x"1", GENERAL_ILLEGAL_I => x"7", INTERRUPT_I => x"0", RESET_CPU_I => x"3", SLOT_ILLEGAL_I => x"6");
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type system_event_code_array is array (cpu_event_cmd_t range <>) of std_logic_vector(11 downto 8);
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constant system_event_codes : system_event_code_array := (INT => x"0", ERR => x"1", BREAK => x"2", RST => x"3");
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type system_event_instr_array is array (cpu_event_cmd_t range <>) of system_instr_t;
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constant system_event_instrs : system_event_instr_array := (INT => INTERRUPT_I, ERR => ERROR_I, BREAK => BREAK_I, RST => RESET_CPU_I);
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end;
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