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The BIOS patch functionality changes will be deferred to a later version.

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kalymos
2026-02-23 19:21:29 +01:00
parent ab6d029d48
commit 10d2310103
4 changed files with 145 additions and 462 deletions
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269
PSNee/BIOS_patching.h
View File

@@ -1,192 +1,118 @@
#pragma once
#ifdef BIOS_PATCH
uint8_t current_pulses = 0;
volatile uint8_t pulse_counter = 0;
volatile uint8_t patch_done = 0;
#ifdef TEST_BIOS
void Bios_Patching() {
PIN_DX_INPUT;
//PIN_DX_LOW;
#ifdef INTERRUPT_RISING
cli(); // Disable interrupts for timing integrity
/*
* PHASE 1: Signal Stabilization & Alignment
* Synchronizes the MCU with the PS1 startup state (Cold Boot vs Reset).
*/
if (PIN_AX_READ != 0) { // Case: Power-on / Line high (---__-_-_)
while (PIN_AX_READ != 0); // Wait for falling edge
while (PIN_AX_READ == 0); // Sync on first clean rising edge
} else { // Case: Reset / Line low (_____-_-_)
while (PIN_AX_READ == 0); // Wait for rising edge
ISR(PIN_AX_INTERRUPT_VECTOR) {
/*
* PHASE 3: Pulse Counting (Inside ISR)
* The hardware Interrupt Service Routine (ISR) now takes over.
* It counts the exact number of incoming pulses on PIN_AX until it
* matches the PULSE_COUNT value.
*/
pulse_counter++;
if (pulse_counter == PULSE_COUNT){ // If pulse_counter reaches the value defined by PULSE_COUNT
/*
* PHASE 4: Precision Bit Alignment
* Once the PULSE_COUNT is reached, a micro-delay (BIT_OFFSET) is applied.
* This shifts the timing from the clock edge to the exact bit position
* within the data stream that needs modification.
*/
_delay_us(BIT_OFFSET);
/*
* PHASE 5: Data Bus Overdrive (The Patch)
* Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit.
* This effectively overwrites the BIOS data on-the-fly
* before reverting the pin to INPUT to release the bus.
*/
PIN_DX_OUTPUT;
_delay_us (OVERRIDE);
PIN_DX_INPUT;
PIN_AX_INTERRUPT_DISABLE;
pulse_counter = 0;
patch_done = 1; // patch_done is set to 1, indicating that the first patch is completed.
}
}
/*
* PHASE 2: Address Bus Window Alignment
* Bypassing initial boot routines to reach one window with a
* known "idle gap" in the address bus activity, positioned
* immediately before the target memory-access cycle.
* BOOT_OFFSET: |----//----------|
* AX: ___-_-_//-_-_-________________-_-_
*/
_delay_ms(BOOT_OFFSET);
PIN_LED_ON;
void Bios_Patching(){
/*
* PHASE 3: Edge Trigger
* Capture the moment AX go HIGH.
* Edge Triger: |
* AX: _-_-_-_-_-________________-_-_-_-_-_-__
*/
#ifdef LOW_TRIGGER
while (PIN_AX_READ);
#else
while (! PIN_AX_READ);
#endif
/*
* PHASE 1: Signal Stabilization & Alignment
* Detects the startup state (Cold Boot vs. Reset).
* If the line is already HIGH (Cold Boot), we wait for a full LOW-to-HIGH transition
* to ensure we are aligned with the start of a clean clock cycle.
*/
/*
* PHASE 4: Precision Bit Alignment
* Delay to shift from AX address edge to the DX data bit.
* BIT_OFFSET: |-------//-----|
* AX: _-_-_-_-_-________________-_-_-_-_//_-_-_-_
*/
_delay_us(BIT_OFFSET);
/*
* PHASE 5: Data Bus Overdrive (The Patch)
* Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit.
* This effectively overwrites the BIOS data on-the-fly
* before reverting the pin to INPUT to release the bus.
*/
PIN_DX_OUTPUT; // Force line (Low/High-Z override)
_delay_us(OVERRIDE);
PIN_DX_INPUT; // Release bus immediately
PIN_LED_OFF;
sei(); // Restore global interrupts
patch_done = 1;
}
if (PIN_AX_READ != 0) { // Case: Power-on / Line high (---__-_-_)
while (PIN_AX_READ != 0); // Wait for falling edge
while (PIN_AX_READ == 0); // Wait for next rising edge to sync
}
else { // Case: Reset / Line low (_____-_-_)
while (PIN_AX_READ == 0); // Wait for the very first rising edge
}
/*
* PHASE 2: Reaching the Target Memory Window
* We introduce a strategic delay (BOOT_OFFSET) to skip initial noise.
* This points the execution to a known idle gap in the
* address range calls before the critical data appears.
* DELAY: |---//-----|
* AX: -_-_//-_-_________-_-_-_
*/
_delay_ms(BOOT_OFFSET);
// Armed for hardware detection
PIN_AX_INTERRUPT_RISING;
PIN_AX_INTERRUPT_ENABLE;
while (patch_done != 1); // Wait for the first stage of the patch to complete:
}
#endif
#ifdef HIGH_PATCH_A
#ifdef INTERRUPT_FALLING
ISR(PIN_AY_INTERRUPT_VECTOR){
ISR(PIN_AX_INTERRUPT_VECTOR) {
pulse_counter++;
if (pulse_counter == PULSE_COUNT_2)
{
_delay_us (BIT_OFFSET_2);
PIN_DX_OUTPUT;
_delay_us (OVERRIDE_2);
PIN_DX_INPUT;
PIN_AY_INTERRUPT_DISABLE;
if (pulse_counter == PULSE_COUNT){
_delay_us (BIT_OFFSET);
PIN_DX_OUTPUT;
_delay_us (OVERRIDE);
PIN_DX_INPUT;
patch_done = 2;
PIN_AX_INTERRUPT_DISABLE;
pulse_counter = 0;
patch_done = 1;
}
}
void Bios_Patching(){
PIN_DX_INPUT;
cli(); // Disable interrupts for timing integrity
if (PIN_AX_READ != 0)
{
if (PIN_AX_READ != 0) {
while (PIN_AX_READ != 0);
while (PIN_AX_READ == 0);
while (PIN_AX_READ == 0);
}
else
{
else {
while (PIN_AX_READ == 0);
}
_delay_ms(BOOT_OFFSET);
PIN_LED_ON;
while (! PIN_AX_READ);
_delay_us(BIT_OFFSET);
PIN_DX_SET;
PIN_DX_OUTPUT; // Force line (Low/High-Z override)
_delay_us(OVERRIDE);
PIN_DX_CLEAR;
PIN_DX_INPUT; // Release bus immediately
PIN_LED_OFF;
sei(); // Restore global interrupts
_delay_ms(BOOT_OFFSET);
PIN_LED_OFF;
_delay_ms(FOLLOWUP_OFFSET);
PIN_AY_INTERRUPT_RISING;
PIN_AY_INTERRUPT_ENABLE;
while (patch_done != 2);
PIN_AX_INTERRUPT_FALLING;
PIN_AX_INTERRUPT_ENABLE;
while (patch_done != 1);
}
#endif
#ifdef HIGH_PATCH_B
void Bios_Patching(){
PIN_DX_INPUT;
cli(); // Disable interrupts for timing integrity
if (PIN_AX_READ != 0)
{
while (PIN_AX_READ != 0);
while (PIN_AX_READ == 0);
}
else
{
while (PIN_AX_READ == 0);
}
_delay_ms(BOOT_OFFSET);
//PIN_LED_ON;
while (! PIN_AX_READ);
_delay_us(BIT_OFFSET);
PIN_DX_SET;
PIN_DX_OUTPUT; // Force line (Low/High-Z override)
_delay_us(OVERRIDE);
PIN_DX_CLEAR;
PIN_DX_INPUT; // Release bus immediately
PIN_LED_OFF;
sei(); // Restore global interrupts
//PIN_LED_OFF;
PIN_LED_ON;
while (PIN_AY_READ != 0);
_delay_ms(FOLLOWUP_OFFSET);
while (PIN_AY_READ);
_delay_us (BIT_OFFSET_2);
PIN_DX_OUTPUT;
_delay_us (OVERRIDE_2);
PIN_DX_INPUT;
PIN_LED_OFF;
}
#endif
#ifdef INTERRUPT_RISING_HIGH_PATCH
ISR(PIN_AX_INTERRUPT_VECTOR) {
pulse_counter++;
if (pulse_counter == PULSE_COUNT){
@@ -197,66 +123,53 @@
PIN_DX_CLEAR;
PIN_DX_INPUT;
PIN_AX_INTERRUPT_DISABLE;
pulse_counter = 0;
patch_done = 1;
}
}
ISR(PIN_AY_INTERRUPT_VECTOR){
pulse_counter++;
if (pulse_counter == PULSE_COUNT_2)
{
if (pulse_counter == PULSE_COUNT_2) {
_delay_us (BIT_OFFSET_2);
PIN_DX_OUTPUT;
_delay_us (OVERRIDE_2);
PIN_DX_INPUT;
PIN_AY_INTERRUPT_DISABLE;
patch_done = 2;
}
}
void Bios_Patching(){
if (PIN_AX_READ != 0)
{
if (PIN_AX_READ != 0) {
while (PIN_AX_READ != 0);
while (PIN_AX_READ == 0);
}
else
{
else {
while (PIN_AX_READ == 0);
}
_delay_ms(BOOT_OFFSET);
PIN_AX_INTERRUPT_RISING;
PIN_AX_INTERRUPT_ENABLE;
PIN_AX_INTERRUPT_ENABLE;
while (patch_done != 1);
while (PIN_AY_READ != 0);
while (PIN_AY_READ != 0);
_delay_ms(FOLLOWUP_OFFSET);
PIN_LED_ON;
PIN_AY_INTERRUPT_RISING;
PIN_AY_INTERRUPT_ENABLE;
PIN_AY_INTERRUPT_ENABLE;
while (patch_done != 2);
PIN_LED_OFF;
}
#endif
#endif

28
PSNee/MCU.h
View File

@@ -124,19 +124,6 @@ static inline void optimizePeripherals(void) {
// Define the clock speed for the microcontroller
#define F_CPU 16000000L
// Clear the timer count register (TCNT0)
//#define TIMER_TCNT_CLEAR TCNT0 = 0x00 // TCNT0 - Timer/Counter Register, clears the timer count
// Set OCR0A to achieve a 100KHz clock frequency
//#define SET_OCROA_DIV OCR0A = 159; // OCR0A – Output Compare Register A, 100KHz clock generation, 0x10011111
// Configure Timer/Counter 0 for CTC mode and enable the clock source
//#define SET_TIMER_TCCROA TCCR0A |= (1 << WGM01); // TCCR0A – Timer/Counter Control Register A, enable CTC mode (WGM01)
//#define SET_TIMER_TCCROB TCCR0B |= (1 << CS00); // TCCR0B – Timer/Counter Control Register B, set clock source to I/O clock
//Waveform Generation Mode, Mode 2 CTC
// Interrupt vector for timer compare match event
//#define CTC_TIMER_VECTOR TIMER0_COMPA_vect //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
#include <stdint.h>
#include <stdbool.h>
#include <avr/io.h>
@@ -148,10 +135,6 @@ static inline void optimizePeripherals(void) {
#define GLOBAL_INTERRUPT_ENABLE SREG |= (1 << 7) // Set the I-bit (bit 7) in the Status Register to enable global interrupts
#define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1 << 7) // Clear the I-bit (bit 7) in the Status Register to disable global interrupts
// Enable/Disable timer interrupts
//#define TIMER_INTERRUPT_ENABLE TIMSK0 |= (1 << OCIE0A) // Enable interrupt on Timer0 Compare Match A
//#define TIMER_INTERRUPT_DISABLE TIMSK0 &= ~(1 << OCIE0A) // Disable interrupt on Timer0 Compare Match A
// Main pin configuration for input and output
// Define the main pins as inputs
@@ -249,11 +232,7 @@ static inline void optimizePeripherals(void) {
#ifdef ATmega32U4_16U4
#define F_CPU 16000000L
// #define TIMER_TCNT_CLEAR TCNT0 = 0x00;
// #define SET_OCROA_DIV OCR0A = 159;
// #define SET_TIMER_TCCROA TCCR0A |= (1 << WGM01);
// #define SET_TIMER_TCCROB TCCR0B |= (1 << CS00);
// #define CTC_TIMER_VECTOR TIMER0_COMPA_vect
#include <stdint.h>
#include <stdbool.h>
@@ -263,11 +242,10 @@ static inline void optimizePeripherals(void) {
#include <util/delay.h>
// Globale interrupt seting
// #define GLOBAL_INTERRUPT_ENABLE SREG |= (1 << 7)
#define GLOBAL_INTERRUPT_ENABLE SREG |= (1 << 7)
#define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1 << 7)
// #define TIMER_INTERRUPT_ENABLE TIMSK0 |= (1 << OCIE0A)
// #define TIMER_INTERRUPT_DISABLE TIMSK0 &= ~(1 << OCIE0A)
// Handling the main pins

161
PSNee/PSNee.ino
View File

@@ -19,12 +19,11 @@
SCPH model number // region code | region
-------------------------------------------------------------------------------------------------*/
//#define SCPH_xxxx // | Universal.
//#define SCPH_xxx1 // NTSC U/C | America.
//#define SCPH_xxx2 // PAL | Europ.
//#define SCPH_xxx3 // NTSC J | Asia.
//#define SCPH_xxxx // Universal
//#define SCPH_5903 // NTSC J | Asia VCD:
//#define SCPH_5903 // NTSC J | Asia VCD.
// Models that require a BIOS patch.
@@ -242,28 +241,6 @@ void captureSubQ(void) {
* isDataSector Boolean flag indicating if the current sector contains data.
**************************************************************************************/
// void logic_SCPH_5903(uint8_t isDataSector) {
// // Identify VCD Lead-In: Specific SCBUF patterns (0xA0/A1/A2) with sub-mode 0x02
// uint8_t isVcdLeadIn = isDataSector && scbuf[1] == 0x00 && scbuf[6] == 0x00 &&
// (scbuf[2] == 0xA0 || scbuf[2] == 0xA1 || scbuf[2] == 0xA2) &&
// (scbuf[3] == 0x02);
// // Identify PSX Lead-In: Same SCBUF patterns but different sub-mode (!= 0x02)
// uint8_t isPsxLeadIn = isDataSector && scbuf[1] == 0x00 && scbuf[6] == 0x00 &&
// (scbuf[2] == 0xA0 || scbuf[2] == 0xA1 || scbuf[2] == 0xA2) &&
// (scbuf[3] != 0x02);
// if (isPsxLeadIn) {
// hysteresis++;
// }
// else if (hysteresis > 0 && !isVcdLeadIn &&
// ((scbuf[0] == 0x01 || isDataSector) && scbuf[1] == 0x00 && scbuf[6] == 0x00)) {
// hysteresis++; // Maintain/Increase confidence for valid non-VCD sectors
// }
// else if (hysteresis > 0) {
// hysteresis--; // Patterns stop matching
// }
// }
void logic_SCPH_5903(uint8_t isDataSector) {
// Optimization: Pre-check common markers (1 and 6) to save CPU cycles
@@ -303,23 +280,6 @@ void logic_SCPH_5903(uint8_t isDataSector) {
******************************************************************************************/
// void logic_Standard(uint8_t isDataSector) {
// // Detect specific Lead-In patterns
// if ((isDataSector && scbuf[1] == 0x00 && scbuf[6] == 0x00) &&
// (scbuf[2] == 0xA0 || scbuf[2] == 0xA1 || scbuf[2] == 0xA2 ||
// (scbuf[2] == 0x01 && (scbuf[3] >= 0x98 || scbuf[3] <= 0x02)))) {
// hysteresis++;
// }
// // Maintain confidence if general valid sector markers are found
// else if (hysteresis > 0 &&
// ((scbuf[0] == 0x01 || isDataSector) && scbuf[1] == 0x00 && scbuf[6] == 0x00)) {
// hysteresis++;
// }
// else if (hysteresis > 0) {
// hysteresis--;
// }
// }
void logic_Standard(uint8_t isDataSector) {
// Optimization: Check common markers once (scbuf[1] and scbuf[6])
if (scbuf[1] == 0x00 && scbuf[6] == 0x00) {
@@ -441,111 +401,10 @@ void performInjectionSequence(uint8_t injectSCEx) {
#endif
}
// void performInjectionSequence(uint8_t injectSCEx) {
// // 44-bit SCEx strings for Japan Asia, USA, and Europe
// static const uint8_t allRegionsSCEx[3][6] = {
// { 0b01011001, 0b11001001, 0b01001011, 0b01011101, 0b11011010, 0b00000010 }, // NTSC-J SCEI SCPH-xxx0 SCPH-xxx3
// { 0b01011001, 0b11001001, 0b01001011, 0b01011101, 0b11111010, 0b00000010 }, // NTSC-U/C SCEA SCPH-xxx1
// { 0b01011001, 0b11001001, 0b01001011, 0b01011101, 0b11101010, 0b00000010 } // PAL SCEE SCPH-xxx2
// };
// // if (hysteresis < HYSTERESIS_MAX) return;
// hysteresis = 11;
// #ifdef LED_RUN
// PIN_LED_ON;
// #endif
// // Pin initialization
// PIN_DATA_OUTPUT;
// PIN_DATA_CLEAR;
// if (!wfck_mode) {
// PIN_WFCK_OUTPUT;
// PIN_WFCK_CLEAR;
// }
// _delay_ms(DELAY_BETWEEN_INJECTIONS);
// // Injection loop (3 cycles)
// for (uint8_t i = 0; i < 3; i++) {
// // Mode 3: cycles through all regions; Others: stay on fixed region
// uint8_t regionIndex = (injectSCEx == 3) ? i : injectSCEx;
// const uint8_t* ByteSet = allRegionsSCEx[regionIndex];
// for (uint8_t bit_counter = 0; bit_counter < 44; bit_counter++) {
// // Bit-level extraction:
// // 1. bit_counter >> 3 identifies the byte index (integer division by 8).
// // 2. bit_counter & 0x07 identifies the bit position within that byte (modulo 8).
// // 3. Right-shift and mask (& 0x01) isolates the target bit for injection.
// uint8_t currentByte = ByteSet[bit_counter >> 3];
// uint8_t currentBit = (currentByte >> (bit_counter & 0x07)) & 0x01;
// if (!wfck_mode) {
// // LOGIC GATE MODE (Old boards)
// if (currentBit == 0) {
// PIN_DATA_OUTPUT;
// PIN_DATA_CLEAR;
// }
// else {
// PIN_DATA_INPUT; // High Impedance = 1
// }
// _delay_us(DELAY_BETWEEN_BITS);
// }
// else {
// // WFCK MODULATION (Newer boards / PU-18+)
// // PIN_DATA_OUTPUT;
// if (currentBit == 0) {
// PIN_DATA_CLEAR;
// _delay_us(DELAY_BETWEEN_BITS);
// }
// else {
// // Synchronize injection with WFCK clock edges
// uint8_t count = 30;
// uint8_t last_wfck = PIN_WFCK_READ;
// while (count > 0) {
// uint8_t current_wfck = PIN_WFCK_READ;
// if (current_wfck != last_wfck) {
// if (current_wfck) {
// PIN_DATA_SET; count--;
// }
// else {
// PIN_DATA_CLEAR;
// }
// last_wfck = current_wfck;
// }
// }
// }
// }
// }
// // Inter-string silence
// PIN_DATA_OUTPUT;
// PIN_DATA_CLEAR;
// _delay_ms(DELAY_BETWEEN_INJECTIONS);
// }
// // Cleanup: Set pins to High-Z (Safe mode)
// if (!wfck_mode) {
// PIN_WFCK_INPUT;
// PIN_DATA_INPUT;
// }
// #ifdef LED_RUN
// PIN_LED_OFF;
// #endif
// }
void Init() {
#if defined(ATmega328_168)
optimizePeripherals();
optimizePeripherals();
#endif
#ifdef LED_RUN
@@ -564,7 +423,7 @@ void Init() {
#endif
#ifdef LED_RUN
//PIN_LED_ON;
PIN_LED_ON;
#endif
if (Flag_Switch == 0) {
@@ -572,7 +431,7 @@ void Init() {
}
#ifdef LED_RUN
//PIN_LED_OFF;
PIN_LED_OFF;
#endif
#endif
@@ -596,14 +455,14 @@ int main() {
#ifdef SCPH_5903
currentLogic = logic_SCPH_5903;
#else
currentLogic = logic_Standard;
currentLogic = logic_SCPH_5903;
#else
currentLogic = logic_Standard;
#endif
board_detection();
#if defined(PSNEE_DEBUG_SERIAL_MONITOR)
Debug_Log(lows, wfck_mode);
Debug_Log(lows, wfck_mode);
#endif
while (1) {
@@ -631,12 +490,10 @@ int main() {
// Execute selected logic through function pointer
currentLogic(isDataSector);
if (hysteresis >= HYSTERESIS_MAX) {
performInjectionSequence(INJECT_SCEx);
}
#if defined(PSNEE_DEBUG_SERIAL_MONITOR)
Debug_Inject();
#endif

149
PSNee/settings.h
View File

@@ -19,163 +19,98 @@
/*------------------------------------------------------------------------------------------------
Specific parameter section for BIOS patches
------------------------------------------------------------------------------------------------*/
// Results of the maximum values
// tested with an Atmega328P
// #ifdef SCPH_102
// #define BIOS_PATCH
// #define INTERRUPT_RISING
// #define BOOT_OFFSET 83.9
// #define PULSE_COUNT 48 !!! -1
// #define BIT_OFFSET 2.75
// #define OVERRIDE 0.2
// #endif
// #ifdef SCPH_100
// #define BIOS_PATCH
// #define INTERRUPT_RISING
// #define BOOT_OFFSET 83.9 //83.72 - 84.15
// #define PULSE_COUNT 47
// #define BIT_OFFSET 2.75 //2.63 - 2.87
// #define OVERRIDE 0.2
// #endif
#ifdef SCPH_102
#ifdef SCPH_102
#define BIOS_PATCH
#define TEST_BIOS
#define BOOT_OFFSET 83.9 // Stabilization window (ms)
#define BIT_OFFSET 225.6 // Precision data alignment (us)
#define OVERRIDE 0.2 // DX injection width (us)
#define INTERRUPT_RISING
#define BOOT_OFFSET 83.9
#define PULSE_COUNT 48
#define BIT_OFFSET 2.75
#define OVERRIDE 0.2
#endif
#ifdef SCPH_100
#define BIOS_PATCH
#define TEST_BIOS
#define BOOT_OFFSET 83.9 // Stabilization window (ms)
#define BIT_OFFSET 225.6 // Precision data alignment (us)
#define OVERRIDE 0.2 // DX injection width (us)
#define INTERRUPT_RISING
#define BOOT_OFFSET 83.9 //83.72 - 84.15
#define PULSE_COUNT 48
#define BIT_OFFSET 2.75 //2.63 - 2.87
#define OVERRIDE 0.2
#endif
#ifdef SCPH_7500_9000
#define BIOS_PATCH
#define TEST_BIOS
#define BOOT_OFFSET 75.2
#define BIT_OFFSET 71.5
#define INTERRUPT_RISING
#define BOOT_OFFSET 75.2 //74.95 - 75.55
#define PULSE_COUNT 16
#define BIT_OFFSET 2.8
#define OVERRIDE 0.2
#endif
#ifdef SCPH_7000
#define BIOS_PATCH
#define TEST_BIOS
#define BOOT_OFFSET 75.2
#define BIT_OFFSET 71.5
#define INTERRUPT_RISING
#define BOOT_OFFSET 75.2 //75.3
#define PULSE_COUNT 16
#define BIT_OFFSET 2.8
#define OVERRIDE 0.2
#endif
#ifdef SCPH_5500
#define BIOS_PATCH
#define TEST_BIOS
#define LOW_TRIGGER
#define INTERRUPT_FALLING
#define BOOT_OFFSET 76.07 //75.99 - 76.14
#define BIT_OFFSET 95.6
#define PULSE_COUNT 21
#define BIT_OFFSET 2.8
#define OVERRIDE 0.2
#endif
#ifdef SCPH_5000
#define BIOS_PATCH
#define TEST_BIOS
#define LOW_TRIGGER
#define INTERRUPT_FALLING
#define BOOT_OFFSET 75.2 //75.12 - 75.27
#define BIT_OFFSET 95.65
#define OVERRIDE 0.2
#define PULSE_COUNT 21
#define BIT_OFFSET 2.8 //2.7 - 2.85
#define OVERRIDE 0.1
#endif
#ifdef SCPH_3500
#define BIOS_PATCH
#define TEST_BIOS
#define LOW_TRIGGER
#define INTERRUPT_FALLING
#define BOOT_OFFSET 75.2 //75.12 - 75.27
#define BIT_OFFSET 95.4
#define PULSE_COUNT 21
#define BIT_OFFSET 2.75 //2.65 - 2.85
#define OVERRIDE 0.2
#endif
// #ifdef SCPH_3000
// #define BIOS_PATCH
// #define HIGH_PATCH_A
// #define BOOT_OFFSET 82.9 //82.65 - 83.26
// #define BIT_OFFSET 283.25
// #define OVERRIDE 0.15
// #define HIGH_PATCH
// #define FOLLOWUP_OFFSET 253.3
// #define PULSE_COUNT_2 43
// #define BIT_OFFSET_2 2.88
// #define OVERRIDE_2 0.15
// #endif
#ifdef SCPH_3000
#define BIOS_PATCH
#define HIGH_PATCH_B
#define BOOT_OFFSET 82.9 //82.65 - 83.26
#define BIT_OFFSET 283.25
#define INTERRUPT_RISING_HIGH_PATCH
#define BOOT_OFFSET 82.9 //82.65 - 83.26
#define PULSE_COUNT 60
#define BIT_OFFSET 2.7 //2.58 - 2.8
#define OVERRIDE 0.15
#define HIGH_PATCH
#define FOLLOWUP_OFFSET 253.3
#define BIT_OFFSET_2 201.8
#define FOLLOWUP_OFFSET 253.3
#define PULSE_COUNT_2 43
#define BIT_OFFSET_2 2.88
#define OVERRIDE_2 0.15
#endif
// #ifdef SCPH_3000
// #define BIOS_PATCH
// #define INTERRUPT_RISING_HIGH_PATCH
// #define BOOT_OFFSET 82.9 //82.65 - 83.26
// #define PULSE_COUNT 60
// #define BIT_OFFSET 2.7 //2.58 - 2.8
// #define OVERRIDE 0.15
// #define HIGH_PATCH
// #define FOLLOWUP_OFFSET 253.3
// #define PULSE_COUNT_2 43
// #define BIT_OFFSET_2 2.88
// #define OVERRIDE_2 0.15
// #endif
// #ifdef SCPH_1000
// #define BIOS_PATCH
// #define INTERRUPT_RISING_HIGH_PATCH
// #define BOOT_OFFSET 82.9 // 82.63 - 83.26
// #define PULSE_COUNT 92
// #define BIT_OFFSET 2.65 // 2.58 - 2.75
// #define OVERRIDE 0.15
// #define HIGH_PATCH
// #define FOLLOWUP_OFFSET 272.8
// #define PULSE_COUNT_2 71
// #define BIT_OFFSET_2 2.88
// #define OVERRIDE_2 0.15
// #endif
// #ifdef SCPH_1000
// #define BIOS_PATCH
// #define HIGH_PATCH_A
// #define BOOT_OFFSET 82.9 // 82.63 - 83.26
// #define BIT_OFFSET 437.1 // 2.58 - 2.75
// #define OVERRIDE 0.15
// #define HIGH_PATCH
// #define FOLLOWUP_OFFSET 272.8
// #define PULSE_COUNT_2 71
// #define BIT_OFFSET_2 2.88
// #define OVERRIDE_2 0.15
// #endif
#ifdef SCPH_1000
#define BIOS_PATCH
#define HIGH_PATCH_B
#define INTERRUPT_RISING_HIGH_PATCH
#define BOOT_OFFSET 82.9 // 82.63 - 83.26
#define BIT_OFFSET 437.1 // 2.58 - 2.75
#define PULSE_COUNT 92
#define BIT_OFFSET 2.65 // 2.58 - 2.75
#define OVERRIDE 0.15
#define HIGH_PATCH
#define FOLLOWUP_OFFSET 272.8
#define BIT_OFFSET_2 336.05
#define PULSE_COUNT_2 71
#define BIT_OFFSET_2 2.88
#define OVERRIDE_2 0.15
#endif