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BIOS patch simplification

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Removal of ISR and reduction of code in the BIOS patch, for improved portability and robustness.

For now it is only available for the SCPH-100 and 102.
This commit is contained in:
kalymos
2026-02-16 20:47:07 +01:00
parent fc86f8b951
commit 64539aac03
3 changed files with 39 additions and 36 deletions
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43
PSNee/BIOS_patching.h
View File

@@ -19,49 +19,46 @@
* PHASE 1: Signal Stabilization & Alignment
* Synchronizes the MCU with the PS1 startup state (Cold Boot vs Reset).
*/
if (PIN_AX_READ != 0) {
if (PIN_AX_READ != 0) { // Case: Power-on / Line high (---__-_-_)
while (PIN_AX_READ != 0); // Wait for falling edge
while (PIN_AX_READ == 0); // Sync on first clean rising edge
} else {
} else { // Case: Reset / Line low (_____-_-_)
while (PIN_AX_READ == 0); // Wait for rising edge
}
/*
* PHASE 2: Address Bus Window Alignment
* Bypassing initial boot routines to reach the target memory-access cycle.
* Bypassing initial boot routines to reach one window with a
* known "idle gap" in the address bus activity, positioned
* immediately before the target memory-access cycle.
* BOOT_OFFSET: |----//----------|
* AX: ___-_-_//-_-_-________________-_-_
*/
_delay_ms(BOOT_OFFSET);
PIN_LED_ON;
/*
* PHASE 3: Zero-Jitter Pulse Counting (Falling Edge Trigger)
* Optimized to capture the exact moment AX returns to LOW on the 48th pulse.
* PHASE 3: Edge Trigger
* Capture the moment AX go HIGH.
* Edge Triger: |
* AX: _-_-_-_-_-________________-_-_-_-_-_-__
*/
while (current_pulses < PULSE_COUNT) {
// 1. Ultra-fast Rising Edge detection
while (!(PIND & (1 << 2)));
current_pulses++;
// 2. Falling Edge detection
// This line is critical: the CPU remains "locked" here as long as the pulse is HIGH.
while (PIND & (1 << 2));
// On the PULSE_COUNT iteration, the loop exits IMMEDIATELY after the signal falls.
}
while (! PIN_AX_READ);
/*
* PHASE 4: Precision Bit Alignment
* Strategic delay to shift from AX address edge to the DX data bit.
* Delay to shift from AX address edge to the DX data bit.
* BIT_OFFSET: |-------//-----|
* AX: _-_-_-_-_-________________-_-_-_-_//_-_-_-_
*/
_delay_us(BIT_OFFSET);
/*
* PHASE 5: Data Bus Overdrive (The Patch)
* Overwriting the 0.2us pulse on the DX line.
* Direct register access (Psnee v8.7 macros) ensures instantaneous execution.
*/
* PHASE 5: Data Bus Overdrive (The Patch)
* Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit.
* This effectively overwrites the BIOS data on-the-fly
* before reverting the pin to INPUT to release the bus.
*/
PIN_DX_OUTPUT; // Force line (Low/High-Z override)
_delay_us(OVERRIDE);
PIN_DX_INPUT; // Release bus immediately

4
PSNee/PSNee.ino
View File

@@ -43,8 +43,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
| Adres pin |
SCPH model number // Data pin | 32-pin BIOS | 40-pin BIOS | BIOS version
-------------------------------------------------------------------------------------------------*/
//#define SCPH_102 // DX - D0 | AX - A7 | | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5
#define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B
#define SCPH_102 // DX - D0 | AX - A7 | | 4.4e - CRC 0BAD7EA9, 4.5e -CRC 76B880E5
//#define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B
//#define SCPH_7500_9000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0
//#define SCPH_7000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 Enables hardware support for disabling BIOS patching.
//#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C

28
PSNee/settings.h
View File

@@ -24,14 +24,14 @@
// tested with an Atmega328P
#ifdef SCPH_102
#define BIOS_PATCH
#define INTERRUPT_RISING
#define BOOT_OFFSET 83.9
#define PULSE_COUNT 48
#define BIT_OFFSET 2.75
#define OVERRIDE 0.2
#endif
// #ifdef SCPH_102
// #define BIOS_PATCH
// #define INTERRUPT_RISING
// #define BOOT_OFFSET 83.9
// #define PULSE_COUNT 48 !!! -1
// #define BIT_OFFSET 2.75
// #define OVERRIDE 0.2
// #endif
// #ifdef SCPH_100
// #define BIOS_PATCH
@@ -42,14 +42,20 @@
// #define OVERRIDE 0.2
// #endif
#ifdef SCPH_102
#define BIOS_PATCH
#define TEST_BIOS
#define BOOT_OFFSET 83.9 // Stabilization window (ms)
#define BIT_OFFSET 225.6 // Precision data alignment (us)
#define OVERRIDE 0.2 // DX injection width (us)
#endif
#ifdef SCPH_100
#define BIOS_PATCH
#define TEST_BIOS
#define BOOT_OFFSET 83.9 // Stabilization window (ms)
#define PULSE_COUNT 47 // Targeted AX address cycles
#define BIT_OFFSET 3.6 // Precision data alignment (us) 3.9 - 3.98
#define OVERRIDE 0.25 // DX injection width (us)
#define BIT_OFFSET 225.6 // Precision data alignment (us)
#define OVERRIDE 0.2 // DX injection width (us)
#endif
#ifdef SCPH_7500_9000