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coment MUC
This commit is contained in:
kalymos
@@ -1,18 +1,117 @@
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//Configuring the clock speed and associated registers. F_CPU / (TCCR0B |= (1<<CS00) *(OCR0A = 159 +1) = 16000000 /(0 * (160)) = 100KHz
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// *****************************************************************************************************************
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// Configuration for different microcontrollers (MUC) to ensure compatibility with the code:
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// - Defines the clock speed, timers, and interrupts for each MUC.
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// - Configures I/O pins for data, clocks, and switches according to the requirements.
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// - Enables pull-up resistors on input pins where needed.
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// - Manages external interrupts and LED outputs for system feedback.
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// - Ensures the setup is compatible with various microcontroller models (e.g., ATmega328, ATtiny series, etc.)
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// *****************************************************************************************************************
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//******************************************************************************************************************
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// Configuring the clock speed and associated registers. The formula for calculating
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// the clock frequency is F_CPU / (TCCR0B |= (1<<CS00)) * (OCR0A = 159 +1) = 16000000 / (0 * (160)) = 100KHz
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//******************************************************************************************************************
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//******************************************************************************************************************
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// Example: DDRB &= ~(1<<DDB0); // Create a mask by shifting the bit 1 to the left by DDB0's position (bit 0), and then inverting it.
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// The bitwise AND operation (&=) updates the register DDRB by clearing the DDB0 bit (setting it to 0)
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// without affecting the other bits.
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//
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// For instance, if DDRB = b11111111 (binary value), the operation shifts the bit 1 to the left to create the mask
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// (1<<DDB0) = b00000001, and then inverts it, which results in b11111110. The AND operation with DDRB clears DDB0.
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//
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// Before: DDRB = b11111111 // Initial value of DDRB (all pins set as output)
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// Mask: ~(b00000001) = b11111110 // Mask generated by shifting and inverting the bit
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// After: DDRB = b11111110 // The DDB0 bit is cleared (set to 0), while other bits remain unchanged
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//******************************************************************************************************************
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//******************************************************************************************************************
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// Example: DDRB |= (1<<DDB0); // Create a mask by shifting the bit 1 to the left by DDB0's position (bit 0),
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// and then apply a bitwise OR operation to set DDB0 to 1 (configure pin PB0 as an output).
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//
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// For instance, if DDRB = b11111111 (binary value), the operation shifts the bit 1 to the left to create the mask
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// (1<<DDB0) = b00000001. The OR operation with DDRB sets the DDB0 bit to 1, leaving other bits unchanged.
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//
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// Before: DDRB = b11111111 // Initial value of DDRB (all pins set as output)
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// Mask: (1<<DDB0) = b00000001 // Mask generated by shifting the bit 1 to the left to position DDB0
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// After: DDRB = b11111111 // The DDB0 bit is set to 1, configuring pin PB0 as an output
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//******************************************************************************************************************
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//******************************************************************************************************************
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// Example: (PIND & (1<<PIND6)); // Create a mask by shifting the bit 1 to the left by PIND6's position (bit 6),
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// and then apply a bitwise AND operation to read the state of the PIND6 pin.
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// The result will be non-zero (true) if the PIND6 pin is high (1), and zero (false) if the PIND6 pin is low (0).
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//
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// For instance, if PIND = b10101010 (binary value), the operation shifts the bit 1 to the left to create the mask
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// (1<<PIND6) = b01000000. The AND operation between PIND and the mask checks if the 6th bit is set to 1 (high).
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//
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// Before: PIND = b10101010 // Initial value of PIND (register containing input pin states)
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// Mask: (1<<PIND6) = b01000000 // Mask generated by shifting the bit 1 to the left to position PIND6
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// Operation: PIND & b01000000 = b00000000 // If PIND6 is low (0)
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// Operation: PIND & b01000000 = b01000000 // If PIND6 is high (1)
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//
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//******************************************************************************************************************
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//******************************************************************************************************************
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// Example: EICRA |= (1<<ISC01) | (1<<ISC00);
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// This operation configures the external interrupt sense control (ISC) for interrupt INT0 (External Interrupt Request 0).
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// Specifically, it sets the mode of INT0 to "rising edge" trigger, meaning the interrupt will be triggered when the pin
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// transitions from low to high (rising edge).
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//
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// EICRA (External Interrupt Control Register A) controls how external interrupts INT0 and INT1 are triggered.
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// The bits ISC01 and ISC00 in this register define the trigger mode for interrupt INT0.
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//
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// - Setting ISC01 to 1 and ISC00 to 1 (via the OR operation) configures INT0 to trigger on the rising edge.
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//
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// Before: EICRA = b00000000 // Initial value of EICRA, all interrupt sense control bits are cleared (no trigger mode set).
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// Operation: EICRA |= (1<<ISC01) | (1<<ISC00) // Set ISC01 and ISC00 to 1 for rising edge trigger.
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// After: EICRA = b00000011 // The bits ISC01 and ISC00 are now set, configuring INT0 to trigger on rising edge.
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//
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// This technique is commonly used to configure external interrupts to trigger based on specific events like a rising
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// or falling edge on the external interrupt pin (INT0 or INT1).
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//******************************************************************************************************************
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//******************************************************************************************************************
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// Example: EICRA = (EICRA & ~(1<<ISC00)) | (1<<ISC01);
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// This operation configures the external interrupt sense control (ISC) for interrupt INT0 (External Interrupt Request 0).
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// Specifically, it sets INT0 to trigger on a "falling edge" (when the signal transitions from high to low).
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//
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// The bits ISC01 and ISC00 in the EICRA register define how the external interrupt INT0 is triggered. The operation
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// clears the bit ISC00 while setting ISC01 to 1, configuring INT0 to trigger when the pin transitions from high to low,
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// i.e., on the falling edge.
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//
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// EICRA (External Interrupt Control Register A) controls how external interrupts INT0 and INT1 are triggered.
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// - ISC01 = 1, ISC00 = 0 configures INT0 to trigger on falling edge (high to low transition).
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//
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// Before: EICRA = b00000011 // Initial value with ISC01 = 1 and ISC00 = 1 (rising edge trigger for INT0)
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// Operation: EICRA & ~(1<<ISC00) clears ISC00 bit (sets it to 0) while keeping ISC01 at 1. Then OR operation with (1<<ISC01) ensures ISC01 stays 1.
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// After: EICRA = b00000010 // The bit ISC00 is now cleared, configuring INT0 to trigger on the falling edge.
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//
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// This technique is used to configure the interrupt to trigger on the falling edge (transition from high to low),
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// without changing the state of other control bits in the EICRA register.
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//******************************************************************************************************************
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#pragma once
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#ifdef ATmega328_168
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// Define the clock speed for the microcontroller
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#define F_CPU 16000000L
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#define TIMER_TCNT_CLEAR TCNT0 = 0x00 //TCNT0 - Timer/Counter Register
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#define SET_OCROA_DIV OCR0A = 159; //OCR0A – Output Compare Register A, 0x10011111, 100KHz
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#define SET_TIMER_TCCROA TCCR0A |= (1 << WGM01); //TCCR0A – Timer/Counter Control Register A. turn on CTC mode, WGM01
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#define SET_TIMER_TCCROB TCCR0B |= (1 << CS00); //TCCR0B – Timer/Counter Control Register B, CS00: Clock Select, clk I/O
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// Clear the timer count register (TCNT0)
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#define TIMER_TCNT_CLEAR TCNT0 = 0x00 // TCNT0 - Timer/Counter Register, clears the timer count
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// Set OCR0A to achieve a 100KHz clock frequency
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#define SET_OCROA_DIV OCR0A = 159; // OCR0A – Output Compare Register A, 100KHz clock generation, 0x10011111
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// Configure Timer/Counter 0 for CTC mode and enable the clock source
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#define SET_TIMER_TCCROA TCCR0A |= (1 << WGM01); // TCCR0A – Timer/Counter Control Register A, enable CTC mode (WGM01)
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#define SET_TIMER_TCCROB TCCR0B |= (1 << CS00); // TCCR0B – Timer/Counter Control Register B, set clock source to I/O clock
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//Waveform Generation Mode, Mode 2 CTC
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// Interrupt vector for timer compare match event
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#define CTC_TIMER_VECTOR TIMER0_COMPA_vect //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
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#include <stdint.h>
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#include <stdbool.h>
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#include <avr/io.h>
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@@ -20,187 +119,91 @@
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#include <avr/sfr_defs.h>
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#include <util/delay.h>
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// Globale interrupt seting
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#define GLOBAL_INTERRUPT_ENABLE SREG |= (1<<7)
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#define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1<<7)
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// Global interrupt control settings
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#define GLOBAL_INTERRUPT_ENABLE SREG |= (1<<7) // Set the I-bit (bit 7) in the Status Register to enable global interrupts
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#define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1<<7) // Clear the I-bit (bit 7) in the Status Register to disable global interrupts
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// Handling the main pins
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// Main pin configuration for input and output
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// Main pins input
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#define PIN_DATA_INPUT DDRB &= ~(1<<DDB0)
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#define PIN_WFCK_INPUT DDRB &= ~(1<<DDB1) // Create a mask (1<<0) with the first bit at 1 b00000001 uses the ~ operator to perform a bit inversion b11111110,
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#define PIN_SQCK_INPUT DDRD &= ~(1<<DDD6) // &= updates the DDRB register with the AND operator and the mask, DDRB bxxxxxxxx OR mask b11111110 = bxxxxxxx0
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#define PIN_SUBQ_INPUT DDRD &= ~(1<<DDD7)
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// Define the main pins as inputs
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#define PIN_DATA_INPUT DDRB &= ~(1<<DDB0) // Set DDRB register to configure PINB0 as input
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#define PIN_WFCK_INPUT DDRB &= ~(1<<DDB1) // Set DDRB register to configure PINB1 as input
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#define PIN_SQCK_INPUT DDRD &= ~(1<<DDD6) // Set DDRB register to configure PINB6 as input
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#define PIN_SUBQ_INPUT DDRD &= ~(1<<DDD7) // Set DDRB register to configure PINB7 as input
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// Main pin output
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#define PIN_DATA_OUTPUT DDRB |= (1<<DDB0) // Create a mask (1<<0) with the first bit at 1 b00000001,
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#define PIN_WFCK_OUTPUT DDRB |= (1<<DDB1) // |= updates the DDRB register with the OR operator and the mask, DDRB bxxxxxxxx OR mask b00000001 = bxxxxxxx1
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// Enable pull-ups and set high on the main pins
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#define PIN_DATA_OUTPUT DDRB |= (1<<DDB0) // Set DDRB register to configure PINB0 as output
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#define PIN_WFCK_OUTPUT DDRB |= (1<<DDB1) // Set DDRB register to configure PINB1 as output
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// Define pull-ups and set high at the main pin
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#define PIN_DATA_SET PORTB |= (1<<PB0) // Create a mask (1<<0) with the first bit at 1 b00000001,
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// |= updates the PORTB register with the OR operator and the mask, PORTB bxxxxxxxx OR mask b00000001 = bxxxxxxx1
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#define PIN_DATA_SET PORTB |= (1<<PB0) // Set PORTB register to make PINB0 high (enable pull-up)
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// Define pull-ups set down at the main pin
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#define PIN_DATA_CLEAR PORTB &= ~(1<<PB0) // Create a mask (1<<0) with the first bit at 1 b00000001 uses the ~ operator to perform a bit inversion b11111110,
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#define PIN_WFCK_CLEAR PORTB &= ~(1<<PB1) // &= updates the DDRB register with the AND operator and the mask, DDRB bxxxxxxxx OR mask b11111110 = bxxxxxxx0
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// Clear the main pins (set low)
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#define PIN_DATA_CLEAR PORTB &= ~(1<<PB0) // Set PORTB register to make PINB0 low
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#define PIN_WFCK_CLEAR PORTB &= ~(1<<PB1) // Set PORTB register to make PINB1 low
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// Read the main pins
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#define PIN_SQCK_READ (PIND & (1<<PIND6)) // Create a mask (1<<6) with the six bit at 1 b00100000,
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#define PIN_SUBQ_READ (PIND & (1<<PIND7)) // compare the PINB register and the mask with the AND operator, and returns the result, PINB bxx1xxxxx AND mask b00100000 = 1
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#define PIN_WFCK_READ (PINB & (1<<PINB1))
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// Read the state of the main input pins
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#define PIN_SQCK_READ (PIND & (1<<PIND6)) // Check if the value of PIND6 is high (1)
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#define PIN_SUBQ_READ (PIND & (1<<PIND7)) // Check if the value of PIND7 is high (1)
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#define PIN_WFCK_READ (PINB & (1<<PINB1)) // Check if the value of PIND1 is high (1)
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// Handling and use of the LED pin
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// LED pin handling (for indication)
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#define LED_RUN
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#define PIN_LED_OUTPUT DDRB |= (1<<DDB5)
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#define PIN_LED_ON PORTB |= (1<<PB5)
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#define PIN_LED_OFF PORTB &= ~(1<<PB5)
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#define PIN_LED_OUTPUT DDRB |= (1<<DDB5) // Configure PINB5 as output (for LED)
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#define PIN_LED_ON PORTB |= (1<<PB5) // Set PINB5 high (turn on LED)
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#define PIN_LED_OFF PORTB &= ~(1<<PB5) // Set PINB5 low (turn off LED)
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// Handling the BIOS patch
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// BIOS interrupt seting
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#define TIMER_INTERRUPT_ENABLE TIMSK0 |= (1<<OCIE0A)
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#define TIMER_INTERRUPT_DISABLE TIMSK0 &= ~(1<<OCIE0A)
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// Enable/Disable timer interrupts
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#define TIMER_INTERRUPT_ENABLE TIMSK0 |= (1<<OCIE0A) // Enable interrupt on Timer0 Compare Match A
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#define TIMER_INTERRUPT_DISABLE TIMSK0 &= ~(1<<OCIE0A) // Disable interrupt on Timer0 Compare Match A
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// BIOS timer clear
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#define TIMER_TIFR_CLEAR TIFR0 |= (1<<OCF0A)
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// Clear the timer interrupt flag
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#define TIMER_TIFR_CLEAR TIFR0 |= (1<<OCF0A) // Clear the Timer0 Compare Match A interrupt flag
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// Pins input
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#define PIN_AX_INPUT DDRD &= ~(1<<DDD2)
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#define PIN_AY_INPUT DDRD &= ~(1<<DDD3)
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#define PIN_DX_INPUT DDRD &= ~(1<<DDD4)
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// Pin output
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#define PIN_DX_OUTPUT DDRD |= (1<<DDD4)
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// Define pull-ups set high
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#define PIN_DX_SET PORTD |= (1<<PD4)
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// Define pull-ups set down
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#define PIN_DX_CLEAR PORTD &= ~(1<<PD4)
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// Read pins for BIOS patch
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#define PIN_AX_READ (PIND & (1<<PIND2))
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#define PIN_AY_READ (PIND & (1<<PIND3))
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// Define input pins for the BIOS patch
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#define PIN_AX_INPUT DDRD &= ~(1<<DDD2) // Set DDRD register to configure PIND2 as input
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#define PIN_AY_INPUT DDRD &= ~(1<<DDD3) // Set DDRD register to configure PIND3 as input
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#define PIN_DX_INPUT DDRD &= ~(1<<DDD4) // Set DDRD register to configure PIND4 as input
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// Handling the external interrupt
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#define PIN_AX_INTERRUPT_ENABLE EIMSK |= (1<<INT0)
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#define PIN_AY_INTERRUPT_ENABLE EIMSK |= (1<<INT1)
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// Define output pins for the BIOS patch
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#define PIN_DX_OUTPUT DDRD |= (1<<DDD4) // Set DDRD register to configure PIND4 as output
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#define PIN_AX_INTERRUPT_DISABLE EIMSK &= ~(1<<INT0)
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#define PIN_AY_INTERRUPT_DISABLE EIMSK &= ~(1<<INT1)
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// Set pull-ups high on output pins
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#define PIN_DX_SET PORTD |= (1<<PD4) // Set PORTD register to make PIND4 high
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#define PIN_AX_INTERRUPT_RISING EICRA |= (1<<ISC01)|(1<<ISC00)
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#define PIN_AY_INTERRUPT_RISING EICRA |= (1<<ISC11)|(1<<ISC10)
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// Set pull-ups low on output pins
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#define PIN_DX_CLEAR PORTD &= ~(1<<PD4) // Set PORTD register to make PIND4 low
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#define PIN_AX_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC00)) | (1<<ISC01))
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#define PIN_AY_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC10)) | (1<<ISC11))
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// Read the input pins for the BIOS patch
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#define PIN_AX_READ (PIND & (1<<PIND2)) // Read the state of PIND2
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#define PIN_AY_READ (PIND & (1<<PIND3)) // Read the state of PIND3
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#define PIN_AX_INTERRUPT_VECTOR INT0_vect
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#define PIN_AY_INTERRUPT_VECTOR INT1_vect
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// External interrupt configuration for BIOS patch
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#define PIN_AX_INTERRUPT_ENABLE EIMSK |= (1<<INT0) // Enable external interrupt on INT0 (PINB2)
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#define PIN_AY_INTERRUPT_ENABLE EIMSK |= (1<<INT1) // Enable external interrupt on INT1 (PINB3)
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// Handling and reading the switch pin for patch BIOS
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#define PIN_SWITCH_INPUT DDRD &= ~(1<<DDD5)
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#define PIN_SWITCH_SET PORTD |= (1<<PD5)
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#define PIN_SWICHE_READ (PIND & (1<<PIND5))
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#define PIN_AX_INTERRUPT_DISABLE EIMSK &= ~(1<<INT0) // Disable external interrupt on INT0
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#define PIN_AY_INTERRUPT_DISABLE EIMSK &= ~(1<<INT1) // Disable external interrupt on INT1
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#define PIN_AX_INTERRUPT_RISING EICRA |= (1<<ISC01)|(1<<ISC00) // Configure INT0 for rising edge trigger
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#define PIN_AY_INTERRUPT_RISING EICRA |= (1<<ISC11)|(1<<ISC10) // Configure INT1 for rising edge trigger
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#define PIN_AX_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC00)) | (1<<ISC01)) // Configure INT0 for falling edge trigger
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#define PIN_AY_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC10)) | (1<<ISC11)) // Configure INT1 for falling edge trigger
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// Interrupt vectors for external interrupts
|
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#define PIN_AX_INTERRUPT_VECTOR INT0_vect // Interrupt vector for INT0 (external interrupt)
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#define PIN_AY_INTERRUPT_VECTOR INT1_vect // Interrupt vector for INT1 (external interrupt)
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||||
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// Handle switch input for BIOS patch
|
||||
#define PIN_SWITCH_INPUT DDRD &= ~(1<<DDD5) // Configure PIND5 as input for switch
|
||||
#define PIN_SWITCH_SET PORTD |= (1<<PD5) // Set PIND5 high (enable pull-up)
|
||||
#define PIN_SWICHE_READ (PIND & (1<<PIND5)) // Read the state of PIND5 (switch input)
|
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|
||||
#endif
|
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|
||||
#ifdef LGT8F328P
|
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|
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#define F_CPU 32000000L
|
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#define TIMER_TCNT_CLEAR TCNT0 = 0x00
|
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#define SET_OCROA_DIV OCR0A = 319;
|
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#define SET_TIMER_TCCROA TCCR0A |= (1 << WGM01);
|
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#define SET_TIMER_TCCROB TCCR0B |= (1 << CS00);
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#define CTC_TIMER_VECTOR TIMER0_COMPA_vect //??
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||||
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#include <stdint.h>
|
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#include <stdbool.h>
|
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#include <avr/io.h>
|
||||
#include <avr/interrupt.h>
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#include <avr/sfr_defs.h>
|
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#include <util/delay.h>
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||||
|
||||
// Globale interrupt seting
|
||||
#define GLOBAL_INTERRUPT_ENABLE SREG |= (1<<7)
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#define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1<<7)
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||||
|
||||
// Handling the main pins
|
||||
|
||||
// Main pins input
|
||||
#define PIN_DATA_INPUT DDRB &= ~(1<<DDB0)
|
||||
#define PIN_WFCK_INPUT DDRB &= ~(1<<DDB1)
|
||||
#define PIN_SQCK_INPUT DDRD &= ~(1<<DDD6)
|
||||
#define PIN_SUBQ_INPUT DDRD &= ~(1<<DDD7)
|
||||
|
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// Main pin output
|
||||
#define PIN_DATA_OUTPUT DDRB |= (1<<DDB0)
|
||||
#define PIN_WFCK_OUTPUT DDRB |= (1<<DDB1)
|
||||
|
||||
// Define pull-ups and set high at the main pin
|
||||
#define PIN_DATA_SET PORTB |= (1<<PB0)
|
||||
|
||||
|
||||
// Define pull-ups set down at the main pin
|
||||
#define PIN_DATA_CLEAR PORTB &= ~(1<<PB0)
|
||||
#define PIN_WFCK_CLEAR PORTB &= ~(1<<PB1)
|
||||
|
||||
// Read the main pins
|
||||
#define PIN_SQCK_READ (PIND & (1<<PIND6))
|
||||
#define PIN_SUBQ_READ (PIND & (1<<PIND7))
|
||||
#define PIN_WFCK_READ (PINB & (1<<PINB1))
|
||||
|
||||
// Handling and use of the LED pin
|
||||
#define LED_RUN
|
||||
#define PIN_LED_OUTPUT DDRB |= (1<<DDB5)
|
||||
#define PIN_LED_ON PORTB |= (1<<PB5)
|
||||
#define PIN_LED_OFF PORTB &= ~(1<<PB5)
|
||||
|
||||
// Handling the BIOS patch
|
||||
|
||||
// BIOS interrupt seting
|
||||
#define TIMER_INTERRUPT_ENABLE TIMSK0 |= (1<<OCIE0A)
|
||||
#define TIMER_INTERRUPT_DISABLE TIMSK0 &= ~(1<<OCIE0A)
|
||||
|
||||
// BIOS timer clear
|
||||
#define TIMER_TIFR_CLEAR TIFR0 |= (1<<OCF0A)
|
||||
|
||||
// Pins input
|
||||
#define PIN_AX_INPUT DDRD &= ~(1<<DDD2)
|
||||
#define PIN_AY_INPUT DDRD &= ~(1<<DDD3)
|
||||
#define PIN_DX_INPUT DDRD &= ~(1<<DDD4)
|
||||
// Pin output
|
||||
#define PIN_DX_OUTPUT DDRD |= (1<<DDD4)
|
||||
// Define pull-ups set high
|
||||
#define PIN_DX_SET PORTD |= (1<<PD4)
|
||||
// Define pull-ups set down
|
||||
#define PIN_DX_CLEAR PORTD &= ~(1<<PD4)
|
||||
// Read pins for BIOS patch
|
||||
#define PIN_AX_READ (PIND & (1<<PIND2))
|
||||
#define PIN_AY_READ (PIND & (1<<PIND3))
|
||||
|
||||
// Handling the external interrupt
|
||||
#define PIN_AX_INTERRUPT_ENABLE EIMSK |= (1<<INT0)
|
||||
#define PIN_AY_INTERRUPT_ENABLE EIMSK |= (1<<INT1)
|
||||
|
||||
#define PIN_AX_INTERRUPT_DISABLE EIMSK &= ~(1<<INT0)
|
||||
#define PIN_AY_INTERRUPT_DISABLE EIMSK &= ~(1<<INT1)
|
||||
|
||||
#define PIN_AX_INTERRUPT_RISING EICRA |= (1<<ISC01)|(1<<ISC00)
|
||||
#define PIN_AY_INTERRUPT_RISING EICRA |= (1<<ISC11)|(1<<ISC10)
|
||||
|
||||
#define PIN_AX_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC00)) | (1<<ISC01))
|
||||
#define PIN_AY_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC10)) | (1<<ISC11))
|
||||
|
||||
#define PIN_AX_INTERRUPT_VECTOR INT0_vect
|
||||
#define PIN_AY_INTERRUPT_VECTOR INT1_vect
|
||||
|
||||
// Handling and reading the switch pin for patch BIOS
|
||||
#define PIN_SWITCH_INPUT DDRD &= ~(1<<DDD5)
|
||||
#define PIN_SWITCH_SET PORTD |= (1<<PD5)
|
||||
#define PIN_SWICHE_READ (PIND & (1<<PIND5))
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef ATmega32U4_16U4
|
||||
|
||||
@@ -350,9 +353,16 @@
|
||||
#define PIN_LED_OFF PORTB &= ~(1<<PB3)
|
||||
|
||||
#if !defined(SCPH_xxx1) && !defined(SCPH_xxx2) && !defined(SCPH_103)
|
||||
#error "ATtiny85_45_25 Not compatible with BIOS patch, please choose a compatible SCPH. For example: SCPH_xxx1: SCPH_xxx2: SCPH_103"
|
||||
#error "ATtiny85_45_25 Not compatible with BIOS patch"
|
||||
#endif
|
||||
|
||||
|
||||
// *****************************************************************************************************************
|
||||
// WARNING:
|
||||
// The following code is not functional as-is.
|
||||
// *****************************************************************************************************************
|
||||
|
||||
|
||||
#ifdef ATtiny88_48
|
||||
|
||||
#define F_CPU 16000000L
|
||||
@@ -454,16 +464,14 @@
|
||||
|
||||
#ifdef ATtiny214_414
|
||||
|
||||
|
||||
|
||||
//#define SET_CTRLA
|
||||
//#define F_CPU 16000000L
|
||||
#define DF_CPU 20000000L
|
||||
#define TIMER_TCNT_CLEAR TCA0.SINGLE.CNT = 0x00 //TCNT0 - Timer/Counter Register
|
||||
#define SET_OCROA_DIV TCA0.SINGLE.CMP0L = 159; //OCR0A – Output Compare Register A, 0x10011111, 100KHz
|
||||
#define SET_TIMER_TCCROA TCA0.SINGLE.CTRLB |= TCA_SINGLE_WGMODE_FRQ_gc //TCCR0A – Timer/Counter Control Register A. turn on CTC mode, CTC0
|
||||
#define SET_TIMER_TCCROB TCA0.SINGLE.CTRLA |= TCA_SINGLE_CLKSEL_DIV1_gc//TCCR0B – Timer/Counter Control Register B, CS00: Clock Select, clk I/O
|
||||
#define SET_OCROA_DIV TCA0.SINGLE.CMP0L = 100; //OCR0A – Output Compare Register A, 0x10011111, 100KHz
|
||||
#define SET_TIMER_TCCROA TCA0.SINGLE.CTRLB |= (1 << TCA_SINGLE_WGM0); //TCA_SINGLE_WGMODE_FRQ_gc //TCCR0A – Timer/Counter Control Register A. turn on CTC mode, CTC0
|
||||
#define SET_TIMER_TCCROB TCA0.SINGLE.CTRLA |= (1 << TCA_SINGLE_CLKSEL0); //TCA_SINGLE_CLKSEL_DIV1_gc//TCCR0B – Timer/Counter Control Register B, CS00: Clock Select, clk I/O
|
||||
//Waveform Generation Mode, Mode 2 CTC
|
||||
#define CTC_TIMER_VECTOR TCA0_CMP0_vect //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
|
||||
#define CTC_TIMER_VECTOR TCA0_OVF_vect //TCA0_CMP0_vect //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
@@ -474,8 +482,8 @@
|
||||
#include <util/delay.h>
|
||||
|
||||
// Globale interrupt seting
|
||||
#define GLOBAL_INTERRUPT_ENABLE CPU.SREG |= (1<<7)
|
||||
#define GLOBAL_INTERRUPT_DISABLE CPU.SREG &= ~(1<<7)
|
||||
#define GLOBAL_INTERRUPT_ENABLE __asm__ __volatile__ ("sei" ::) //CPU.SREG |= (1<<7)
|
||||
#define GLOBAL_INTERRUPT_DISABLE __asm__ __volatile__ ("cli" ::) //CPU.SREG &= ~(1<<7)
|
||||
|
||||
// Handling the main pins
|
||||
|
||||
@@ -557,6 +565,103 @@
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef LGT8F328P
|
||||
|
||||
#define F_CPU 32000000L
|
||||
#define TIMER_TCNT_CLEAR TCNT0 = 0x00
|
||||
#define SET_OCROA_DIV OCR0A = 319;
|
||||
#define SET_TIMER_TCCROA TCCR0A |= (1 << WGM01);
|
||||
#define SET_TIMER_TCCROB TCCR0B |= (1 << CS00);
|
||||
#define CTC_TIMER_VECTOR TIMER0_COMPA_vect
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <avr/io.h>
|
||||
#include <avr/interrupt.h>
|
||||
#include <avr/sfr_defs.h>
|
||||
#include <util/delay.h>
|
||||
|
||||
// Globale interrupt seting
|
||||
#define GLOBAL_INTERRUPT_ENABLE SREG |= (1<<7)
|
||||
#define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1<<7)
|
||||
|
||||
// Handling the main pins
|
||||
|
||||
// Main pins input
|
||||
#define PIN_DATA_INPUT DDRB &= ~(1<<DDB0)
|
||||
#define PIN_WFCK_INPUT DDRB &= ~(1<<DDB1)
|
||||
#define PIN_SQCK_INPUT DDRD &= ~(1<<DDD6)
|
||||
#define PIN_SUBQ_INPUT DDRD &= ~(1<<DDD7)
|
||||
|
||||
// Main pin output
|
||||
#define PIN_DATA_OUTPUT DDRB |= (1<<DDB0)
|
||||
#define PIN_WFCK_OUTPUT DDRB |= (1<<DDB1)
|
||||
|
||||
// Define pull-ups and set high at the main pin
|
||||
#define PIN_DATA_SET PORTB |= (1<<PB0)
|
||||
|
||||
|
||||
// Define pull-ups set down at the main pin
|
||||
#define PIN_DATA_CLEAR PORTB &= ~(1<<PB0)
|
||||
#define PIN_WFCK_CLEAR PORTB &= ~(1<<PB1)
|
||||
|
||||
// Read the main pins
|
||||
#define PIN_SQCK_READ (PIND & (1<<PIND6))
|
||||
#define PIN_SUBQ_READ (PIND & (1<<PIND7))
|
||||
#define PIN_WFCK_READ (PINB & (1<<PINB1))
|
||||
|
||||
// Handling and use of the LED pin
|
||||
#define LED_RUN
|
||||
#define PIN_LED_OUTPUT DDRB |= (1<<DDB5)
|
||||
#define PIN_LED_ON PORTB |= (1<<PB5)
|
||||
#define PIN_LED_OFF PORTB &= ~(1<<PB5)
|
||||
|
||||
// Handling the BIOS patch
|
||||
|
||||
// BIOS interrupt seting
|
||||
#define TIMER_INTERRUPT_ENABLE TIMSK0 |= (1<<OCIE0A)
|
||||
#define TIMER_INTERRUPT_DISABLE TIMSK0 &= ~(1<<OCIE0A)
|
||||
|
||||
// BIOS timer clear
|
||||
#define TIMER_TIFR_CLEAR TIFR0 |= (1<<OCF0A)
|
||||
|
||||
// Pins input
|
||||
#define PIN_AX_INPUT DDRD &= ~(1<<DDD2)
|
||||
#define PIN_AY_INPUT DDRD &= ~(1<<DDD3)
|
||||
#define PIN_DX_INPUT DDRD &= ~(1<<DDD4)
|
||||
// Pin output
|
||||
#define PIN_DX_OUTPUT DDRD |= (1<<DDD4)
|
||||
// Define pull-ups set high
|
||||
#define PIN_DX_SET PORTD |= (1<<PD4)
|
||||
// Define pull-ups set down
|
||||
#define PIN_DX_CLEAR PORTD &= ~(1<<PD4)
|
||||
// Read pins for BIOS patch
|
||||
#define PIN_AX_READ (PIND & (1<<PIND2))
|
||||
#define PIN_AY_READ (PIND & (1<<PIND3))
|
||||
|
||||
// Handling the external interrupt
|
||||
#define PIN_AX_INTERRUPT_ENABLE EIMSK |= (1<<INT0)
|
||||
#define PIN_AY_INTERRUPT_ENABLE EIMSK |= (1<<INT1)
|
||||
|
||||
#define PIN_AX_INTERRUPT_DISABLE EIMSK &= ~(1<<INT0)
|
||||
#define PIN_AY_INTERRUPT_DISABLE EIMSK &= ~(1<<INT1)
|
||||
|
||||
#define PIN_AX_INTERRUPT_RISING EICRA |= (1<<ISC01)|(1<<ISC00)
|
||||
#define PIN_AY_INTERRUPT_RISING EICRA |= (1<<ISC11)|(1<<ISC10)
|
||||
|
||||
#define PIN_AX_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC00)) | (1<<ISC01))
|
||||
#define PIN_AY_INTERRUPT_FALLING (EICRA = (EICRA & ~(1<<ISC10)) | (1<<ISC11))
|
||||
|
||||
#define PIN_AX_INTERRUPT_VECTOR INT0_vect
|
||||
#define PIN_AY_INTERRUPT_VECTOR INT1_vect
|
||||
|
||||
// Handling and reading the switch pin for patch BIOS
|
||||
#define PIN_SWITCH_INPUT DDRD &= ~(1<<DDD5)
|
||||
#define PIN_SWITCH_SET PORTD |= (1<<PD5)
|
||||
#define PIN_SWICHE_READ (PIND & (1<<PIND5))
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CH32V003
|
||||
|
||||
|
||||
@@ -249,14 +249,19 @@ int main() {
|
||||
;
|
||||
#endif
|
||||
|
||||
Timer_Start();
|
||||
#ifdef LED_RUN
|
||||
PIN_LED_OFF;
|
||||
#endif
|
||||
|
||||
Timer_Start();
|
||||
//************************************************************************
|
||||
// Board detection
|
||||
//
|
||||
// GATE: __----------------------- // this is a PU-7 .. PU-20 board!
|
||||
//
|
||||
// WFCK: __-_-_-_-_-_-_-_-_-_-_-_- // this is a PU-22 or newer board!
|
||||
// typical readouts PU-22: highs: 2449 lows: 2377
|
||||
//************************************************************************
|
||||
do {
|
||||
if (PIN_WFCK_READ == 0) lows++; // good for ~5000 reads in 1s
|
||||
_delay_us(200);
|
||||
@@ -273,10 +278,6 @@ int main() {
|
||||
wfck_mode = 0; //flag oldmod
|
||||
}
|
||||
|
||||
#ifdef LED_RUN
|
||||
PIN_LED_OFF;
|
||||
#endif
|
||||
|
||||
while (1) {
|
||||
|
||||
_delay_ms(1); /* Start with a small delay, which can be necessary
|
||||
@@ -320,12 +321,14 @@ int main() {
|
||||
|
||||
GLOBAL_INTERRUPT_ENABLE; // End critical section
|
||||
|
||||
/* Check if read head is in wobble area
|
||||
| We only want to unlock game discs (0x41) and only if the read head is in the outer TOC area.
|
||||
| We want to see a TOC sector repeatedly before injecting (helps with timing and marginal lasers).
|
||||
| All this logic is because we don't know if the HC-05 is actually processing a getSCEX() command.
|
||||
| Hysteresis is used because older drives exhibit more variation in read head positioning.
|
||||
| While the laser lens moves to correct for the error, they can pick up a few TOC sectors. */
|
||||
//************************************************************************
|
||||
// Check if read head is in wobble area
|
||||
// We only want to unlock game discs (0x41) and only if the read head is in the outer TOC area.
|
||||
// We want to see a TOC sector repeatedly before injecting (helps with timing and marginal lasers).
|
||||
// All this logic is because we don't know if the HC-05 is actually processing a getSCEX() command.
|
||||
// Hysteresis is used because older drives exhibit more variation in read head positioning.
|
||||
// While the laser lens moves to correct for the error, they can pick up a few TOC sectors.
|
||||
//************************************************************************
|
||||
|
||||
//This variable initialization macro is to replace (0x41) with a filter that will check that only the three most significant bits are correct. 0x001xxxxx
|
||||
uint8_t isDataSector = (((scbuf[0] & 0x40) == 0x40) && (((scbuf[0] & 0x10) == 0) && ((scbuf[0] & 0x80) == 0)));
|
||||
@@ -355,8 +358,12 @@ int main() {
|
||||
// Hysteresis naturally goes to 0 otherwise (the read head moved).
|
||||
hysteresis = 11;
|
||||
|
||||
//************************************************************************
|
||||
//Executes the region code patch injection sequence.
|
||||
//************************************************************************
|
||||
|
||||
#ifdef LED_RUN
|
||||
PIN_LED_ON;
|
||||
PIN_LED_ON;
|
||||
#endif
|
||||
|
||||
PIN_DATA_OUTPUT;
|
||||
@@ -383,7 +390,7 @@ int main() {
|
||||
PIN_DATA_INPUT;
|
||||
|
||||
#ifdef LED_RUN
|
||||
PIN_LED_OFF;
|
||||
PIN_LED_OFF;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user