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https://github.com/kalymos/PsNee.git
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Docs: minor comment fixes and technical alignment
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@@ -199,8 +199,8 @@
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// Define the main pins as inputs
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#define PIN_DATA_INPUT DDRB &= ~(1 << DDB0) // Set DDRB register to configure PINB0 as input
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#define PIN_WFCK_INPUT DDRB &= ~(1 << DDB1) // Set DDRB register to configure PINB1 as input
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#define PIN_SQCK_INPUT DDRD &= ~(1 << DDD6) // Set DDRB register to configure PINB6 as input
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#define PIN_SUBQ_INPUT DDRD &= ~(1 << DDD7) // Set DDRB register to configure PINB7 as input
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#define PIN_SQCK_INPUT DDRD &= ~(1 << DDD6) // Set DDRD register to configure PINB6 as input
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#define PIN_SUBQ_INPUT DDRD &= ~(1 << DDD7) // Set DDRD register to configure PINB7 as input
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// Configure lines as outputs (for injection/override)
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#define PIN_DATA_OUTPUT DDRB |= (1 << DDB0) // Set DDRB register to configure PINB0 as output
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@@ -214,7 +214,7 @@
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// Direct Register Reading (High-speed polling)
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#define PIN_SQCK_READ (!!(PIND & (1 << PIND6))) // Check if the value of PIND6 is high (1)
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#define PIN_SUBQ_READ (!!(PIND & (1 << PIND7))) // Check if the value of PIND7 is high (1)
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#define PIN_WFCK_READ (!!(PINB & (1 << PINB1))) // Check if the value of PIND1 is high (1)
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#define PIN_WFCK_READ (!!(PINB & (1 << PINB1))) // Check if the value of PINB1 is high (1)
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// --- Status Indication (LED) ---
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#ifdef LED_RUN
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@@ -244,7 +244,7 @@
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#define PIN_AX_READ (!!(PIND & (1 << PIND2)))
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// Hardware Interrupt (INT0) for AX pulse counting
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#define PIN_AX_INTERRUPT_ENABLE EIMSK |= (1<<INT0) // Enable external interrupt on INT0 (PINB2)
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#define PIN_AX_INTERRUPT_ENABLE EIMSK |= (1<<INT0) // Enable external interrupt on INT0 (PINB3)
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#define PIN_AX_INTERRUPT_DISABLE EIMSK &= ~(1<<INT0) // Disable external interrupt on INT0
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#define PIN_AX_INTERRUPT_RISING EICRA |= (1<<ISC01)|(1<<ISC00) // Configure INT0 for rising edge trigger
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#define PIN_AX_INTERRUPT_VECTOR INT0_vect // Interrupt vector for INT0 (external interrupt)
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@@ -321,13 +321,13 @@ uint8_t hysteresis = 0;
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* FUNCTION : BoardDetection
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*
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* DESCRIPTION :
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* Distinguishes motherboard generations (PU-7 through PU-22+) by analyzing
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* Distinguishes motherboard generations (PU-7 through PU-18) by analyzing
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* the behavior of the WFCK signal.
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*
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* SIGNAL CHARACTERISTICS:
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* - Legacy Boards (PU-7 to PU-20): WFCK acts as a static GATE signal.
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* - Legacy Boards (PU-7 to PU-18): WFCK acts as a static GATE signal.
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* It remains HIGH.
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* - Modern Boards (PU-22 or newer): WFCK is an oscillating clock signal
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* - Modern Boards (PU-20 or newer): WFCK is an oscillating clock signal
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* (Frequency-based).
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*
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*
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@@ -383,17 +383,13 @@ void BoardDetection() {
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// If the window expires without seeing enough LOW pulses, it remains wfck_mode = 0 (GATE)
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}
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/******************************************************************************************************************
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* FUNCTION : CaptureSUBQ
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*
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* DESCRIPTION :
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* Captures a complete 12-byte SUBQ frame from the CD controller.
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* Synchronizes with the SQCK (SUBQ Clock) pin to shift in serial data from
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* the SUBQ pin. This implementation follows the standard PlayStation CDIC
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* protocol (Synchronous Serial, LSB first).
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* Synchronizes with the SQCK (SUBQ Clock) pin to shift in serial data.
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* Implementation: Synchronous Serial, LSB first reconstruction.
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******************************************************************************************************************/
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void CaptureSUBQ(void) {
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@@ -403,7 +399,7 @@ void CaptureSUBQ(void) {
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do {
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uint8_t bitsToRead = 8;
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// Direct byte initialization to save a register copy
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// Clear current byte to avoid garbage data
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*bufferPtr = 0;
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while (bitsToRead--) {
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@@ -415,8 +411,8 @@ void CaptureSUBQ(void) {
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while (!PIN_SQCK_READ); // Wait for rising edge
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/**
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* PHASE 2: BIT ACQUISITION & SHIFTING
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* LSB first: shift the buffer pointer directly to avoid 'currentByte' overhead.
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* PHASE 2: BIT ACQUISITION & LSB RECONSTRUCTION
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* Shift right to move previous bits toward LSB and inject new bit at 0x80.
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*/
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*bufferPtr >>= 1;
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if (PIN_SUBQ_READ) {
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@@ -510,11 +506,14 @@ void CaptureSUBQ(void) {
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if (SUBQBuffer[1] == 0x00 && SUBQBuffer[6] == 0x00) {
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/*
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* HIT INCREMENT CONDITIONS:
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* A. LEAD-IN PATTERNS: Detects TOC markers (A0-A2) or Track 01 at spiral start.
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* (uint8_t)(SUBQBuffer[3] - 0x03) >= 0xF5 handles the 0x98 to 0x02 wrap-around.
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* B. TRACKING LOCK: Maintains count if already synced and reading valid sectors.
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*/
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* HIT INCREMENT CONDITIONS:
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* A. LEAD-IN PATTERNS: Detects TOC markers (A0-A2) or Track 01 at the spiral start.
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* The calculation (uint8_t)(SUBQBuffer[3] - 0x03) >= 0xF5 handles
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* the 0x98 to 0x02 wrap-around near the TOC boundary.
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* B. TRACKING LOCK: Maintains the counter if already synced and reading
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* valid sectors (Audio or Data).
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*/
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if ( (isDataSector && (SUBQBuffer[2] >= 0xA0 || (SUBQBuffer[2] == 0x01 && ( (uint8_t)(SUBQBuffer[3] - 0x03) >= 0xF5)))) ||
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(hysteresis > 0 && (SUBQBuffer[0] == 0x01 || isDataSector)) )
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{
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@@ -731,7 +730,7 @@ int main() {
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CaptureSUBQ();
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// Confidence Filtering: Accumulate hits toward HYSTERESIS_MAX
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// Validation and Data/TOC masking (0xD0) are handled inside the filter.
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// Control byte masking (0xD0) and TOC pattern matching are handled inside the filter.
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FilterSUBQSamples(SUBQBuffer[0]);
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// Execution: Trigger SCEx injection once confidence (hysteresis) is reached
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