github.com/kalymos.PsNee
1
0
Fork 0
mirror of https://github.com/kalymos/PsNee.git synced 2026-01-11 23:53:07 +00:00
Code Issues Releases Wiki Activity

MUC-MCU

Browse Source 
Fixed the MUC-MCU file name.
Fixed a bug that prevented additional MCUs from being compiled.
Modified the clock registers for ATtiny 48-88s; the TCCROB register is missing in these MUCs.
This commit is contained in:
kalymos 2025-04-19 18:44:54 +02:00
parent f51c503516
commit f4e16fe717
2 changed files with 13 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
PSNee_V8.6/PSNee_V8.6/MUC.h → PSNee_V8.6/PSNee_V8.6/MCU.h
View File

@ -355,7 +355,7 @@
#if !defined(SCPH_xxx1) && !defined(SCPH_xxx2) && !defined(SCPH_103) && !defined(SCPH_xxxx)
#error "ATtiny85_45_25 Not compatible with BIOS patch"
#endif
#endif
// *****************************************************************************************************************
// WARNING:
@ -369,8 +369,10 @@
#define TIMER_TCNT_CLEAR TCNT0 = 0x00 //TCNT0 - Timer/Counter Register
#define SET_OCROA_DIV OCR0A = 159; //OCR0A – Output Compare Register A, 0x10011111, 100KHz
#define SET_TIMER_TCCROA TCCR0A |= (1 << CTC0 ); //TCCR0A – Timer/Counter Control Register A. turn on CTC mode, CTC0
#define SET_TIMER_TCCROB TCCR0A |= (1 << CS00); //TCCR0B – Timer/Counter Control Register B, CS00: Clock Select, clk I/O
//Waveform Generation Mode, Mode 2 CTC
// On ATtiny88, TCCR0B doesn't exist — clock select bits (CS01, CS00) are in TCCR0A.
// This sets the prescaler to 1, so the timer runs at full system clock (16 MHz).
#define SET_TIMER_TCCROB TCCR0A |= (1 << CS01) | (1 << CS00)
#define CTC_TIMER_VECTOR TIMER0_COMPA_vect //interrupt vector for match event, OCR0A comparison and Timer/Counter 0
@ -411,10 +413,10 @@
#define PIN_WFCK_READ (PINB & (1<<PINB1))
// Handling and use of the LED pin
//#define LED_RUN
//#define PIN_LED_OUTPUT DDRB |= (1<<DDB5)
//#define PIN_LED_ON PORTB |= (1<<PB5)
//#define PIN_LED_OFF PORTB &= ~(1<<PB5)
#define LED_RUN
#define PIN_LED_OUTPUT DDRB |= (1<<DDB5)
#define PIN_LED_ON PORTB |= (1<<PB5)
#define PIN_LED_OFF PORTB &= ~(1<<PB5)
// Handling the BIOS patch
@ -750,4 +752,4 @@
#endif
#endif

6
PSNee_V8.6/PSNee_V8.6/PSNee_V8.6.ino
View File

@ -20,7 +20,7 @@
//#define SCPH_5500 // DX - D0, AX - A5. BIOS ver. 3.0j, CRC FF3EEB8C
//#define SCPH_3500_5000 // DX - D0, for 40-pin BIOS: AX - A4, for 32-pin BIOS: AX - A5. BIOS ver. 2.2j, CRC 24FC7E17 | 2.1j, CRC BC190209
//#define SCPH_3000 // DX - D5, for 40-pin BIOS: AX - A6, AY - A7, for 32-pin BIOS: AX - A7, AY - A8. BIOS ver. 1.1j, CRC 3539DEF6
//#define SCPH_1000 // DX - D5, for 40-pin BIOS: AX - A6, AY - A7, for 32-pin BIOS: AX - A7, AY - A8. BIOS ver. 1.0j, CRC 3B601FC8
#define SCPH_1000 // DX - D5, for 40-pin BIOS: AX - A6, AY - A7, for 32-pin BIOS: AX - A7, AY - A8. BIOS ver. 1.0j, CRC 3B601FC8
//------------------------------------------------------------------------------------------------
@ -30,7 +30,7 @@
//#define ATmega328_168
//#define ATmega32U4_16U4
//#define ATtiny85_45_25
#define ATtiny88_48
/*
Fuses:
ATmega - H: DF, L: EE, E: FD.
@ -71,7 +71,7 @@
// pointer and variable section
//------------------------------------------------------------------------------------------------
#include "MUC.h"
#include "MCU.h"
#include "settings.h"
#include "BIOS_patching.h"