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@ -262,3 +262,58 @@ rf: read dma to 36777, count 7000; disk_addr 455000 (154112) EMA 45 DMA 5000
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rf: write dma to 25777, count 6000; disk_addr 16000 (7168) EMA 1 DMA 6000
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xxx boom 5; cycles 1100000
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-----------------
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xxx rf_go! read (rf_da 20000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 20000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 310000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! write (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 30000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 40000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 0, wc 0, ma 7777)
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xxx rf_go! read (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 310000, wc 7400, ma 5377)
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xxx rf_go! write (rf_da 16000, wc 6000, ma 5777)
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xxx rf_go! read (rf_da 0, wc 0, ma 7777)
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xxx rf_go! read (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 310400, wc 7400, ma 5377)
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xxx rf_go! write (rf_da 16000, wc 6000, ma 5777)
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xxx rf_go! read (rf_da 0, wc 0, ma 7777)
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xxx rf_go! read (rf_da 321400, wc 7400, ma 7777)
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xxx rf_go! read (rf_da 325000, wc 5000, ma 377)
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xxx rf_go! read (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! read (rf_da 310400, wc 7400, ma 5377)
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xxx rf_go! read (rf_da 330000, wc 4400, ma 3377)
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xxx rf_go! read (rf_da 333400, wc 7000, ma 6777)
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xxx rf_go! write (rf_da 16000, wc 6000, ma 5777)
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rf: start! read disk_addr 0000000 (000 0000) (ma 06604 wc 7601)
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rf: start! read disk_addr 0000000 (000 0000) (ma 07004 wc 0001)
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rf: start! read disk_addr 0020000 (002 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0020000 (002 0000) (ma 00000 wc 0001)
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rf: start! read disk_addr 0020000 (002 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0310000 (031 0000) (ma 10000 wc 0001)
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rf: start! read disk_addr 0010000 (001 0000) (ma 10000 wc 0001)
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rf: start! write disk_addr 0010000 (001 0000) (ma 10000 wc 0001)
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rf: start! read disk_addr 0030000 (003 0000) (ma 00000 wc 0001)
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rf: start! read disk_addr 0040000 (004 0000) (ma 10000 wc 0001)
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rf: start! read disk_addr 0000000 (000 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0010000 (001 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0310000 (031 0000) (ma 25400 wc 7401)
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rf: start! write disk_addr 0016000 (001 6000) (ma 26000 wc 6001)
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rf: start! read disk_addr 0000000 (000 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0010000 (001 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0310400 (031 0400) (ma 25400 wc 7401)
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rf: start! write disk_addr 0016000 (001 6000) (ma 26000 wc 6001)
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rf: start! read disk_addr 0000000 (000 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0321400 (032 1400) (ma 30000 wc 7401)
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rf: start! read disk_addr 0325000 (032 5000) (ma 30400 wc 5001)
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rf: start! read disk_addr 0010000 (001 0000) (ma 20000 wc 0001)
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rf: start! read disk_addr 0310400 (031 0400) (ma 25400 wc 7401)
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rf: start! read disk_addr 0330000 (033 0000) (ma 33400 wc 4401)
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rf: start! read disk_addr 0333400 (033 3400) (ma 37000 wc 7001)
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rf: start! write disk_addr 0016000 (001 6000) (ma 26000 wc 6001)
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rf: start! read disk_addr 0000000 (000 0000) (ma 20000 wc 0001)
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@ -57,11 +57,13 @@ module fake_uart(clk, reset, state,
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begin
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if (t_state == 1)
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begin
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t_delay = 20;
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t_delay = 38/*20*/;
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end
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if (t_delay > 0)
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begin
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t_delay = t_delay - 1;
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if (state == 4'b0001)
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t_delay = t_delay - 1;
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// t_delay = t_delay - 1;
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if (t_delay == 0)
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begin
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t_done = 1;
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@ -89,7 +91,7 @@ module fake_uart(clk, reset, state,
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// begin
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// $display("xxx want input; cycles %d", cycles);
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// end
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if (r_index == r_count && cycles == 200000)
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if (r_index == r_count && cycles == 110000/*200000*/)
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begin
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rdata[0] = "L";
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rdata[1] = "O";
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@ -110,7 +112,7 @@ module fake_uart(clk, reset, state,
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r_refires = 1;
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$display("xxx boom 1; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 300000)
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if (r_index == r_count && cycles == 120000/*300000*/)
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begin
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rdata[0] = "\215";
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r_index = 0;
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@ -118,7 +120,7 @@ module fake_uart(clk, reset, state,
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r_refires = 2;
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$display("xxx boom 2; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 400000)
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if (r_index == r_count && cycles == 130000/*400000*/)
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begin
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rdata[0] = "\215";
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r_index = 0;
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@ -127,8 +129,9 @@ module fake_uart(clk, reset, state,
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$display("xxx boom 3; cycles %d", cycles);
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end
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//`define msg_rcat 1
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`define msg_rfocal 1
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if (r_index == r_count && cycles == 500000)
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//`define msg_rfocal 1
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`define msg_pald 1
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if (r_index == r_count && cycles == 300000/*500000*/)
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begin
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`ifdef msg_rcat
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rdata[0] = "R";
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@ -151,11 +154,22 @@ module fake_uart(clk, reset, state,
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rdata[7] = "\215";
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r_index = 0;
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r_count = 8;
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`endif
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`ifdef msg_pald
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rdata[0] = "R";
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rdata[1] = " ";
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rdata[2] = "P";
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rdata[3] = "A";
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rdata[4] = "L";
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rdata[5] = "D";
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rdata[6] = "\215";
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r_index = 0;
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r_count = 7;
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`endif
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r_refires = 4;
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$display("xxx boom 4; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 600000)
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if (r_index == r_count && cycles == 400000/*600000*/)
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begin
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rdata[0] = "\215";
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r_index = 0;
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@ -6,14 +6,6 @@
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test_pdp8.v
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exit 0
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../cver/gplcver-2.12a.src/bin/cver \
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+loadvpi=../pli/rf/pli_rf.so:vpi_compat_bootstrap \
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+showpc \
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+cycles=2000000 \
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+pc=07400 \
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test_pdp8.v
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exit 0
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# +loadvpi=../pli/disassemble/pli_disassemble.so:vpi_compat_bootstrap \
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#
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@ -336,11 +336,10 @@ module test;
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$finish;
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if (show_one_pc)
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#1 $display("pc %o ir %o l%b ac %o ion %o (IF%o DF%o UF%o SF%o IB%o UB%o) %b",
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#1 $display("pc %o ir %o l%b ac %o ion %o (IF%o DF%o UF%o SF%o IB%o UB%o)",
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cpu.pc, cpu.mb,
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cpu.l, cpu.ac, cpu.interrupt_enable,
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cpu.IF, cpu.DF, cpu.UF, cpu.SF, cpu.IB, cpu.UB,
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cpu.interrupt_inhibit_delay);
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cpu.IF, cpu.DF, cpu.UF, cpu.SF, cpu.IB, cpu.UB);
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`ifdef xxx
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if (show_one_pc)
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@ -1,8 +1,7 @@
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load ../tss8/tss8_init.bin
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set rf enabled
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set df disabled
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attach rf rf.dsk
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run 24200
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boot rf
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exit
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