fixed bug; user osr/hlt didn't trap
This commit is contained in:
brad
parent
b734f58acd
commit
e1cd575b11
@ -41,37 +41,39 @@ module bootrom(clk, reset, addr, data_out, rd, selected);
|
||||
$display("rom: active %b delay %o addr %o", active, delay, addr);
|
||||
`endif
|
||||
|
||||
if (rd)
|
||||
`ifdef bootrom_tss8
|
||||
if (rd)
|
||||
case (addr)
|
||||
// copy tss8 bootstrap to ram and jump to it
|
||||
// (see ../rom/rom.pal)
|
||||
12'o7400: data = 12'o7240;
|
||||
12'o7401: data = 12'o1223;
|
||||
12'o7401: data = 12'o1224;
|
||||
12'o7402: data = 12'o3010;
|
||||
12'o7403: data = 12'o1216;
|
||||
12'o7403: data = 12'o1217;
|
||||
12'o7404: data = 12'o3410;
|
||||
12'o7405: data = 12'o1217;
|
||||
12'o7405: data = 12'o1220;
|
||||
12'o7406: data = 12'o3410;
|
||||
12'o7407: data = 12'o1220;
|
||||
12'o7407: data = 12'o1221;
|
||||
12'o7410: data = 12'o3410;
|
||||
12'o7411: data = 12'o1221;
|
||||
12'o7411: data = 12'o1222;
|
||||
12'o7412: data = 12'o3410;
|
||||
12'o7413: data = 12'o1222;
|
||||
12'o7413: data = 12'o1223;
|
||||
12'o7414: data = 12'o3410;
|
||||
12'o7415: data = 12'o5623;
|
||||
12'o7416: data = 12'o7600;
|
||||
12'o7417: data = 12'o6603;
|
||||
12'o7420: data = 12'o6622;
|
||||
12'o7421: data = 12'o5352;
|
||||
12'o7422: data = 12'o5752;
|
||||
12'o7423: data = 12'o7750;
|
||||
12'o7415: data = 12'o7300;
|
||||
12'o7416: data = 12'o5624;
|
||||
12'o7417: data = 12'o7600;
|
||||
12'o7420: data = 12'o6603;
|
||||
12'o7421: data = 12'o6622;
|
||||
12'o7422: data = 12'o5352;
|
||||
12'o7423: data = 12'o5752;
|
||||
12'o7424: data = 12'o7750;
|
||||
endcase // case(addr)
|
||||
|
||||
if (rd && active && addr == 12'o7415)
|
||||
if (rd && active && addr == 12'o7416)
|
||||
deactivate = 1;
|
||||
`endif
|
||||
`ifdef bootrom_uart
|
||||
if (rd)
|
||||
case (addr)
|
||||
// run simple uart test
|
||||
12'o7400: data = 12'o7240;
|
||||
|
||||
19
rtl/pdp8.v
19
rtl/pdp8.v
@ -287,7 +287,9 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
|
||||
|
||||
wire interrupt_inhibit;
|
||||
wire skip_condition;
|
||||
|
||||
|
||||
wire user_interrupt;
|
||||
|
||||
wire fetch; // memory cycle to fetch instruction
|
||||
wire deferred;// memory cycle to get address of operand
|
||||
wire execute;// memory cycle to getch (store) operand and execute isn
|
||||
@ -349,6 +351,12 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
|
||||
(opr && (mb[8] && !mb[0]) && (skip_condition ^ mb[3])) ||
|
||||
(iot && (io_skip || interrupt_skip));
|
||||
|
||||
assign user_interrupt =
|
||||
// i/o operation
|
||||
(UF && iot) ||
|
||||
// group 2 - user mode halt or osr
|
||||
(UF && opr && (mb[8] & !mb[0]) && (mb[2] | mb[1]));
|
||||
|
||||
// cpu states
|
||||
parameter [3:0]
|
||||
F0 = 4'b0000,
|
||||
@ -671,6 +679,7 @@ $display("SINT: UI %b, state %b", UI, state);
|
||||
IF <= 3'b000;
|
||||
DF <= 3'b000;
|
||||
UF <= 1'b0;
|
||||
UB <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
@ -816,7 +825,9 @@ $display("SINT: UI %b, state %b", UI, state);
|
||||
|
||||
if (io_data_avail)
|
||||
begin
|
||||
`ifdef debug
|
||||
if (0) $display("io_data clock %o", io_data_in);
|
||||
`endif
|
||||
ac <= io_data_in;
|
||||
end
|
||||
|
||||
@ -827,16 +838,18 @@ $display("SINT: UI %b, state %b", UI, state);
|
||||
|
||||
end // if (iot)
|
||||
|
||||
if (io_interrupt || (iot && UF))
|
||||
if (io_interrupt || user_interrupt)
|
||||
begin
|
||||
`ifdef debug
|
||||
if (0)
|
||||
$display("F1 - set interrupt; (%b %b %b; %b %b; %b %b %b)",
|
||||
$display("xxx F1 interrupt; (%b %b %b; %b %b; %b %b %b)",
|
||||
interrupt_enable,
|
||||
interrupt_inhibit,
|
||||
interrupt_cycle,
|
||||
io_interrupt, iot && UF,
|
||||
IB_pending, UB_pending,
|
||||
interrupt_inhibit_delay);
|
||||
`endif
|
||||
|
||||
interrupt <= 1;
|
||||
end
|
||||
|
||||
@ -73,9 +73,12 @@ module pdp8_kw(clk, reset, iot, state, mb,
|
||||
end
|
||||
|
||||
`ifdef sim_time_kw
|
||||
integer c_cycles;
|
||||
integer c_cycles, cycles;
|
||||
initial
|
||||
c_cycles = 1;
|
||||
begin
|
||||
c_cycles = 0;
|
||||
cycles = 0;
|
||||
end
|
||||
`endif
|
||||
|
||||
//
|
||||
@ -94,14 +97,14 @@ module pdp8_kw(clk, reset, iot, state, mb,
|
||||
begin
|
||||
`ifdef sim_time_kw
|
||||
// to make sim deterministic, count cpu fetches
|
||||
cycles = cycles + 1;
|
||||
c_cycles = c_cycles + 1;
|
||||
if (c_cycles == 16001)
|
||||
if (c_cycles > 16004)
|
||||
begin
|
||||
c_cycles = 0;
|
||||
assert_kw_flag = 1;
|
||||
$display("kw8i assert assert_kw_flag sim");
|
||||
end
|
||||
else
|
||||
assert_kw_flag = 0;
|
||||
`endif
|
||||
end
|
||||
|
||||
@ -129,7 +132,7 @@ module pdp8_kw(clk, reset, iot, state, mb,
|
||||
3'o3:
|
||||
begin
|
||||
`ifdef debug
|
||||
$display("kw8i: CSCF");
|
||||
$display("kw8i: CSCF %d", c_cycles);
|
||||
`endif
|
||||
kw_flag <= 1'b0;
|
||||
end
|
||||
@ -153,12 +156,13 @@ module pdp8_kw(clk, reset, iot, state, mb,
|
||||
|
||||
F3:
|
||||
begin
|
||||
if (assert_kw_flag && kw_clk_en)
|
||||
if (assert_kw_flag/* && kw_clk_en*/)
|
||||
begin
|
||||
kw_flag <= 1;
|
||||
`ifdef debug
|
||||
$display("kw8i: assert_kw_flag %t\n", $time);
|
||||
if (kw_flag == 0) $display("kw8i: set kw_flag! %t\n", $time);
|
||||
$display("kw8i: assert_kw_flag %t", $time);
|
||||
if (kw_flag == 0) $display("kw8i: set kw_flag! cycles %d, %t",
|
||||
cycles, $time);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
@ -175,10 +179,21 @@ module pdp8_kw(clk, reset, iot, state, mb,
|
||||
assert_kw_flag <= 0;
|
||||
else
|
||||
if (assert_kw_ctr_zero)
|
||||
assert_kw_flag <= 1;
|
||||
begin
|
||||
`ifdef debug
|
||||
$display("kw8i assert assert_kw_flag rtl");
|
||||
`endif
|
||||
assert_kw_flag <= 1;
|
||||
end
|
||||
else
|
||||
if (state == F3)
|
||||
assert_kw_flag <= 0;
|
||||
begin
|
||||
`ifdef debug
|
||||
if (assert_kw_flag)
|
||||
$display("kw8i deassert assert_kw_flag");
|
||||
`endif
|
||||
assert_kw_flag <= 0;
|
||||
end
|
||||
|
||||
`ifndef sim_time_kw
|
||||
assign assert_kw_ctr_zero = kw_ctr == 0;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user