verif/Makefile

@@ -0,0 +1,3 @@
+clean:
+	rm -f verilog.log
+	rm -f *.vcd

verif/run_io.v

@@ -0,0 +1,83 @@
+// run_io.v
+// testing top end for pdp8_io.v
+//
+
+`include "../rtl/pdp8_tt.v"
+`include "../rtl/pdp8_rf.v"
+`include "../rtl/pdp8_io.v"
+
+
+`timescale 1ns / 1ns
+
+module test;
+
+   reg clk, reset;
+
+   wire [11:0] io_data_in;
+   wire [11:0] io_data_out;
+   wire        io_data_avail;
+   wire        io_interrupt;
+   wire        io_skip;
+   wire        io_clear_ac;
+   wire [5:0]  io_select;
+   
+   wire        iot;
+   wire [3:0]  state;
+   wire [11:0] mb;
+   
+   pdp8_io io(.clk(clk),
+	      .reset(reset),
+	      .iot(iot),
+	      .state(state),
+	      .mb(mb),
+	      .io_data_in(io_data_out),
+	      .io_data_out(io_data_in),
+	      .io_select(io_select),
+	      .io_data_avail(io_data_avail),
+	      .io_interrupt(io_interrupt),
+	      .io_skip(io_skip),
+	      .io_clear_ac(io_clear_ac));
+
+  initial
+    begin
+      $timeformat(-9, 0, "ns", 7);
+
+      $dumpfile("pdp8_io.vcd");
+      $dumpvars(0, test.io);
+    end
+
+  initial
+    begin
+      clk = 0;
+      reset = 0;
+
+    #1 begin
+         reset = 1;
+       end
+
+    #50 begin
+         reset = 0;
+       end
+  
+      #3000 $finish;
+    end
+
+  always
+    begin
+      #10 clk = 0;
+      #10 clk = 1;
+    end
+
+  //----
+  integer cycle;
+
+  initial
+    cycle = 0;
+
+  always @(posedge io.clk)
+    begin
+      cycle = cycle + 1;
+    end
+
+endmodule
+

verif/run_rf.v

@@ -2,7 +2,7 @@
 // testing top end for pdp8_rf.v
 //
 
-`include "pdp8_rf.v"
+`include "../rtl/pdp8_rf.v"
 
 
 `timescale 1ns / 1ns

verif/run_top.v

@@ -0,0 +1,119 @@
+// run_top.v
+// testing top end for pdp8.v
+//
+
+`include "pdp8.v"
+`include "pdp8_io.v"
+`include "pdp8_ram.v"
+
+`timescale 1ns / 1ns
+
+module test;
+
+
+   reg	rs232_txd;
+   wire rs232_rxd;
+
+   reg [3:0] button;
+
+   wire [7:0] led;
+   reg 	      sysclk;
+
+   wire [7:0] sevenseg;
+   wire [3:0] sevenseg_an;
+
+   reg [7:0]  slideswitch;
+
+   wire [17:0] ram_a;
+   wire        ram_oe_n;
+   wire        ram_we_n;
+
+   wire [15:0] ram1_io;
+   wire        ram1_ce_n;
+   wire        ram1_ub_n;
+   wire        ram1_lb_n;
+
+   wire [15:0] ram2_io;
+   wire        ram2_ce_n;
+   wire        ram2_ub_n;
+   wire        ram2_lb_n;
+   
+   wire [15:0] ide_data_bus;
+   wire        ide_dior, ide_diow;
+   wire [1:0]  ide_cs;
+   wire [2:0]  ide_da;
+
+   top top(.rs232_txd(rs232_txd),
+	   .rs232_rxd(rs232_rxd),
+	   .button(button),
+	   .led(led),
+	   .sysclk(sysclk),
+	   .sevenseg(sevenseg),
+	   .sevenseg_an(sevenseg_an),
+	   .slideswitch(slideswitch),
+	   .ram_a(ram_a),
+	   .ram_oe_n(ram_oe_n),
+	   .ram_we_n(ram_we_n),
+
+	   .ram1_io(ram1_io),
+	   .ram1_ce_n(ram1_ce_n),
+	   .ram1_ub_n(ram1_ub_n),
+	   .ram1_lb_n(ram1_lb_n),
+
+	   .ram2_io(ram2_io),
+	   .ram2_ce_n(ram2_ce_n),
+	   .ram2_ub_n(ram2_ub_n),
+	   .ram2_lb_n(ram2_lb_n),
+
+	   .ide_data_bus(ide_data_bus),
+	   .ide_dior(ide_dior),
+	   .ide_diow(ide_diow),
+	   .ide_cs(ide_cs),
+	   .ide_da(ide_da));
+
+  initial
+    begin
+      $timeformat(-9, 0, "ns", 7);
+
+      $dumpfile("pdp8.vcd");
+      $dumpvars(0, test.cpu);
+    end
+
+  initial
+    begin
+       sysclk = 0;
+      #3000000 $finish;
+    end
+
+  always
+    begin
+      #10 sysclk = 0;
+      #10 sysclk = 1;
+    end
+
+  //----
+  integer cycle;
+
+  initial
+    cycle = 0;
+
+  always @(posedge top.cpu.clk)
+   if (top.cpu.state == 4'b0000)
+    begin
+      cycle = cycle + 1;
+//      #1 $display("#%d, r%b s%d, pc %o ir%o ma %o mb %o j%b l%b ac %o, i%b/%b",
+//		cycle, top.cpu.run, top.cpu.state, top.cpu.pc,
+//		top.cpu.ir, top.cpu.ma, top.cpu.mb, top.cpu.jmp, top.cpu.l, top.cpu.ac,
+//		top.cpu.interrupt_enable, top.cpu.interrupt);
+       //#1 $display("   io_data_in %o, io_data_out %o",
+       //io_data_in, io_data_out);
+
+      #1 $display("pc %o ir %o l %b ac %o ion %o",
+		  top.cpu.pc, top.cpu.mb, top.cpu.l, top.cpu.ac, top.cpu.interrupt_enable);
+
+       if (state == 4'b1100)
+	 $finish;
+    end
+
+endmodule
+

verif/run_tt.v

@@ -0,0 +1,79 @@
+// run_tt.v
+// testing top end for pdp8_tt.v
+//
+
+`include "../rtl/pdp8_tt.v"
+
+
+`timescale 1ns / 1ns
+
+module test;
+
+   reg clk, reset;
+
+   wire [11:0] io_data_in;
+   wire [11:0] io_data_out;
+   wire        io_data_avail;
+   wire        io_interrupt;
+   wire        io_skip;
+   wire [5:0]  io_select;
+   
+   wire        iot;
+   wire [3:0]  state;
+   wire [11:0] mb;
+   
+   pdp8_tt tt(.clk(clk),
+	      .reset(reset),
+	      .iot(iot),
+	      .state(state),
+	      .mb(mb),
+	      .io_data_in(io_data_out),
+	      .io_data_out(io_data_in),
+	      .io_select(io_select),
+	      .io_data_avail(io_data_avail),
+	      .io_interrupt(io_interrupt),
+	      .io_skip(io_skip));
+
+  initial
+    begin
+      $timeformat(-9, 0, "ns", 7);
+
+      $dumpfile("pdp8_tt.vcd");
+      $dumpvars(0, test.tt);
+    end
+
+  initial
+    begin
+      clk = 0;
+      reset = 0;
+
+    #1 begin
+         reset = 1;
+       end
+
+    #50 begin
+         reset = 0;
+       end
+  
+      #3000 $finish;
+    end
+
+  always
+    begin
+      #10 clk = 0;
+      #10 clk = 1;
+    end
+
+  //----
+  integer cycle;
+
+  initial
+    cycle = 0;
+
+  always @(posedge tt.clk)
+    begin
+      cycle = cycle + 1;
+    end
+
+endmodule
+