revamped clocking of internal state
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brad
parent
f30156e5bc
commit
4e2201fcf8
210
rtl/pdp8_rf.v
210
rtl/pdp8_rf.v
@ -478,17 +478,27 @@ module pdp8_rf(clk, reset, iot, state, mb,
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reg db_done;
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wire dma_done;
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reg clear_db_done;
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reg set_db_done;
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reg [14:0] dma_addr;
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reg [11:0] dma_wc;
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reg [19:0] disk_addr;
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reg load_disk_addr;
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reg incr_disk_addr;
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wire [7:0] buffer_addr;
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reg [19:8] buffer_disk_addr;
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reg buffer_dirty;
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reg [11:0] buffer_hold;
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reg load_buffer_hold;
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reg set_buffer_addr;
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reg set_buffer_dirty;
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wire buffer_matches_DMA;
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wire buffer_rd;
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wire buffer_wr;
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@ -811,21 +821,32 @@ is_read <= 1'b1;
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// comb logic to create 'next state'
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always @(*)
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begin
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db_next_state = DB_idle;
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// load_disk_addr = 0;
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db_next_state = db_state;
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load_disk_addr = 0;
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incr_disk_addr = 0;
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set_buffer_addr = 0;
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set_buffer_dirty = 0;
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load_buffer_hold = 0;
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case (db_state)
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DB_idle:
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begin
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if (dma_start)
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db_next_state = DB_start_xfer1;
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// if (ram_done) load_disk_addr = 1;
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end
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if (dma_start)
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db_next_state = DB_start_xfer1;
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DB_start_xfer1:
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db_next_state = ram_done ? DB_start_xfer2 : DB_start_xfer1;
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if (ram_done)
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begin
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clear_db_done = 1;
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load_disk_addr = 1;
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db_next_state = DB_start_xfer2;
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end
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DB_start_xfer2:
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db_next_state = ram_done ? DB_start_xfer3 : DB_start_xfer2;
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if (ram_done)
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begin
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set_db_done = 1;
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db_next_state = DB_start_xfer3;
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end
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DB_start_xfer3:
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db_next_state = is_read ? DB_check_xfer_read : DB_begin_xfer_write;
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@ -838,48 +859,67 @@ is_read <= 1'b1;
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db_next_state = buffer_dirty ?
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DB_write_old_page :
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DB_read_new_page;
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// if (ram_done) load_disk_addr = 1;
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end
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DB_next_xfer_read:
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db_next_state = ram_done ?
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(dma_done ? DB_done_xfer : DB_next_xfer_incr) :
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DB_next_xfer_read;
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if (ram_done)
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begin
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incr_disk_addr = 1;
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db_next_state = dma_done ? DB_done_xfer : DB_next_xfer_incr;
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end
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DB_next_xfer_incr:
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// if (dma_done)
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// db_next_state = DB_done_xfer;
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// else
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db_next_state = is_read ? DB_check_xfer_read:DB_begin_xfer_write;
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DB_begin_xfer_write:
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db_next_state = ram_done ? DB_check_xfer_write:DB_begin_xfer_write;
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if (ram_done)
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begin
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load_buffer_hold = 1;
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db_next_state = DB_check_xfer_write;
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end
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DB_check_xfer_write:
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if (buffer_matches_DMA)
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db_next_state = dma_done ? DB_done_xfer : DB_next_xfer_incr;
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else
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db_next_state = buffer_dirty ? DB_write_old_page:DB_read_new_page;
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if (buffer_matches_DMA)
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begin
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set_buffer_dirty = 1;
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incr_disk_addr = 1;
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db_next_state = dma_done ? DB_done_xfer : DB_next_xfer_incr;
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end
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else
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db_next_state = buffer_dirty ?
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DB_write_old_page :
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DB_read_new_page;
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DB_done_xfer:
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db_next_state = ram_done ? DB_done_xfer1 : DB_done_xfer;
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if (ram_done)
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db_next_state = DB_done_xfer1;
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DB_done_xfer1:
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db_next_state = ram_done ? DB_done_xfer2 : DB_done_xfer1;
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if (ram_done)
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db_next_state = DB_done_xfer2;
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DB_done_xfer2:
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db_next_state = state == F2 ? DB_done_xfer3 : DB_done_xfer2;
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if (state == F2)
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db_next_state = DB_done_xfer3;
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DB_done_xfer3:
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db_next_state = DB_idle;
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DB_read_new_page:
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db_next_state = ide_done ?
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(is_read ? DB_check_xfer_read:DB_check_xfer_write) :
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DB_read_new_page;
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if (ide_done)
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begin
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set_buffer_addr = 1;
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db_next_state = is_read ?
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DB_check_xfer_read :
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DB_check_xfer_write;
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end
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DB_write_old_page:
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db_next_state = ide_done ? DB_read_new_page : DB_write_old_page;
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if (ide_done)
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begin
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set_buffer_addr = 1;
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db_next_state = DB_read_new_page;
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end
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endcase
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end
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@ -893,32 +933,20 @@ is_read <= 1'b1;
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assign dma_done = dma_wc == 12'o0000;
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// general state
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// general state - wc & ca
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always @(posedge clk)
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if (reset)
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begin
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db_done <= 1'b1;
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dma_wc <= 12'b0;
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dma_addr <= 14'b0;
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disk_addr <= 20'b0;
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buffer_disk_addr[19:8] <= 12'b111111111111;
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buffer_dirty <= 1'b0;
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buffer_hold <= 12'b0;
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end
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else
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begin
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case (db_state)
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DB_idle:
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begin
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end
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DB_start_xfer1:
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begin
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disk_addr <= {EMA, DMA};
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dma_wc <= ram_in + 12'o0001;
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db_done <= 0;
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`ifdef debug
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if (ram_done) $display("rf: read wc %o", ram_in);
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`endif
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@ -936,17 +964,14 @@ is_read <= 1'b1;
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DB_start_xfer3:
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begin
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// this state might be not be needed
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$display("rf: start! disk_addr %o (%o %o)", disk_addr, EMA, DMA);
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`ifdef debug
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$display("rf: start! disk_addr %o (%o %o)",
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disk_addr, EMA, DMA);
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`endif
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end
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DB_begin_xfer_write:
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begin
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buffer_hold <= ram_in;
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end
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DB_next_xfer_incr:
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begin
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// disk_addr <= disk_addr + 20'b1;
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dma_addr[11:0] <= dma_addr[11:0] + 12'o00001;
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dma_wc <= dma_wc + 12'b1;
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`ifdef debug_rf
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@ -956,9 +981,7 @@ is_read <= 1'b1;
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DB_next_xfer_read:
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begin
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if (ram_done)
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disk_addr <= disk_addr + 20'b1;
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/* snoop for our wc & ca */
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if (dma_addr == 12'o7750 && ram_done)
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begin
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dma_wc <= buff_out;
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@ -977,53 +1000,66 @@ is_read <= 1'b1;
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`endif
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end
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DB_check_xfer_write:
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begin
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buffer_dirty <= 1;
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if (buffer_matches_DMA)
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disk_addr <= disk_addr + 20'b1;
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end
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`ifdef debug
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DB_done_xfer:
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if (ram_done) $display("rf: write wc %o", dma_wc);
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DB_done_xfer1:
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if (ram_done) $display("rf: write ca %o", dma_addr);
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`endif
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DB_done_xfer2:
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begin
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`ifdef debug
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$display("rf: done");
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$display("rf: done");
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`endif
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db_done <= 1;
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end
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DB_read_new_page:
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begin
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buffer_dirty <= 0;
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buffer_disk_addr[19:8] <= disk_addr[19:8];
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end
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DB_write_old_page:
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begin
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buffer_dirty <= 0;
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buffer_disk_addr[19:8] <= disk_addr[19:8];
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end
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endcase
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end
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//
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// always @(posedge clk)
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// if (reset)
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// disk_addr <= 0;
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// else
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// if (load_disk_addr)
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// disk_addr <= {EMA, DMA};
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// else
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// if (incr_disk_addr)
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// disk_addr <= disk_addr + 20'b1;
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always @(posedge clk)
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if (reset)
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buffer_hold <= 12'b0;
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else
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if (load_buffer_hold)
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buffer_hold <= ram_in;
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// done state
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always @(posedge clk)
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if (reset)
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db_done <= 1'b1;
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else
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if (clear_db_done)
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db_done <= 1'b0;
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else
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if (set_db_done)
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db_done <= 1'b1;
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// buffer address
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always @(posedge clk)
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if (reset)
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begin
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buffer_disk_addr[19:8] <= 12'b111111111111;
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buffer_dirty <= 1'b0;
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end
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else
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if (set_buffer_dirty)
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buffer_dirty <= 1'b1;
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else
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if (set_buffer_addr)
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begin
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buffer_dirty <= 1'b0;
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buffer_disk_addr[19:8] <= disk_addr[19:8];
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end
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// disk address
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always @(posedge clk)
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if (reset)
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disk_addr <= 0;
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else
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if (load_disk_addr)
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disk_addr <= {EMA, DMA};
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else
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if (incr_disk_addr)
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disk_addr <= disk_addr + 20'b1;
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//
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