github.com/lisper.cpus-pdp8
1
0
Fork 0
mirror of synced 2026-01-11 23:53:00 +00:00
Code Issues Releases Wiki Activity

basic focal working

Browse Source
This commit is contained in:
brad 2009-05-10 23:51:20 +00:00
parent 595692fe2b
commit 6b363bd84c
3 changed files with 51 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
cpu/pdp8.v
View File

@ -245,8 +245,8 @@ module pdp8(clk, reset,
* ac <= 0
*/
assign skip_condition = (mb[6] && ac[11]) ||
(mb[5] && ac == 0) ||
(mb[4] && l == 1);
(mb[5] && (ac == 12'b0)) ||
(mb[4] && l);
assign pc_incr =
(opr & !mb[8]) ||
@ -324,6 +324,7 @@ module pdp8(clk, reset,
pc <= 0;
else
begin
if (state == F1) $display("pc_skip %b", pc_skip);
//if (state == F1 || state == D3 || state == E3)
//$display(" pc <- %o", pc_mux);
pc <= pc_mux;
@ -419,10 +420,11 @@ module pdp8(clk, reset,
if (interrupt && interrupt_enable &&
!interrupt_inhibit && !interrupt_cycle)
begin
$display("interrupt; %b %b %b",
interrupt, interrupt_enable, interrupt_cycle);
$display("xxx interrupt, pc %o; %b %b %b",
pc, interrupt, interrupt_enable, interrupt_cycle);
interrupt_cycle <= 1;
interrupt <= 0;
interrupt_enable <= 0;
// simulate a jsr to 0
mb <= 12'o4000;
@ -436,7 +438,7 @@ module pdp8(clk, reset,
interrupt_cycle <= 0;
//?? interrupt_inhibit <= 0;
//?? ib_pending <= 0;
$display(" read ram %o -> %o", ram_addr, ram_data_in);
//$display("read ram [%o] -> %o", ram_addr, ram_data_in);
mb <= ram_data_in;
ir <= ram_data_in[11:9];
end
@ -542,16 +544,18 @@ module pdp8(clk, reset,
begin
if (mb[0]) // IAC
{l,ac} <= {l,ac} + 1'b1;
if (mb[3:1] == 3'b001) // BSW
{l,ac} <= {l,ac[5:0],ac[11:6]};
if (mb[3] && !mb[1]) // RAR
{l,ac} <= {ac[0],l,ac[11:1]};
if (mb[3] && mb[1]) // RTR
{l,ac} <= {ac[1:0],l,ac[11:2]};
if (mb[2] && !mb[1]) // RAL
{l,ac} <= {ac[11:0],l};
if (mb[2] && mb[1]) // RTL
{l,ac} <= {ac[10:0],l,ac[11]};
case (mb[3:1])
3'b001: // BSW
{l,ac} <= {l,ac[5:0],ac[11:6]};
3'b010: // RAL
{l,ac} <= {ac[11:0],l};
3'b011: // RTL
{l,ac} <= {ac[10:0],l,ac[11]};
3'b100: // RAR
{l,ac} <= {ac[0],l,ac[11:1]};
3'b101: // RTR
{l,ac} <= {ac[1:0],l,ac[11:2]};
endcase
end
if (!UF)
@ -617,7 +621,7 @@ module pdp8(clk, reset,
D0:
begin
$display(" read ram %o -> %o", ram_addr, ram_data_in);
$display("read ram [%o] -> %o", ram_addr, ram_data_in);
mb <= ram_data_in;
end
@ -631,7 +635,7 @@ module pdp8(clk, reset,
D2:
begin
// write ram
$display(" write ram %o <- %o", ram_addr, ram_data_out);
$display("write ram [%o] <- %o", ram_addr, ram_data_out);
end
D3:
@ -653,7 +657,7 @@ module pdp8(clk, reset,
E0:
begin
$display(" read ram %o -> %o", ram_addr, ram_data_in);
$display("read ram [%o] -> %o", ram_addr, ram_data_in);
mb <= ram_data_in;
end
@ -676,7 +680,7 @@ module pdp8(clk, reset,
E2:
begin
// write ram
$display(" write ram %o <- %o", ram_addr, ram_data_out);
$display("write ram [%o] <- %o", ram_addr, ram_data_out);
end
E3:
@ -685,7 +689,7 @@ module pdp8(clk, reset,
ac <= ac & mb;
else
if (tad)
{l,ac} <= ac + mb;
{l,ac} <= {l,ac} + {1'b0,mb};
else
if (dca)
ac <= 0;

27
cpu/pdp8_io.v
View File

@ -203,7 +203,7 @@ module pdp8_io(clk, reset, iot, state, mb,
reg rx_int, tx_int;
reg [12:0] rx_data, tx_data;
reg tx_delaying;
reg [3:0] tx_delay;
integer tx_delay;
parameter F0 = 4'b0000;
parameter F1 = 4'b0001;
@ -254,7 +254,7 @@ module pdp8_io(clk, reset, iot, state, mb,
io_data_out = io_data_in;
io_data_avail = 1;
if (state == F0 && iot)
if (state == F1 && iot)
case (io_select)
6'o03:
begin
@ -267,7 +267,10 @@ module pdp8_io(clk, reset, iot, state, mb,
6'o04:
if (mb[0])
io_skip = tx_int;
begin
io_skip = tx_int;
$display("xxx io_skip %b", tx_int);
end
6'o60:
case (mb[2:0])
@ -376,15 +379,22 @@ module pdp8_io(clk, reset, iot, state, mb,
6'o04:
begin
if (mb[0])
begin
end
if (mb[1])
tx_int <= 0;
begin
tx_int <= 0;
$display("xxx reset tx_int");
end
if (mb[2])
begin
tx_data <= io_data_in;
$display("xxx tx_data %o", io_data_in);
tx_int <= 1;
tx_delaying <= 1;
tx_delay <= 4'b1111;
$display("set tx_int");
tx_delay <= 98;
$display("xxx set tx_int");
end
end // case: 6'o04
@ -434,9 +444,10 @@ module pdp8_io(clk, reset, iot, state, mb,
if (tx_delaying)
begin
tx_delay <= tx_delay - 1;
if (tx_delay == 4'b0)
//$display("xxx delay %d", tx_delay);
if (tx_delay == 0)
begin
$display("iot2 %t, set io_interrupt", $time);
$display("iot2 %t, xxx set io_interrupt", $time);
tx_delaying <= 0;
io_interrupt <= 1;
end

13
cpu/run.v
View File

@ -106,16 +106,19 @@ module test;
cycle = 0;
always @(posedge cpu.clk)
// if (cpu.state == 4'b0000)
if (cpu.state == 4'b0000)
begin
cycle = cycle + 1;
#1 $display("#%d, r%b s%d, pc %o ir%o ma %o mb %o j%b l%b ac %o, i%b/%b",
cycle, cpu.run, cpu.state, cpu.pc,
cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac,
cpu.interrupt_enable, cpu.interrupt);
// #1 $display("#%d, r%b s%d, pc %o ir%o ma %o mb %o j%b l%b ac %o, i%b/%b",
// cycle, cpu.run, cpu.state, cpu.pc,
// cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac,
// cpu.interrupt_enable, cpu.interrupt);
//#1 $display(" io_data_in %o, io_data_out %o",
//io_data_in, io_data_out);
#1 $display("pc %o ir %o l %b ac %o ion %o",
cpu.pc, cpu.mb, cpu.l, cpu.ac, cpu.interrupt_enable);
if (state == 4'b1100)
$finish;
end