github.com/lisper.cpus-pdp8
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mirror of synced 2026-04-16 00:21:31 +00:00
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fixed several bugs for fpga version

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added sim_time check in reset code
fixed uart
runs hello uart test on fpga
This commit is contained in:
brad
2010-04-24 10:27:54 +00:00
parent 1ff40e5627
commit 78343d5643
6 changed files with 97 additions and 29 deletions
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36
rtl/bootrom.v
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@@ -2,6 +2,9 @@
// boot rom occupies one page from 7400 - 7577
//
//`define bootrom_tss8
`define bootrom_uart
module bootrom(clk, reset, addr, data_out, rd, selected);
input clk;
@@ -39,6 +42,7 @@ module bootrom(clk, reset, addr, data_out, rd, selected);
`endif
if (rd)
`ifdef bootrom_tss8
case (addr)
// copy tss8 bootstrap to ram and jump to it
// (see ../rom/rom.pal)
@@ -66,7 +70,37 @@ module bootrom(clk, reset, addr, data_out, rd, selected);
if (rd && addr == 12'o7415)
deactivate = 1;
`endif
`ifdef bootrom_uart
case (addr)
// run simple uart test
12'o7400: data = 12'o7240;
12'o7401: data = 12'o1215;
12'o7402: data = 12'o3010;
12'o7403: data = 12'o1216;
12'o7404: data = 12'o3007;
12'o7405: data = 12'o7200;
12'o7406: data = 12'o1410;
12'o7407: data = 12'o6046;
12'o7410: data = 12'o6041;
12'o7411: data = 12'o5210;
12'o7412: data = 12'o2007;
12'o7413: data = 12'o5205;
12'o7414: data = 12'o5214;
12'o7415: data = 12'o7417;
12'o7416: data = 12'o7766;
12'o7417: data = 12'o0215;
12'o7420: data = 12'o0212;
12'o7421: data = 12'o0310;
12'o7422: data = 12'o0305;
12'o7423: data = 12'o0314;
12'o7424: data = 12'o0314;
12'o7425: data = 12'o0317;
12'o7426: data = 12'o0241;
12'o7427: data = 12'o0215;
12'o7430: data = 12'o0212;
endcase // case(addr)
`endif
end
endmodule

4
rtl/brg.v
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@@ -12,8 +12,8 @@ module brg(clk, reset, tx_baud_clk, rx_baud_clk);
parameter BAUD = 16'd9600;
`ifdef sim_time
parameter RX_CLK_DIV = 13'd2;
parameter TX_CLK_DIV = 13'd2;
parameter RX_CLK_DIV = 13'd5;
parameter TX_CLK_DIV = 13'd5;
`else
parameter RX_CLK_DIV = SYS_CLK / (BAUD * 16 * 2);
parameter TX_CLK_DIV = SYS_CLK / (BAUD * 2);

4
rtl/debounce.v
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@@ -5,7 +5,11 @@ module debounce(clk, in, out);
input in;
output out;
`ifdef sim_time
reg [1:0] clkdiv;
`else
reg [14:0] clkdiv;
`endif
reg slowclk;
reg [9:0] hold;
reg onetime;

57
rtl/pdp8_tt.v
View File

@@ -8,8 +8,6 @@
`define debug_tt_data 1
`endif
//`define sim_time
module pdp8_tt(clk, brgclk, reset,
iot, state, mb,
io_data_in, io_data_out, io_select, io_selected,
@@ -77,7 +75,7 @@ module pdp8_tt(clk, brgclk, reset,
.tx_baud_clk(uart_tx_clk),
.rx_baud_clk(uart_rx_clk));
`ifdef sim_time
`ifdef use_fake_uart
//
fake_uart tt_uart(.clk(clk),
.reset(reset),
@@ -184,6 +182,20 @@ module pdp8_tt(clk, brgclk, reset,
end
else
begin
//
if (assert_tx_int)
begin
`ifdef debug_tt_int
$display("xxx set tx_int");
`endif
tx_int <= 1;
end
if (assert_rx_int)
begin
//$display("xxx set rx_int");
rx_int <= 1;
end
//
if (iot && state == F1)
begin
`ifdef debug_tt_reg
@@ -194,7 +206,7 @@ module pdp8_tt(clk, brgclk, reset,
case (io_select)
6'o03:
begin
if (mb[1])
if (mb[1] && ~assert_rx_int)
rx_int <= 1'b0;
end
@@ -203,12 +215,9 @@ module pdp8_tt(clk, brgclk, reset,
if (mb[0])
begin
end
if (mb[1])
if (mb[1] && ~assert_tx_int)
begin
if (assert_tx_int)
tx_int <= 1'b1;
else
tx_int <= 1'b0;
tx_int <= 1'b0;
`ifdef debug_tt_in
$display("xxx reset tx_int");
`endif
@@ -223,21 +232,21 @@ module pdp8_tt(clk, brgclk, reset,
end // case: 6'o04
endcase
end // if (iot && state == F1)
else
begin
if (assert_tx_int)
begin
`ifdef debug_tt_int
$display("xxx set tx_int");
`endif
tx_int <= 1;
end
if (assert_rx_int)
begin
//$display("xxx set rx_int");
rx_int <= 1;
end
end
// else
// begin
// if (assert_tx_int)
// begin
//`ifdef debug_tt_int
// $display("xxx set tx_int");
//`endif
// tx_int <= 1;
// end
// if (assert_rx_int)
// begin
// //$display("xxx set rx_int");
// rx_int <= 1;
// end
// end
end // else: !if(reset)

7
rtl/top.v
View File

@@ -49,7 +49,10 @@ module top(rs232_txd, rs232_rxd,
// -----------------------------------------------------------------
`define slower
`ifndef sim_time
`define slower
`endif
`ifdef slower
reg clk;
reg [24:0] clkdiv;
@@ -152,7 +155,7 @@ module top(rs232_txd, rs232_rxd,
.ext_ram_out(ext_ram_in));
pdp8_io io(.clk(clk),
.brgclk(clk),
.brgclk(sysclk),
.reset(reset),
.iot(iot),
.state(state),

18
rtl/uart.v
View File

@@ -212,6 +212,9 @@ module uart(clk, reset,
tx_over_run <= 1;
else
begin
`ifdef sim_time
$display("uart: tx_data %o", tx_data);
`endif
tx_reg <= tx_data;
tx_empty <= 0;
end
@@ -221,6 +224,21 @@ module uart(clk, reset,
begin
tx_cnt <= tx_cnt + 4'b1;
`ifdef sim_time
case (tx_cnt)
4'd0: $display("tx: start");
4'd1: $display("tx: %b", tx_reg[0]);
4'd2: $display("tx: %b", tx_reg[1]);
4'd3: $display("tx: %b", tx_reg[2]);
4'd4: $display("tx: %b", tx_reg[3]);
4'd5: $display("tx: %b", tx_reg[4]);
4'd6: $display("tx: %b", tx_reg[5]);
4'd7: $display("tx: %b", tx_reg[6]);
4'd8: $display("tx: %b", tx_reg[7]);
4'd9: $display("tx: done");
endcase
`endif
case (tx_cnt)
4'd0: tx_out <= 0;
4'd1: tx_out <= tx_reg[0];