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using top s3 ram

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This commit is contained in:
brad
2010-04-14 13:26:17 +00:00
parent fc6b7ec578
commit c5c41bb132
4 changed files with 211 additions and 33 deletions
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138
verif/ram_s3board.v Normal file
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@@ -0,0 +1,138 @@
//
// // simulate IS61LV25616AL-10T on s3board
// debug only
//
module ram_256kx16(a, io, ce_n, ub_n, lb_n, we_n, oe_n);
input [17:0] a;
inout [15:0] io;
input ce_n;
input ub_n;
input lb_n;
input we_n;
input oe_n;
reg [7:0] ram_h[262143:0];
reg [7:0] ram_l[262143:0];
assign io = { (oe_n | ub_n) ? 8'bz : ram_h[a],
(oe_n | lb_n) ? 8'bz : ram_l[a] };
always @(we_n or ce_n or ub_n or lb_n or a or a or io)
if (~we_n && ~ce_n)
begin
if (0)
$display("ram_256kx16: %t ce_n %b ub_n %b lb_n %b we_n %b oe_n %b",
$time, ce_n, ub_n, lb_n, we_n, oe_n);
`ifdef debug_ram_low
if (~ub_n && ~lb_n) $display("ram_256kx16: %t write %o <- %o", $time, a, io);
else
if (~ub_n) $display("ram_256kx16: writeh %o <- %o", a, io);
else
if (~lb_n) $display("ram_256kx16: writel %o <- %o", a, io);
`endif
if (~ub_n) ram_h[a] = io[15:8];
if (~lb_n) ram_l[a] = io[7:0];
end
`ifdef debug_ram_low
always @(we_n or ce_n or ub_n or lb_n or a or a or io)
if (we_n && ~ce_n)
begin
if (0)
$display("ram_256kx16: %t ce_n %b ub_n %b lb_n %b we_n %b oe_n %b",
$time, ce_n, ub_n, lb_n, we_n, oe_n);
if (~ub_n && ~lb_n) $display("ram_256kx16: read %o -> %o", a, io);
else
if (~ub_n) $display("ram_256kx16: readh %o -> %o", a, io[7:0]);
else
if (~lb_n) $display("ram_256kx16: readl %o -> %o", a, io[7:0]);
end
`endif
endmodule
module ram_s3board(ram_a, ram_oe_n, ram_we_n,
ram1_io, ram1_ce_n, ram1_ub_n, ram1_lb_n,
ram2_io, ram2_ce_n, ram2_ub_n, ram2_lb_n);
input [17:0] ram_a;
input ram_oe_n, ram_we_n;
inout [15:0] ram1_io;
inout [15:0] ram2_io;
input ram1_ce_n, ram1_ub_n, ram1_lb_n;
input ram2_ce_n, ram2_ub_n, ram2_lb_n;
// synthesis translate_off
integer i;
reg [15:0] v;
integer file;
reg [1023:0] str;
reg [1023:0] testfilename;
integer n;
initial
begin
for (i = 0; i < 32768/*8192*/; i=i+1)
begin
ram1.ram_h[i] = 7'b0;
ram1.ram_l[i] = 7'b0;
end
`ifdef __ICARUS__
`define no_scan
`endif
`ifdef verilator
`define no_scan
`endif
`ifdef no_scan
n = 0;
`else
n = $scan$plusargs("test=", testfilename);
`endif
if (n > 0)
begin
$display("ram_s3board: code filename: %s", testfilename);
file = $fopen(testfilename, "r");
while ($fscanf(file, "%o %o", i, v) > 0)
begin
//$display("ram_s3board[%0o] <- %o", i, v);
ram1.ram_h[i] = v[15:8];
ram1.ram_l[i] = v[7:0];
end
$fclose(file);
end
end
`ifdef debug_ram
always @(ram_a or ram_oe_n or ram1_ce_n or ram_we_n or ram1_io)
begin
if (0)
$display("ram_s3board: ce_n %b ub_n %b lb_n %b we_n %b oe_n %b",
ram1_ce_n, ram1_ub_n, ram1_lb_n, ram_we_n, ram_oe_n);
if (ram_oe_n == 0 && ram_we_n == 1)
$display("ram_s3board: read [%o] -> %o", ram_a, ram1_io);
if (ram_oe_n == 1 && ram_we_n == 0)
$display("ram_s3board: write [%o] <- %o", ram_a, ram1_io);
end
`endif
// synthesis translate_on
ram_256kx16 ram1(.a(ram_a), .io(ram1_io),
.ce_n(ram1_ce_n), .ub_n(ram1_ub_n), .lb_n(ram1_lb_n),
.we_n(ram_we_n), .oe_n(ram_oe_n));
ram_256kx16 ram2(.a(ram_a), .io(ram2_io),
.ce_n(ram2_ce_n), .ub_n(ram2_ub_n), .lb_n(ram2_lb_n),
.we_n(ram_we_n), .oe_n(ram_oe_n));
endmodule

1
verif/run.sh Executable file
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@@ -0,0 +1 @@
cver +showpc +cycles=500000 +test=tss8_init.mem +pc=24200 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >xx

57
verif/test_pdp8.v
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@@ -2,6 +2,9 @@
// test bench top end for pdp8.v
//
`define sim_time
//`define use_sim_model
`include "../rtl/pdp8_tt.v"
`include "../rtl/pdp8_rf.v"
`include "../rtl/pdp8_kw.v"
@@ -14,9 +17,14 @@
`include "../rtl/ide_disk.v"
`include "../rtl/ide.v"
`include "../rtl/ram_32kx12.v"
`include "../rtl/ram_256x12.v"
`ifdef use_sim_model
`include "../rtl/ram_32kx12.v"
`else
`include "../verif/ram_s3board.v"
`endif
`timescale 1ns / 1ns
module test;
@@ -48,6 +56,18 @@ module test;
wire ext_ram_done;
wire [11:0] ext_ram_out;
wire [17:0] sram_a;
wire sram_oe_n;
wire sram_we_n;
wire [15:0] sram1_io;
wire sram1_ce_n;
wire sram1_ub_n;
wire sram1_lb_n;
wire [15:0] sram2_io;
wire sram2_ce_n;
wire sram2_ub_n;
wire sram2_lb_n;
wire [15:0] ide_data_bus;
wire ide_dior, ide_diow;
wire [1:0] ide_cs;
@@ -103,13 +123,31 @@ module test;
.ide_data_bus(ide_data_bus));
pdp8_ram ram(.clk(clk),
.reset(reset),
.addr(ram_addr),
.data_in(ram_data_in),
.data_out(ram_data_out),
.rd(ram_rd),
.wr(ram_wr));
.reset(reset),
.addr(ram_addr),
.data_in(ram_data_in),
.data_out(ram_data_out),
.rd(ram_rd),
.wr(ram_wr),
.sram_a(sram_a),
.sram_oe_n(sram_oe_n), .sram_we_n(sram_we_n),
.sram1_io(sram1_io), .sram1_ce_n(sram1_ce_n),
.sram1_ub_n(sram1_ub_n), .sram1_lb_n(sram1_lb_n),
.sram2_io(sram2_io), .sram2_ce_n(sram2_ce_n),
.sram2_ub_n(sram2_ub_n), .sram2_lb_n(sram2_lb_n));
`ifndef use_sim_model
ram_s3board sram(.ram_a(sram_a),
.ram_oe_n(sram_oe_n),
.ram_we_n(sram_we_n),
.ram1_io(sram1_io),
.ram1_ce_n(sram1_ce_n),
.ram1_ub_n(sram1_ub_n), .ram1_lb_n(sram1_lb_n),
.ram2_io(sram2_io),
.ram2_ce_n(sram2_ce_n),
.ram2_ub_n(sram2_ub_n), .ram2_lb_n(sram2_lb_n));
`endif
reg [14:0] starting_pc;
reg [1023:0] arg;
@@ -117,10 +155,9 @@ module test;
initial
begin
$timeformat(-9, 0, "ns", 7);
$timeformat(-9, 0, "ns", 7);
$dumpfile("test_pdp8.vcd");
// $dumpvars(0, test.cpu);
$dumpfile("test_pdp8.vcd");
$dumpvars(0, test);
end

48
verif/test_top.v
View File

@@ -4,13 +4,15 @@
`include "../rtl/ide.v"
`include "../rtl/ide_disk.v"
`include "../rtl/brg.v"
`include "../rtl/uart.v"
`include "../rtl/pdp8_kw.v"
`include "../rtl/pdp8_tt.v"
`include "../rtl/pdp8_rf.v"
`include "../rtl/pdp8_io.v"
`include "../rtl/pdp8_ram.v"
`include "../rtl/pdp8.v"
`include "../rtl/top.v"
`include "../rtl/ram_32kx12.v"
`include "../rtl/ram_256x12.v"
`include "../rtl/debounce.v"
@@ -31,19 +33,19 @@ module test;
reg [7:0] slideswitch;
wire [17:0] ram_a;
wire ram_oe_n;
wire ram_we_n;
wire [17:0] sram_a;
wire sram_oe_n;
wire sram_we_n;
wire [15:0] ram1_io;
wire ram1_ce_n;
wire ram1_ub_n;
wire ram1_lb_n;
wire [15:0] sram1_io;
wire sram1_ce_n;
wire sram1_ub_n;
wire sram1_lb_n;
wire [15:0] ram2_io;
wire ram2_ce_n;
wire ram2_ub_n;
wire ram2_lb_n;
wire [15:0] sram2_io;
wire sram2_ce_n;
wire sram2_ub_n;
wire sram2_lb_n;
wire [15:0] ide_data_bus;
wire ide_dior, ide_diow;
@@ -58,19 +60,19 @@ module test;
.sevenseg(sevenseg),
.sevenseg_an(sevenseg_an),
.slideswitch(slideswitch),
.ram_a(ram_a),
.ram_oe_n(ram_oe_n),
.ram_we_n(ram_we_n),
.sram_a(sram_a),
.sram_oe_n(sram_oe_n),
.sram_we_n(sram_we_n),
.ram1_io(ram1_io),
.ram1_ce_n(ram1_ce_n),
.ram1_ub_n(ram1_ub_n),
.ram1_lb_n(ram1_lb_n),
.sram1_io(sram1_io),
.sram1_ce_n(sram1_ce_n),
.sram1_ub_n(sram1_ub_n),
.sram1_lb_n(sram1_lb_n),
.ram2_io(ram2_io),
.ram2_ce_n(ram2_ce_n),
.ram2_ub_n(ram2_ub_n),
.ram2_lb_n(ram2_lb_n),
.sram2_io(sram2_io),
.sram2_ce_n(sram2_ce_n),
.sram2_ub_n(sram2_ub_n),
.sram2_lb_n(sram2_lb_n),
.ide_data_bus(ide_data_bus),
.ide_dior(ide_dior),