verif/fake_uart.v

@@ -128,9 +128,10 @@ module fake_uart(clk, reset, state,
 		  r_refires = 3;
 		  $display("xxx boom 3; cycles %d", cycles);
 	       end
-//`define msg_rcat 1
+`define msg_rcat 1
 //`define msg_rfocal 1
-`define msg_pald 1
+//`define msg_rpald 1
+//`define msg_rpip 1
 	     if (r_index == r_count && cycles == 300000/*500000*/)
 	       begin
 `ifdef msg_rcat
@@ -155,7 +156,7 @@ module fake_uart(clk, reset, state,
 		  r_index = 0;
 		  r_count = 8;
 `endif
-`ifdef msg_pald
+`ifdef msg_rpald
 		  rdata[0] = "R";
 		  rdata[1] = " ";
 		  rdata[2] = "P";
@@ -165,6 +166,16 @@ module fake_uart(clk, reset, state,
 		  rdata[6] = "\215";
 		  r_index = 0;
 		  r_count = 7;
+`endif
+`ifdef msg_rpip
+		  rdata[0] = "R";
+		  rdata[1] = " ";
+		  rdata[2] = "P";
+		  rdata[3] = "I";
+		  rdata[4] = "P";
+		  rdata[5] = "\215";
+		  r_index = 0;
+		  r_count = 6;
 `endif
 		  r_refires = 4;
 		  $display("xxx boom 4; cycles %d", cycles);

verif/run.sh

@@ -1,5 +1,6 @@
 ../cver/gplcver-2.12a.src/bin/cver  \
     +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \
+    +define+use_fake_uart=1 \
     +showpc \
     +cycles=2000000 \
     +pc=07400 \

verif/test_pdp8.v

@@ -11,7 +11,6 @@
 `endif
 
 `ifdef sim
- `define use_fake_uart
  `define debug
  `define sim_time
 `define debug_s3ram
@@ -20,7 +19,9 @@
 //`define debug_log
 `endif
 
-//`define use_rf_pli
+`ifndef use_rf_pli
+ `define use_sim_ram_model 1
+`endif
 
 `include "../rtl/pdp8_tt.v"
 `include "../rtl/pdp8_rf.v"
@@ -29,7 +30,12 @@
 `include "../rtl/pdp8_ram.v"
 `include "../rtl/pdp8.v"
 
-`include "../verif/fake_uart.v"
+`ifdef use_fake_uart
+ `include "../verif/fake_uart.v"
+`else
+ `include "../rtl/uart.v"
+`endif
+
 `include "../rtl/brg.v"
 
 `include "../rtl/ide_disk.v"
@@ -170,7 +176,7 @@ module test;
 		.sram2_ub_n(sram2_ub_n), .sram2_lb_n(sram2_lb_n));
 `endif
    
-`ifndef use_sim_model
+`ifndef use_sim_ram_model
    ram_s3board sram(.ram_a(sram_a),
 		    .ram_oe_n(sram_oe_n),
 		    .ram_we_n(sram_we_n),