50 lines
926 B
Verilog
50 lines
926 B
Verilog
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/* 32kx12 static ram */
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module ram_32kx12(A, DI, DO, CE_N, WE_N);
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input[14:0] A;
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input[11:0] DI;
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input CE_N, WE_N;
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output[11:0] DO;
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reg[11:0] ram [0:32767];
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integer i;
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initial
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begin
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for (i = 0; i < 32768; i=i+1)
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ram[i] = 12'b0;
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ram[15'o0000] = 12'o5177;
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ram[15'o0200] = 12'o7300;
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ram[15'o0201] = 12'o1300;
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ram[15'o0202] = 12'o1301;
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ram[15'o0203] = 12'o3302;
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ram[15'o0204] = 12'o7402;
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ram[15'o0205] = 12'o5200;
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`include "focal.v"
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ram[15'o0000] = 12'o5404;
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ram[15'o0004] = 12'o0200;
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end
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always @(WE_N or CE_N or A or DI)
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begin
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if (WE_N == 0 && CE_N == 0)
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begin
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$display("ram: write [%o] <- %o", A, DI);
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ram[ A ] = DI;
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end
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end
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//always @(A)
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// begin
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// $display("ram: ce %b, we %b [%o] -> %o", CE_N, WE_N, A, ram[A]);
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// end
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// assign DO = ram[ A ];
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assign DO = (^A === 1'bX || A === 1'bz) ? ram[0] : ram[A];
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endmodule
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