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Brad Parker 116cbe08db added README.md
2016-01-02 12:17:45 -05:00
cpu
basic focal working
2009-05-10 23:51:20 +00:00
images
basic images for focal
2007-01-03 12:30:31 +00:00
pdf
2010-04-02 12:33:22 +00:00
pli
2010-06-07 20:36:11 +00:00
rom
2010-10-23 23:31:38 +00:00
rtl
synthesis
2010-10-26 11:20:13 +00:00
sim
boots tss/8
2010-04-02 12:32:05 +00:00
simhv36-1
added new tss8 source dirs
2016-01-02 16:39:18 +00:00
synth
2010-10-26 11:18:34 +00:00
tests
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tss8
2011-11-25 13:03:04 +00:00
tss8_uwm
added new tss8 source dirs
2016-01-02 16:39:18 +00:00
tss8.2
added new tss8 source dirs
2016-01-02 16:39:18 +00:00
tss8.23
added new tss8 source dirs
2016-01-02 16:39:18 +00:00
utils
changes for building tss8 variants
2016-01-01 21:55:02 +00:00
v
initial
2007-01-02 16:24:48 +00:00
verif
verilator
2010-10-23 23:30:54 +00:00
verilator
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xilinx
2010-04-24 10:35:11 +00:00
README.md
added README.md
2016-01-02 12:17:45 -05:00

README.md

cpus-pdp8

Verilog FPGA PDP-8/i cpu

A working PDP-8/i cpu with an RF08 disk emulator which uses a IDE disk as a backing store. It boots TSS/8.

Included are several versions of TSS/8 sources with utilites to build the base o/s from scratch.

A base file system with utilties is required as I have not yet found all the sources for the base utilties.

Description
FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source
Readme 65 MiB
Languages
Verilog 46.9%
C 39%
Roff 4.1%
C++ 3.4%
Module Management System 1.7%
Other 4.7%