49 lines
1004 B
Verilog
49 lines
1004 B
Verilog
// display.v
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// display pc on led'and 4x7 segment digits
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module display(clk, reset, pc, dots, sevenseg, sevenseg_an);
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input clk;
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input reset;
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input [11:0] pc;
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input [3:0] dots;
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output [7:0] sevenseg;
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output [3:0] sevenseg_an;
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//
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wire [2:0] digit;
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reg [1:0] anode;
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reg [10:0] divider;
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reg aclk;
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assign digit = (anode == 2'b11) ? pc[11:9] :
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(anode == 2'b10) ? pc[8:6] :
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(anode == 2'b01) ? pc[5:3] :
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(anode == 2'b00) ? pc[2:0] :
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3'b0;
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assign sevenseg_an = (anode == 2'b11) ? 4'b0111 :
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(anode == 2'b10) ? 4'b1011 :
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(anode == 2'b01) ? 4'b1101 :
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(anode == 2'b00) ? 4'b1110 :
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4'b1111;
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assign sevenseg[0] = ~dots[anode];
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sevensegdecode decode({1'b0, digit}, sevenseg[7:1]);
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always @(posedge clk)
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begin
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divider <= divider + 11'b1;
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if (divider == 0)
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aclk = ~aclk;
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end
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// digit scan clock
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always @(posedge aclk)
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anode <= anode + 1'b1;
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endmodule
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