90 lines
1.8 KiB
Verilog
90 lines
1.8 KiB
Verilog
// fpga.v
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module fpga (clka,
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reset_n,
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ps2_clk,
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ps2_data,
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vga_blue0,
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vga_blue1,
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vga_blue2,
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vga_green0,
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vga_green1,
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vga_green2,
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vga_red0,
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vga_red1,
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vga_red2,
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vga_hsync_n,
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vga_vsync_n,
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fpga_din_d0,
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fpga_d1,
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fpga_d2,
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fpga_d3,
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fpga_d4,
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fpga_d5,
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fpga_d6,
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fpga_d7
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);
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input clka; // 100mhz
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input reset_n;
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input ps2_clk, ps2_data;
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output vga_blue0, vga_blue1, vga_blue2;
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output vga_green0, vga_green1, vga_green2;
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output vga_red0, vga_red1, vga_red2;
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output vga_hsync_n, vga_vsync_n;
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output fpga_din_d0, fpga_d1, fpga_d2, fpga_d3,
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fpga_d4, fpga_d5, fpga_d6, fpga_d7;
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//
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wire hsync, vsync;
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wire [8:0] pixel;
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//
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wire [7:0] led_data;
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// signals to create a 25MHz clock from the 100MHz input clock
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wire clk25;
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reg [1:0] gray_cnt;
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// clock divider by 4 to for a slower clock
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// uses grey code for minimized logic
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always @(posedge clka or negedge reset_n)
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if (~reset_n)
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gray_cnt <= 2'b00;
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else
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case (gray_cnt)
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2'b00: gray_cnt <= 2'b01;
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2'b01: gray_cnt <= 2'b11;
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2'b11: gray_cnt <= 2'b10;
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2'b10: gray_cnt <= 2'b00;
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default: gray_cnt <= 2'b00;
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endcase
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// assign 25mhz clock
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assign clk25 = gray_cnt[1];
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vga vga (.reset_n(reset_n),
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.clock(clk25),
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.pixel(pixel),
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.blank_n(),
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.hsync(hsync),
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.vsync(vsync),
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.ps2_clk(ps2_clk),
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.ps2_data(ps2_data),
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.led_data(led_data));
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assign vga_hsync_n = ~hsync;
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assign vga_vsync_n = ~vsync;
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assign {vga_red2, vga_red1, vga_red0,
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vga_green2, vga_green1, vga_green0,
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vga_blue2, vga_blue1, vga_blue0} = pixel;
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assign {fpga_din_d0, fpga_d1, fpga_d2, fpga_d3,
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fpga_d4, fpga_d5, fpga_d6, fpga_d7} = led_data;
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endmodule // fpga
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