65 lines
1.2 KiB
Verilog
65 lines
1.2 KiB
Verilog
module fake_ram(clk, reset,
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ram_read_req, ram_write_req, ram_done,
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ram_ma, ram_in, ram_out);
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input clk;
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input reset;
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input ram_read_req;
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input ram_write_req;
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output ram_done;
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input [14:0] ram_ma;
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input [11:0] ram_in;
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output [11:0] ram_out;
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//--------------
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reg [11:0] ram [0:32767];
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integer i;
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integer ram_debug;
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initial
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begin
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ram_debug = 0;
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for (i = 0; i < 32768; i=i+1)
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ram[i] = 12'b0;
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end
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reg [2:0] ram_state;
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wire [2:0] ram_state_next;
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always @(posedge clk)
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if (reset)
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ram_state <= 0;
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else
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ram_state <= ram_state_next;
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assign ram_state_next =
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(ram_state == 0 && ram_read_req) ? 1 :
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(ram_state == 1) ? 0 :
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(ram_state == 0 && ram_write_req) ? 2 :
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(ram_state == 2) ? 0 :
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0;
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assign ram_done = ram_state == 1 || ram_state == 2;
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always @(ram_state)
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begin
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if (ram_state == 2)
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begin
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if (ram_debug) $display("ram: write [%o] <- %o", ram_ma, ram_in);
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ram[ ram_ma ] = ram_in;
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end
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if (ram_state == 1)
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begin
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if (ram_debug) $display("ram: read [%o] -> %o", ram_ma, ram[ram_ma]);
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end
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end
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assign ram_out = ram[ ram_ma ];
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endmodule
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