148 lines
3.5 KiB
Verilog
148 lines
3.5 KiB
Verilog
//
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// // simulate IS61LV25616AL-10T on s3board
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// debug only
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//
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module ram_256kx16(a, io, ce_n, ub_n, lb_n, we_n, oe_n);
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input [17:0] a;
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inout [15:0] io;
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input ce_n;
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input ub_n;
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input lb_n;
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input we_n;
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input oe_n;
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reg [7:0] ram_h[262143:0];
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reg [7:0] ram_l[262143:0];
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assign io = { (oe_n | ub_n) ? 8'bz : ram_h[a],
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(oe_n | lb_n) ? 8'bz : ram_l[a] };
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always @(we_n or ce_n or ub_n or lb_n or a or a or io)
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if (~we_n && ~ce_n)
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begin
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if (0)
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$display("ram_256kx16: %t ce_n %b ub_n %b lb_n %b we_n %b oe_n %b",
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$time, ce_n, ub_n, lb_n, we_n, oe_n);
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`ifdef debug_ram_low
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if (~ub_n && ~lb_n) $display("ram_256kx16: %t write %o <- %o", $time, a, io);
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else
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if (~ub_n) $display("ram_256kx16: writeh %o <- %o", a, io);
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else
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if (~lb_n) $display("ram_256kx16: writel %o <- %o", a, io);
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`endif
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if (~ub_n) ram_h[a] = io[15:8];
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if (~lb_n) ram_l[a] = io[7:0];
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end
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`ifdef debug_ram_low
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always @(we_n or ce_n or ub_n or lb_n or a or a or io)
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if (we_n && ~ce_n)
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begin
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if (0)
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$display("ram_256kx16: %t ce_n %b ub_n %b lb_n %b we_n %b oe_n %b",
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$time, ce_n, ub_n, lb_n, we_n, oe_n);
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if (~ub_n && ~lb_n) $display("ram_256kx16: read %o -> %o", a, io);
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else
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if (~ub_n) $display("ram_256kx16: readh %o -> %o", a, io[7:0]);
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else
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if (~lb_n) $display("ram_256kx16: readl %o -> %o", a, io[7:0]);
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end
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`endif
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endmodule
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module ram_s3board(ram_a, ram_oe_n, ram_we_n,
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ram1_io, ram1_ce_n, ram1_ub_n, ram1_lb_n,
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ram2_io, ram2_ce_n, ram2_ub_n, ram2_lb_n);
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input [17:0] ram_a;
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input ram_oe_n, ram_we_n;
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inout [15:0] ram1_io;
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inout [15:0] ram2_io;
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input ram1_ce_n, ram1_ub_n, ram1_lb_n;
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input ram2_ce_n, ram2_ub_n, ram2_lb_n;
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// synthesis translate_off
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integer i;
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reg [15:0] v;
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reg [63:0] file;
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reg [1023:0] str;
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reg [1023:0] testfilename;
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integer n;
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initial
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begin
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for (i = 0; i < 32768/*8192*/; i=i+1)
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begin
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ram1.ram_h[i] = 8'b0;
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ram1.ram_l[i] = 8'b0;
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end
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n = 0;
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`ifdef verilator
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`define no_scan
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`endif
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`ifdef __ICARUS__
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n = $value$plusargs("test=%s", testfilename);
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`endif
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`ifdef __CVER__
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n = $scan$plusargs("test=", testfilename);
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`endif
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if (n == 0)
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begin
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testfilename = "default.mem";
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$display("using default file");
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n = 1;
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end
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if (n > 0)
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begin
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$display("ram_s3board: code filename: %s", testfilename);
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file = $fopen(testfilename, "r");
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while ($fscanf(file, "%o %o\n", i, v) > 0)
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begin
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//$display("ram_s3board[%0o] <- %o", i, v);
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ram1.ram_h[i] = v[15:8];
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ram1.ram_l[i] = v[7:0];
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end
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$fclose(file);
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end
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end
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`ifdef debug_s3ram
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always @(ram_a or ram_oe_n or ram1_ce_n or ram_we_n or ram1_io)
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begin
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if (0)
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$display("ram_s3board: ce_n %b ub_n %b lb_n %b we_n %b oe_n %b",
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ram1_ce_n, ram1_ub_n, ram1_lb_n, ram_we_n, ram_oe_n);
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if (ram_oe_n == 0 && ram_we_n == 1)
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$display("ram_s3board: read [%o] -> %o %t", ram_a, ram1_io, $time);
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if (ram_oe_n == 1 && ram_we_n == 0)
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$display("ram_s3board: write [%o] <- %o %t", ram_a, ram1_io, $time);
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end
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`endif
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// synthesis translate_on
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ram_256kx16 ram1(.a(ram_a), .io(ram1_io),
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.ce_n(ram1_ce_n), .ub_n(ram1_ub_n), .lb_n(ram1_lb_n),
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.we_n(ram_we_n), .oe_n(ram_oe_n));
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ram_256kx16 ram2(.a(ram_a), .io(ram2_io),
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.ce_n(ram2_ce_n), .ub_n(ram2_ub_n), .lb_n(ram2_lb_n),
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.we_n(ram_we_n), .oe_n(ram_oe_n));
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endmodule
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