109 lines
2.2 KiB
C++
109 lines
2.2 KiB
C++
//
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// test.cpp
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//
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//
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include "Vtest.h"
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#include <iostream>
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Vtest *top; // Instantiation of module
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unsigned int main_time = 0; // Current simulation time
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double sc_time_stamp () { // Called by $time in Verilog
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return main_time;
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}
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int main(int argc, char** argv)
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{
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VerilatedVcdC* tfp = NULL;
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Verilated::commandArgs(argc, argv); // Remember args
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top = new Vtest; // Create instance
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#ifdef VM_TRACE
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if (0) {
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Verilated::traceEverOn(true);
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VL_PRINTF("Enabling waves...\n");
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tfp = new VerilatedVcdC;
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top->trace(tfp, 99); // Trace 99 levels of hierarchy
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tfp->open("test.vcd"); // Open the dump file
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}
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#endif
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top->v__DOT__io__DOT__rf__DOT__buffer__DOT__ram_debug = 1;
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top->v__DOT__sysclk = 0;
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while (!Verilated::gotFinish()) {
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// Resets
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if (main_time < 500) {
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if (main_time == 20) {
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VL_PRINTF("reset on\n");
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top->v__DOT__reset = 1;
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top->v__DOT__initial_pc = 07400;
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}
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if (main_time == 50) {
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VL_PRINTF("reset off\n");
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top->v__DOT__reset = 0;
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}
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}
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// Toggle clock
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top->v__DOT__sysclk = ~top->v__DOT__sysclk;
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// Evaluate model
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top->eval();
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//if (top->v__DOT__sysclk) {
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//printf("state %d\n", top->v__DOT__state);
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//}
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if (top->v__DOT__sysclk &&
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top->v__DOT__state == 1)
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{
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VL_PRINTF("pc %o ir %o l%d ac %o ion %o "
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"(IF%o DF%o UF%o SF%o IB%o UB%o) state %d\n",
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top->v__DOT__cpu__DOT__pc,
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top->v__DOT__mb,
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top->v__DOT__cpu__DOT__l,
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top->v__DOT__cpu__DOT__ac,
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top->v__DOT__cpu__DOT__interrupt_enable,
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top->v__DOT__cpu__DOT__IF,
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top->v__DOT__cpu__DOT__DF,
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top->v__DOT__cpu__DOT__UF,
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top->v__DOT__cpu__DOT__SF,
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top->v__DOT__cpu__DOT__IB,
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top->v__DOT__cpu__DOT__UB,
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top->v__DOT__state);
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}
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#ifdef VM_TRACE
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//#define MIN_TIME 0
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//#define MAX_TIME 100000
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#define MIN_TIME 5196000
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#define MAX_TIME 5313000
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if (tfp) {
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if (main_time > MIN_TIME)
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tfp->dump(main_time);
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if (main_time > MAX_TIME)
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vl_finish("test.cpp",__LINE__,"");
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}
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#endif
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main_time += 10;
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}
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top->final();
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if (tfp)
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tfp->close();
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}
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