69 lines
1.1 KiB
Verilog
69 lines
1.1 KiB
Verilog
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`include "pdp8.v"
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`timescale 1ns / 1ns
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module test;
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reg clk, reset_n;
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reg[11:0] switches;
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pdp8 cpu(clk, reset_n, switches);
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initial
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begin
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$timeformat(-9, 0, "ns", 7);
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$dumpfile("pdp8.vcd");
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$dumpvars(0, test.cpu);
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end
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initial
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begin
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clk = 0;
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reset_n = 1;
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#1 begin
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reset_n = 0;
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end
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#100 begin
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reset_n = 1;
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end
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// #1500000 $finish;
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#3000000 $finish;
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end
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always
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begin
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#100 clk = 0;
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#100 clk = 1;
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end
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//----
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integer cycle;
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initial
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cycle = 0;
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always @(posedge cpu.clk)
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if (cpu.state == 4'b0000)
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begin
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cycle = cycle + 1;
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#1 $display("cycle %d, r%b, pc %o, ir%o, ma %o, mb %o, jmp %b, l%b ac %o, i%b/%b",
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cycle, cpu.run, cpu.pc,
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cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac,
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cpu.interrupt_enable, cpu.interrupt);
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end
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// always @(posedge cpu.clk)
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// begin
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// #1 $display("state %b, runs %b, pc %o, ir %o, ma %o mb %o, jmp %b, l %b ac %o",
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// cpu.state, cpu.run, cpu.pc,
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// cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac);
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// end
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endmodule
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