brad 0adc80d5fd basic images for focal

2007-01-03 12:30:31 +00:00

cpu

added basic cpu; simulates correctly

2007-01-03 12:30:19 +00:00

images

basic images for focal

2007-01-03 12:30:31 +00:00

v

initial

2007-01-02 16:24:48 +00:00

xilinx

initial

2007-01-02 16:28:10 +00:00

Description

FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source

65 MiB

Languages

Verilog 46.9%

C 39%

Roff 4.1%

C++ 3.4%

Module Management System 1.7%

Other 4.7%