112 lines
2.6 KiB
Verilog
112 lines
2.6 KiB
Verilog
//
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// boot rom occupies one page from 7400 - 7577
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//
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//`define bootrom_uart 1
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`ifndef bootrom_uart
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`define bootrom_tss8 1
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`endif
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module bootrom(clk, reset, addr, data_out, rd, selected);
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input clk;
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input reset;
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input [14:0] addr;
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output [11:0] data_out;
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input rd;
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output selected;
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//
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reg deactivate;
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reg [2:0] delay;
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reg [11:0] data;
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wire active;
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always @(posedge clk)
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if (reset)
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delay <= 3'o7;
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else
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if (deactivate || (delay != 3'o7 && delay != 3'o0))
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delay <= delay - 3'o1;
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assign active = delay != 3'b000;
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assign selected = active && (addr >= 15'o07400 && addr <= 15'o07577);
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assign data_out = data;
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always @(*)
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begin
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deactivate = 0;
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//`define debug_rom
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`ifdef debug_rom
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$display("rom: active %b delay %o addr %o", active, delay, addr);
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`endif
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`ifdef bootrom_tss8
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if (rd)
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case (addr)
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// copy tss8 bootstrap to ram and jump to it
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// (see ../rom/rom.pal)
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15'o7400: data = 12'o7240;
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15'o7401: data = 12'o1224;
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15'o7402: data = 12'o3010;
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15'o7403: data = 12'o1217;
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15'o7404: data = 12'o3410;
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15'o7405: data = 12'o1220;
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15'o7406: data = 12'o3410;
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15'o7407: data = 12'o1221;
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15'o7410: data = 12'o3410;
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15'o7411: data = 12'o1222;
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15'o7412: data = 12'o3410;
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15'o7413: data = 12'o1223;
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15'o7414: data = 12'o3410;
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15'o7415: data = 12'o7300;
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15'o7416: data = 12'o5624;
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15'o7417: data = 12'o7600;
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15'o7420: data = 12'o6603;
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15'o7421: data = 12'o6622;
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15'o7422: data = 12'o5352;
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15'o7423: data = 12'o5752;
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15'o7424: data = 12'o7750;
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endcase // case(addr)
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if (rd && active && addr == 15'o07416)
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deactivate = 1;
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`endif
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`ifdef bootrom_uart
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if (rd)
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case (addr)
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// run simple uart test
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12'o7400: data = 12'o7240;
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12'o7401: data = 12'o1215;
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12'o7402: data = 12'o3010;
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12'o7403: data = 12'o1216;
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12'o7404: data = 12'o3007;
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12'o7405: data = 12'o7200;
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12'o7406: data = 12'o1410;
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12'o7407: data = 12'o6046;
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12'o7410: data = 12'o6041;
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12'o7411: data = 12'o5210;
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12'o7412: data = 12'o2007;
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12'o7413: data = 12'o5205;
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12'o7414: data = 12'o5214;
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12'o7415: data = 12'o7417;
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12'o7416: data = 12'o7766;
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12'o7417: data = 12'o0215;
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12'o7420: data = 12'o0212;
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12'o7421: data = 12'o0310;
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12'o7422: data = 12'o0305;
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12'o7423: data = 12'o0314;
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12'o7424: data = 12'o0314;
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12'o7425: data = 12'o0317;
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12'o7426: data = 12'o0241;
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12'o7427: data = 12'o0215;
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12'o7430: data = 12'o0212;
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endcase // case(addr)
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`endif
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end
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endmodule
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