89 lines
1.8 KiB
Verilog
89 lines
1.8 KiB
Verilog
//
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// interface to async sram
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// used on s3board
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//
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// multiplexes between to high speed SRAMs
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//
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//`define use_sim_model 1
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module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr,
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sram_a, sram_oe_n, sram_we_n,
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sram1_io, sram1_ce_n, sram1_ub_n, sram1_lb_n,
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sram2_io, sram2_ce_n, sram2_ub_n, sram2_lb_n);
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input clk;
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input reset;
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input [14:0] addr;
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input [11:0] data_in;
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output [11:0] data_out;
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input rd;
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input wr;
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output [17:0] sram_a;
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output sram_oe_n, sram_we_n;
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inout [15:0] sram1_io;
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output sram1_ce_n, sram1_ub_n, sram1_lb_n;
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inout [15:0] sram2_io;
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output sram2_ce_n, sram2_ub_n, sram2_lb_n;
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//
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wire rom_decode;
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wire [11:0] rom_data;
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bootrom rom(.clk(clk),
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.reset(reset),
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.addr(addr),
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.data_out(rom_data),
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.rd(rd),
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.selected(rom_decode));
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`ifdef use_sim_ram_model
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wire [11:0] sram_data_in;
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wire [11:0] sram_data_out;
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ram_32kx12 ram(.A(addr),
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.DI(sram_data_in),
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.DO(sram_data_out),
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.CE_N(1'b0),
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.WE_N(~wr));
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assign sram_data_in = data_in;
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assign data_out = rom_decode ? rom_data : sram_data_out;
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// always @(posedge clk)
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// $display("addr %o, rom_decode %b %o", addr, rom_decode, rom_data);
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`else
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//
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wire sram1_ub, sram1_lb;
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// common
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assign sram_a = {3'b0, addr};
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assign sram_oe_n = ~rd;
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assign sram_we_n = ~wr;
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// sram1
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assign sram1_ub = 1'b1;
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assign sram1_lb = 1'b1;
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assign sram1_ce_n = 1'b0;
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assign sram1_ub_n = ~sram1_ub;
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assign sram1_lb_n = ~sram1_lb;
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assign data_out = rom_decode ? rom_data : sram1_io[11:0];
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assign sram1_io = ~sram_oe_n ? 16'bz : {4'b0, data_in};
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// sram2 not used
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assign sram2_io = 16'b0;
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assign sram2_ce_n = 1'b1;
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assign sram2_ub_n = 1'b1;
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assign sram2_lb_n = 1'b1;
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`endif
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endmodule
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