36 lines
901 B
Verilog
36 lines
901 B
Verilog
// sevensegdecode.v
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// seven segment decoder for s3board
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module sevensegdecode(digit, ss_out);
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input [3:0] digit;
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output [6:0] ss_out;
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// segments abcdefg
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// a
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// f b
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// g
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// e c
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// d
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assign ss_out =
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(digit == 4'd0) ? 7'b0000001 :
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(digit == 4'd1) ? 7'b1001111 :
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(digit == 4'd2) ? 7'b0010010 :
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(digit == 4'd3) ? 7'b0000110 :
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(digit == 4'd4) ? 7'b1001100 :
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(digit == 4'd5) ? 7'b0100100 :
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(digit == 4'd6) ? 7'b1100000 :
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(digit == 4'd7) ? 7'b0001111 :
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(digit == 4'd8) ? 7'b0000000 :
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(digit == 4'd9) ? 7'b0001100 :
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(digit == 4'ha) ? 7'b0001001 :
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(digit == 4'hb) ? 7'b1100000 :
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(digit == 4'hc) ? 7'b0110001 :
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(digit == 4'hd) ? 7'b1000010 :
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(digit == 4'he) ? 7'b0010000 :
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(digit == 4'hf) ? 7'b0111000 :
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7'b1111111;
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endmodule
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