170 lines
6.9 KiB
Plaintext
170 lines
6.9 KiB
Plaintext
Release 8.2i Map I.31
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Xilinx Mapping Report File for Design 'fpga'
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Design Information
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------------------
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Command Line : map -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise
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-p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd
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fpga.pcf
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Target Device : xc2s200
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Target Package : fg256
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Target Speed : -5
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Mapper Version : spartan2 -- $Revision: 1.34.32.1 $
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Mapped Date : Thu Dec 21 09:18:40 2006
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 3
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Logic Utilization:
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Number of Slice Flip Flops: 37 out of 4,704 1%
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Number of 4 input LUTs: 39 out of 4,704 1%
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Logic Distribution:
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Number of occupied Slices: 39 out of 2,352 1%
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Number of Slices containing only related logic: 39 out of 39 100%
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Number of Slices containing unrelated logic: 0 out of 39 0%
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*See NOTES below for an explanation of the effects of unrelated logic
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Total Number 4 input LUTs: 52 out of 4,704 1%
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Number used as logic: 39
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Number used as a route-thru: 13
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Number of bonded IOBs: 11 out of 176 6%
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IOB Flip Flops: 2
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Number of GCLKs: 2 out of 4 50%
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Number of GCLKIOBs: 1 out of 4 25%
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Total equivalent gate count for design: 630
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Additional JTAG gate count for IOBs: 576
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Peak Memory Usage: 356 MB
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Modular Design Summary
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Section 11 - Timing Report
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Section 12 - Configuration String Information
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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WARNING:LIT:243 - Logical network clkb has no load.
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WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 11
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more times for the following (max. 5 shown):
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vga_hsync_n,
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vga_red0,
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vga_red1,
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vga_red2,
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vga_green0
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To see the details of these warning messages, please use the -detail switch.
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WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol
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"gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1) has a mix of clock and
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non-clock loads. The non-clock loads are:
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Pin D of gray_cnt_FFd2
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Section 3 - Informational
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-------------------------
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INFO:MapLib:562 - No environment variables are currently set.
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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rate limited output drivers. The delay on speed critical single ended outputs
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can be dramatically reduced by designating them as fast outputs in the
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schematic.
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Section 4 - Removed Logic Summary
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---------------------------------
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2 block(s) optimized away
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Section 5 - Removed Logic
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-------------------------
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Optimized Block(s):
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TYPE BLOCK
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GND XST_GND
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VCC XST_VCC
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To enable printing of redundant blocks removed and signals merged, set the
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detailed map report option and rerun map.
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Section 6 - IOB Properties
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--------------------------
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+------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
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| | | | | Strength | Rate | | | Delay |
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+------------------------------------------------------------------------------------------------------------------------+
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| clka | GCLKIOB | INPUT | LVTTL | | | | | |
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| fpga_d1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| fpga_d2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| fpga_d3 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| fpga_d4 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| fpga_d5 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| fpga_d6 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| fpga_d7 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| fpga_din_d0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
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| ps2_clk | IOB | INPUT | LVTTL | | | INFF | | IFD |
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| ps2_data | IOB | INPUT | LVTTL | | | INFF | | IFD |
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| reset_n | IOB | INPUT | LVTTL | | | | | |
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+------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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No area groups were found in this design.
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----------------------
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Section 10 - Modular Design Summary
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-----------------------------------
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Modular Design not used for this design.
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Section 11 - Timing Report
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--------------------------
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No timing report for this architecture.
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Section 12 - Configuration String Details
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-----------------------------------------
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Use the "-detail" map option to print out Configuration Strings
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