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brad
2007-01-02 16:28:10 +00:00
parent 823db1be62
commit ecaac3a25c
138 changed files with 56138 additions and 0 deletions
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10
xilinx/TODO.txt Normal file
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pdp-8
register file
caddr
ddr controller
video bitmap
disk interface
xc2s200-5fg256

2
xilinx/ps2/_ngo/netlist.lst Normal file
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/mwave/work/nt/xess/xilinx/ps2/fpga.ngc 1166710707
OK

8
xilinx/ps2/_xmsgs/bitgen.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

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xilinx/ps2/_xmsgs/map.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">clkb</arg> has no load.
</msg>
<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">11</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">vga_hsync_n,
vga_red0,
vga_red1,
vga_red2,
vga_green0</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>
<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFG symbol &quot;gray_cnt_FFd1_BUFG&quot; (output signal=gray_cnt_FFd1)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin D of gray_cnt_FFd2</arg>
</msg>
</messages>

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xilinx/ps2/_xmsgs/ngdbuild.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

13
xilinx/ps2/_xmsgs/par.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="unknown" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;. For a balance between the fastest runtime and best performance, set the effort level to &quot;med&quot;.
</msg>
<msg type="info" file="Timing" num="2761" delta="unknown" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
</messages>

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xilinx/ps2/_xmsgs/trce.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="unknown" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="unknown" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
</messages>

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xilinx/ps2/_xmsgs/xst.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_hsync_n</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_red0</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_red1</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_red2</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_green0</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_green1</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_green2</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">clkb</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_blue0</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_blue1</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_blue2</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_vsync_n</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">vsync</arg>&gt; is never used or assigned.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">kb_scancode&lt;7&gt;</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">kb_bsy</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">hsync</arg>&gt; is never used or assigned.
</msg>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">pixel</arg>&gt; is never used or assigned.
</msg>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">data</arg>&gt; is never used or assigned.
</msg>
<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">ps2/ps2_clk_r_1</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>
<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">ps2/sc_r_7</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>
<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

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xilinx/ps2/fpga.bgn Normal file
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Release 8.2i - Bitgen I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file 'v200.nph' in environment
/opt/Xilinx.
"fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5
Opened constraints file fpga.pcf.
Thu Dec 21 09:19:03 2006
bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No fpga.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 4** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
| M1Pin | Pullup** |
+----------------------+----------------------+
| M2Pin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GSR_cycle | 6** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| Gclkdel0 | 11111** |
+----------------------+----------------------+
| Gclkdel1 | 11111** |
+----------------------+----------------------+
| Gclkdel2 | 11111** |
+----------------------+----------------------+
| Gclkdel3 | 11111** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "fpga.bit".
Bitstream generation is complete.

BIN
xilinx/ps2/fpga.bit Normal file
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Binary file not shown.

31
xilinx/ps2/fpga.bld Normal file
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Release 8.2i ngdbuild I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise
-dd _ngo -nt timestamp -uc /mwave/work/nt/xess/v/fpga2.ucf -p xc2s200-fg256-5
fpga.ngc fpga.ngd
Reading NGO file '/mwave/work/nt/xess/xilinx/ps2/fpga.ngc' ...
Applying constraints in "/mwave/work/nt/xess/v/fpga2.ucf" to the design...
Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 239836 kilobytes
Writing NGD file "fpga.ngd" ...
Writing NGDBUILD log file "fpga.bld"...

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xilinx/ps2/fpga.cmd_log Normal file
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xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd

1
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work

3
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Release 8.2i - par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Thu Dec 21 09:18:51 2006
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: fpga_map.ncd
OUTPUT FILE: fpga.pad
PART TYPE: xc2s200
SPEED GRADE: -5
PACKAGE: fg256
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|DCI Value|IO Register|Signal Integrity|
A1|||GND|||||||||||||
A2||IOB|IO|UNUSED||7||||||||||
A3||IOB|IO_VREF_0|UNUSED||0||||||||||
A4||IOB|IO|UNUSED||0||||||||||
A5||IOB|IO|UNUSED||0||||||||||
A6||IOB|IO|UNUSED||0||||||||||
A7||IOB|IO|UNUSED||0||||||||||
A8||IOB|IO|UNUSED||1||||||||||
A9||IOB|IO|UNUSED||1||||||||||
A10||IOB|IO|UNUSED||1||||||||||
A11||IOB|IO|UNUSED||1||||||||||
A12||IOB|IO|UNUSED||1||||||||||
A13||IOB|IO|UNUSED||1||||||||||
A14||IOB|IO_VREF_1|UNUSED||1||||||||||
A15|||TDI|||||||||||||
A16|||GND|||||||||||||
B1||IOB|IO_VREF_7|UNUSED||7||||||||||
B2|||GND|||||||||||||
B3||IOB|IO|UNUSED||0||||||||||
B4||IOB|IO_VREF_0|UNUSED||0||||||||||
B5||IOB|IO|UNUSED||0||||||||||
B6||IOB|IO|UNUSED||0||||||||||
B7||IOB|IO_VREF_0|UNUSED||0||||||||||
B8||GCLKIOB|GCK3|UNUSED||0||||||||||
B9||IOB|IO_VREF_1|UNUSED||1||||||||||
B10||IOB|IO|UNUSED||1||||||||||
B11||IOB|IO|UNUSED||1||||||||||
B12||IOB|IO|UNUSED||1||||||||||
B13||IOB|IO_CS|UNUSED||1||||||||||
B14|||TDO|||||||||||||
B15|||GND|||||||||||||
B16||IOB|IO|UNUSED||2||||||||||
C1||IOB|IO_VREF_7|UNUSED||7||||||||||
C2||IOB|IO|UNUSED||7||||||||||
C3|||VCCINT||||||||2.5|||||
C4|||TCK|||||||||||||
C5||IOB|IO|UNUSED||0||||||||||
C6||IOB|IO_VREF_0|UNUSED||0||||||||||
C7||IOB|IO|UNUSED||0||||||||||
C8||IOB|IO|UNUSED||0||||||||||
C9||GCLKIOB|GCK2|UNUSED||1||||||||||
C10||IOB|IO|UNUSED||1||||||||||
C11||IOB|IO_VREF_1|UNUSED||1||||||||||
C12||IOB|IO|UNUSED||1||||||||||
C13||IOB|IO_WRITE|UNUSED||1||||||||||
C14|||VCCINT||||||||2.5|||||
C15||IOB|IO_DOUT_BUSY|UNUSED||2||||||||||
C16||IOB|IO|UNUSED||2||||||||||
D1||IOB|IO_VREF_7|UNUSED||7||||||||||
D2||IOB|IO|UNUSED||7||||||||||
D3|||TMS|||||||||||||
D4|||VCCINT||||||||2.5|||||
D5||IOB|IO|UNUSED||0||||||||||
D6||IOB|IO|UNUSED||0||||||||||
D7||IOB|IO|UNUSED||0||||||||||
D8||IOB|IO|UNUSED||0||||||||||
D9||IOB|IO|UNUSED||1||||||||||
D10||IOB|IO|UNUSED||1||||||||||
D11||IOB|IO|UNUSED||1||||||||||
D12||IOB|IO|UNUSED||1||||||||||
D13|||VCCINT||||||||2.5|||||
D14|fpga_din_d0|IOB|IO_DIN_D0|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
D15|||CCLK|||||||||||||
D16||IOB|IO|UNUSED||2||||||||||
E1|ps2_data|IOB|IO|INPUT|LVTTL|7||||IFD||LOCATED||YES|NONE|
E2||IOB|IO|UNUSED||7||||||||||
E3|reset_n|IOB|IO|INPUT|LVTTL|7||||NONE||LOCATED||NO|NONE|
E4||IOB|IO|UNUSED||7||||||||||
E5|||VCCINT||||||||2.5|||||
E6||IOB|IO|UNUSED||0||||||||||
E7||IOB|IO|UNUSED||0||||||||||
E8|||VCCO_0|||0|||||any******|||||
E9|||VCCO_1|||1|||||any******|||||
E10||IOB|IO|UNUSED||1||||||||||
E11||IOB|IO_VREF_1|UNUSED||1||||||||||
E12|||VCCINT||||||||2.5|||||
E13||IOB|IO_VREF_2|UNUSED||2||||||||||
E14||IOB|IO|UNUSED||2||||||||||
E15||IOB|IO|UNUSED||2||||||||||
E16|fpga_d1|IOB|IO_D1|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
F1||IOB|IO|UNUSED||7||||||||||
F2||IOB|IO|UNUSED||7||||||||||
F3||IOB|IO|UNUSED||7||||||||||
F4|ps2_clk|IOB|IO|INPUT|LVTTL|7||||IFD||LOCATED||YES|NONE|
F5||IOB|IO|UNUSED||7||||||||||
F6|||GND|||||||||||||
F7|||GND|||||||||||||
F8|||VCCO_0|||0|||||any******|||||
F9|||VCCO_1|||1|||||any******|||||
F10|||GND|||||||||||||
F11|||GND|||||||||||||
F12||IOB|IO|UNUSED||2||||||||||
F13||IOB|IO_VREF_2|UNUSED||2||||||||||
F14||IOB|IO_VREF_2|UNUSED||2||||||||||
F15|fpga_d2|IOB|IO_D2|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
F16||IOB|IO|UNUSED||2||||||||||
G1||PCIIOB|IO_IRDY|UNUSED||7||||||||||
G2||IOB|IO|UNUSED||7||||||||||
G3||IOB|IO|UNUSED||7||||||||||
G4||IOB|IO|UNUSED||7||||||||||
G5||IOB|IO|UNUSED||7||||||||||
G6|||GND|||||||||||||
G7|||GND|||||||||||||
G8|||GND|||||||||||||
G9|||GND|||||||||||||
G10|||GND|||||||||||||
G11|||GND|||||||||||||
G12||IOB|IO|UNUSED||2||||||||||
G13||IOB|IO|UNUSED||2||||||||||
G14||IOB|IO|UNUSED||2||||||||||
G15||IOB|IO|UNUSED||2||||||||||
G16|fpga_d3|IOB|IO_D3|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
H1||IOB|IO|UNUSED||6||||||||||
H2||IOB|IO|UNUSED||7||||||||||
H3||IOB|IO_VREF_7|UNUSED||7||||||||||
H4||IOB|IO|UNUSED||7||||||||||
H5|||VCCO_7|||7|||||any******|||||
H6|||VCCO_7|||7|||||any******|||||
H7|||GND|||||||||||||
H8|||GND|||||||||||||
H9|||GND|||||||||||||
H10|||GND|||||||||||||
H11|||VCCO_2|||2|||||3.30|||||
H12|||VCCO_2|||2|||||3.30|||||
H13||IOB|IO_VREF_2|UNUSED||2||||||||||
H14||IOB|IO|UNUSED||2||||||||||
H15||IOB|IO|UNUSED||2||||||||||
H16||PCIIOB|IO_IRDY|UNUSED||2||||||||||
J1||IOB|IO|UNUSED||6||||||||||
J2||PCIIOB|IO_TRDY|UNUSED||6||||||||||
J3||IOB|IO_VREF_6|UNUSED||6||||||||||
J4||IOB|IO|UNUSED||6||||||||||
J5|||VCCO_6|||6|||||any******|||||
J6|||VCCO_6|||6|||||any******|||||
J7|||GND|||||||||||||
J8|||GND|||||||||||||
J9|||GND|||||||||||||
J10|||GND|||||||||||||
J11|||VCCO_3|||3|||||3.30|||||
J12|||VCCO_3|||3|||||3.30|||||
J13||IOB|IO|UNUSED||2||||||||||
J14||IOB|IO|UNUSED||3||||||||||
J15||PCIIOB|IO_TRDY|UNUSED||3||||||||||
J16|fpga_d4|IOB|IO_D4|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
K1||IOB|IO|UNUSED||6||||||||||
K2||IOB|IO|UNUSED||6||||||||||
K3||IOB|IO|UNUSED||6||||||||||
K4||IOB|IO|UNUSED||6||||||||||
K5||IOB|IO|UNUSED||6||||||||||
K6|||GND|||||||||||||
K7|||GND|||||||||||||
K8|||GND|||||||||||||
K9|||GND|||||||||||||
K10|||GND|||||||||||||
K11|||GND|||||||||||||
K12||IOB|IO|UNUSED||3||||||||||
K13||IOB|IO|UNUSED||3||||||||||
K14||IOB|IO|UNUSED||3||||||||||
K15||IOB|IO|UNUSED||3||||||||||
K16||IOB|IO_VREF_3|UNUSED||3||||||||||
L1||IOB|IO|UNUSED||6||||||||||
L2||IOB|IO|UNUSED||6||||||||||
L3||IOB|IO|UNUSED||6||||||||||
L4||IOB|IO|UNUSED||6||||||||||
L5||IOB|IO|UNUSED||6||||||||||
L6|||GND|||||||||||||
L7|||GND|||||||||||||
L8|||VCCO_5|||5|||||any******|||||
L9|||VCCO_4|||4|||||any******|||||
L10|||GND|||||||||||||
L11|||GND|||||||||||||
L12||IOB|IO|UNUSED||3||||||||||
L13||IOB|IO_VREF_3|UNUSED||3||||||||||
L14||IOB|IO_VREF_3|UNUSED||3||||||||||
L15||IOB|IO|UNUSED||3||||||||||
L16||IOB|IO|UNUSED||3||||||||||
M1||IOB|IO_VREF_6|UNUSED||6||||||||||
M2||IOB|IO|UNUSED||6||||||||||
M3||IOB|IO|UNUSED||6||||||||||
M4||IOB|IO|UNUSED||6||||||||||
M5|||VCCINT||||||||2.5|||||
M6||IOB|IO|UNUSED||5||||||||||
M7||IOB|IO|UNUSED||5||||||||||
M8|||VCCO_5|||5|||||any******|||||
M9|||VCCO_4|||4|||||any******|||||
M10||IOB|IO|UNUSED||4||||||||||
M11||IOB|IO|UNUSED||4||||||||||
M12|||VCCINT||||||||2.5|||||
M13||IOB|IO_VREF_3|UNUSED||3||||||||||
M14||IOB|IO|UNUSED||3||||||||||
M15||IOB|IO|UNUSED||3||||||||||
M16|fpga_d5|IOB|IO_D5|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
N1||IOB|IO_VREF_6|UNUSED||6||||||||||
N2||IOB|IO_VREF_6|UNUSED||6||||||||||
N3|||M0|||||||||||||
N4|||VCCINT||||||||2.5|||||
N5||IOB|IO|UNUSED||5||||||||||
N6||IOB|IO|UNUSED||5||||||||||
N7||IOB|IO|UNUSED||5||||||||||
N8||GCLKIOB|GCK0|UNUSED||4||||||||||
N9||IOB|IO|UNUSED||4||||||||||
N10||IOB|IO|UNUSED||4||||||||||
N11||IOB|IO|UNUSED||4||||||||||
N12||IOB|IO|UNUSED||4||||||||||
N13|||VCCINT||||||||2.5|||||
N14|fpga_d7|IOB|IO_D7|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
N15||IOB|IO_INIT|UNUSED||3||||||||||
N16|fpga_d6|IOB|IO_D6|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
P1||IOB|IO|UNUSED||6||||||||||
P2|||M1|||||||||||||
P3|||VCCINT||||||||2.5|||||
P4|||NC|||||||||||||
P5||IOB|IO|UNUSED||5||||||||||
P6||IOB|IO|UNUSED||5||||||||||
P7||IOB|IO|UNUSED||5||||||||||
P8||IOB|IO_VREF_5|UNUSED||5||||||||||
P9||IOB|IO_VREF_4|UNUSED||4||||||||||
P10||IOB|IO|UNUSED||4||||||||||
P11||IOB|IO|UNUSED||4||||||||||
P12||IOB|IO|UNUSED||4||||||||||
P13||IOB|IO|UNUSED||4||||||||||
P14|||VCCINT||||||||2.5|||||
P15|||PROGRAM|||||||||||||
P16||IOB|IO|UNUSED||3||||||||||
R1||IOB|IO|UNUSED||6||||||||||
R2|||GND|||||||||||||
R3|||M2|||||||||||||
R4|||NC|||||||||||||
R5||IOB|IO_VREF_5|UNUSED||5||||||||||
R6||IOB|IO|UNUSED||5||||||||||
R7||IOB|IO|UNUSED||5||||||||||
R8|clka|GCLKIOB|GCK1|INPUT|LVTTL|5||||NONE||LOCATED||NO|NONE|
R9||IOB|IO|UNUSED||4||||||||||
R10||IOB|IO|UNUSED||4||||||||||
R11||IOB|IO|UNUSED||4||||||||||
R12||IOB|IO|UNUSED||4||||||||||
R13||IOB|IO_VREF_4|UNUSED||4||||||||||
R14|||DONE|||||||||||||
R15|||GND|||||||||||||
R16||IOB|IO|UNUSED||3||||||||||
T1|||GND|||||||||||||
T2||IOB|IO_VREF_5|UNUSED||5||||||||||
T3||IOB|IO|UNUSED||5||||||||||
T4||IOB|IO_VREF_5|UNUSED||5||||||||||
T5||IOB|IO|UNUSED||5||||||||||
T6||IOB|IO|UNUSED||5||||||||||
T7||IOB|IO|UNUSED||5||||||||||
T8||IOB|IO|UNUSED||5||||||||||
T9||IOB|IO|UNUSED||4||||||||||
T10||IOB|IO|UNUSED||4||||||||||
T11||IOB|IO_VREF_4|UNUSED||4||||||||||
T12||IOB|IO_VREF_4|UNUSED||4||||||||||
T13||IOB|IO|UNUSED||4||||||||||
T14||IOB|IO|UNUSED||4||||||||||
T15||IOB|IO|UNUSED||3||||||||||
T16|||GND|||||||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

200
xilinx/ps2/fpga.par Normal file
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Release 8.2i par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
wide:: Thu Dec 21 09:18:46 2006
par -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
Constraints file: fpga.pcf.
Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
"fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.27 2006-05-03".
Device Utilization Summary:
Number of GCLKs 2 out of 4 50%
Number of External GCLKIOBs 1 out of 4 25%
Number of LOCed GCLKIOBs 1 out of 1 100%
Number of External IOBs 11 out of 176 6%
Number of LOCed IOBs 11 out of 11 100%
Number of SLICEs 39 out of 2352 1%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:98976a) REAL time: 3 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs
Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 3 secs
Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 3 secs
Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs
Phase 6.8
.
.
.
.
.
.
Phase 6.8 (Checksum:99cc93) REAL time: 3 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs
Writing design to file fpga.ncd
Total REAL time to Placer completion: 3 secs
Total CPU time to Placer completion: 3 secs
Starting Router
Phase 1: 225 unrouted; REAL time: 3 secs
Phase 2: 200 unrouted; REAL time: 4 secs
Phase 3: 25 unrouted; REAL time: 4 secs
Phase 4: 25 unrouted; (1488) REAL time: 4 secs
Phase 5: 25 unrouted; (1) REAL time: 4 secs
Phase 6: 0 unrouted; (1) REAL time: 4 secs
Phase 7: 0 unrouted; (1) REAL time: 4 secs
Phase 8: 0 unrouted; (1) REAL time: 4 secs
Phase 9: 0 unrouted; (1) REAL time: 4 secs
Phase 10: 0 unrouted; (1) REAL time: 4 secs
Phase 11: 0 unrouted; (1) REAL time: 4 secs
Total REAL time to Router completion: 4 secs
Total CPU time to Router completion: 4 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| gray_cnt_FFd1 | GCLKBUF0| No | 25 | 0.207 | 0.763 |
+---------------------+--------------+------+------+------------+-------------+
| clka_BUFGP | GCLKBUF1| No | 1 | 0.000 | 0.743 |
+---------------------+--------------+------+------+------------+-------------+
| ps2/rdy_r | Local| | 2 | 0.000 | 2.188 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
The Delay Summary Report
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 1.482
The MAXIMUM PIN DELAY IS: 6.039
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.856
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00
--------- --------- --------- --------- --------- ---------
98 78 17 15 15 0
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic | Absolute |Number of
| | | Levels | Slack |errors
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net gra | N/A | 8.576ns | 4 | N/A | N/A
y_cnt_FFd1 | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | N/A | 6.308ns | 1 | N/A | N/A
a_BUFGP | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net ps2 | N/A | 2.969ns | 0 | N/A | N/A
/rdy_r | | | | |
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 5 secs
Total CPU time to PAR completion: 5 secs
Peak Memory Usage: 307 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file fpga.ncd
PAR done!

18
xilinx/ps2/fpga.pcf Normal file
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//! **************************************************************************
// Written by: Map I.31 on Thu Dec 21 09:18:43 2006
//! **************************************************************************
SCHEMATIC START;
COMP "reset_n" LOCATE = SITE "E3" LEVEL 1;
COMP "clka" LOCATE = SITE "R8" LEVEL 1;
COMP "fpga_d1" LOCATE = SITE "E16" LEVEL 1;
COMP "fpga_din_d0" LOCATE = SITE "D14" LEVEL 1;
COMP "fpga_d2" LOCATE = SITE "F15" LEVEL 1;
COMP "fpga_d3" LOCATE = SITE "G16" LEVEL 1;
COMP "fpga_d4" LOCATE = SITE "J16" LEVEL 1;
COMP "fpga_d5" LOCATE = SITE "M16" LEVEL 1;
COMP "fpga_d6" LOCATE = SITE "N16" LEVEL 1;
COMP "fpga_d7" LOCATE = SITE "N14" LEVEL 1;
COMP "ps2_data" LOCATE = SITE "E1" LEVEL 1;
COMP "ps2_clk" LOCATE = SITE "F4" LEVEL 1;
SCHEMATIC END;

2
xilinx/ps2/fpga.prj Normal file
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verilog work "../../v/ps2.v"
verilog work "../../v/fpga2.v"

0
xilinx/ps2/fpga.stx Normal file
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524
xilinx/ps2/fpga.syr Normal file
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Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s
-->
Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s
-->
Reading design: fpga.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "fpga.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "fpga"
Output Format : NGC
Target Device : xc2s200-5-fg256
---- Source Options
Top Module Name : fpga
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Multiplier Style : lut
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Write Timing Constraints : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
lso : fpga.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
tristate2logic : Yes
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../../v/ps2.v" in library work
Compiling verilog file "../../v/fpga2.v" in library work
Module <ps2> compiled
Module <fpga> compiled
No errors in compilation
Analysis of file <"fpga.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <fpga> in library <work>.
Analyzing hierarchy for module <ps2> in library <work> with parameters.
PS2_FREQ = "00000000000000000000000000001010"
KEY_RELEASE = "11110000"
FREQ = "00000000000000000110000110101000"
TIMEOUT = "00000000000000000000100111000100"
Building hierarchy successfully finished.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <fpga>.
Module <fpga> is correct for synthesis.
Analyzing module <ps2> in library <work>.
FREQ = 32'sb00000000000000000110000110101000
PS2_FREQ = 32'sb00000000000000000000000000001010
TIMEOUT = 32'sb00000000000000000000100111000100
KEY_RELEASE = 8'b11110000
Module <ps2> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <ps2>.
Related source file is "../../v/ps2.v".
Found 14-bit adder for signal <$addsub0000> created at line 93.
Found 4-bit adder for signal <$addsub0001> created at line 103.
Found 4-bit register for signal <bitcnt_r>.
Found 4-bit 4-to-1 multiplexer for signal <bitcnt_x>.
Found 1-bit register for signal <error_r>.
Found 1-bit register for signal <keyrel_r>.
Found 1-bit 4-to-1 multiplexer for signal <keyrel_x>.
Found 5-bit register for signal <ps2_clk_r>.
Found 1-bit register for signal <rdy_r>.
Found 10-bit register for signal <sc_r>.
Found 14-bit register for signal <timer_r>.
Summary:
inferred 36 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 5 Multiplexer(s).
Unit <ps2> synthesized.
Synthesizing Unit <fpga>.
Related source file is "../../v/fpga2.v".
WARNING:Xst:1306 - Output <vga_hsync_n> is never assigned.
WARNING:Xst:1306 - Output <vga_red0> is never assigned.
WARNING:Xst:1306 - Output <vga_red1> is never assigned.
WARNING:Xst:1306 - Output <vga_red2> is never assigned.
WARNING:Xst:1306 - Output <vga_green0> is never assigned.
WARNING:Xst:1306 - Output <vga_green1> is never assigned.
WARNING:Xst:1306 - Output <vga_green2> is never assigned.
WARNING:Xst:647 - Input <clkb> is never used.
WARNING:Xst:1306 - Output <vga_blue0> is never assigned.
WARNING:Xst:1306 - Output <vga_blue1> is never assigned.
WARNING:Xst:1306 - Output <vga_blue2> is never assigned.
WARNING:Xst:1306 - Output <vga_vsync_n> is never assigned.
WARNING:Xst:1780 - Signal <vsync> is never used or assigned.
WARNING:Xst:646 - Signal <kb_scancode<7>> is assigned but never used.
WARNING:Xst:646 - Signal <kb_bsy> is assigned but never used.
WARNING:Xst:1780 - Signal <hsync> is never used or assigned.
WARNING:Xst:1780 - Signal <pixel> is never used or assigned.
WARNING:Xst:1780 - Signal <data> is never used or assigned.
Found finite state machine <FSM_0> for signal <gray_cnt>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 4 |
| Inputs | 0 |
| Outputs | 2 |
| Clock | clka (rising_edge) |
| Reset | reset_n (negative) |
| Reset type | asynchronous |
| Reset State | 00 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 1-bit register for signal <rdy>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 D-type flip-flop(s).
Unit <fpga> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
14-bit adder : 1
4-bit adder : 1
# Registers : 8
1-bit register : 4
10-bit register : 1
14-bit register : 1
4-bit register : 1
5-bit register : 1
# Multiplexers : 2
1-bit 4-to-1 multiplexer : 1
4-bit 4-to-1 multiplexer : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <gray_cnt> on signal <gray_cnt[1:2]> with gray encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
11 | 11
10 | 10
-------------------
Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 1
# Adders/Subtractors : 2
14-bit adder : 1
4-bit adder : 1
# Registers : 39
Flip-Flops : 39
# Multiplexers : 2
1-bit 4-to-1 multiplexer : 1
4-bit 4-to-1 multiplexer : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <fpga> ...
Optimizing unit <ps2> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 1.
Final Macro Processing ...
Processing Unit <fpga> :
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <ps2/ps2_clk_r_1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <ps2/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <fpga> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 39
Flip-Flops : 39
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : fpga.ngr
Top Level Output File Name : fpga
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 24
Cell Usage :
# BELS : 85
# GND : 1
# INV : 4
# LUT1 : 13
# LUT2 : 16
# LUT3 : 2
# LUT3_L : 1
# LUT4 : 14
# LUT4_D : 3
# LUT4_L : 2
# MUXCY : 13
# MUXF5 : 2
# VCC : 1
# XORCY : 13
# FlipFlops/Latches : 39
# FDC : 24
# FDCE : 10
# FDP : 5
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 11
# IBUF : 3
# OBUF : 8
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s200fg256-5
Number of Slices: 34 out of 2352 1%
Number of Slice Flip Flops: 39 out of 4704 0%
Number of 4 input LUTs: 55 out of 4704 1%
Number of IOs: 24
Number of bonded IOBs: 12 out of 180 6%
Number of GCLKs: 2 out of 4 50%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
ps2/rdy_r | NONE(rdy) | 1 |
clka | BUFGP | 2 |
gray_cnt_FFd11 | BUFG | 36 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
-------------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-------------------------------------+------------------------+-------+
ps2/rst_n_inv(ps2/rst_n_inv1_INV_0:O)| NONE(rdy) | 39 |
-------------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 10.147ns (Maximum Frequency: 98.551MHz)
Minimum input arrival time before clock: 2.827ns
Maximum output required time after clock: 8.329ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'ps2/rdy_r'
Clock period: 5.188ns (frequency: 192.753MHz)
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 5.188ns (Levels of Logic = 1)
Source: rdy (FF)
Destination: rdy (FF)
Source Clock: ps2/rdy_r rising
Destination Clock: ps2/rdy_r rising
Data Path: rdy to rdy
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 1.292 1.340 rdy (rdy)
INV:I->O 1 0.653 1.150 _not00011_INV_0 (_not0001)
FDC:D 0.753 rdy
----------------------------------------
Total 5.188ns (2.698ns logic, 2.490ns route)
(52.0% logic, 48.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clka'
Clock period: 9.821ns (frequency: 101.823MHz)
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay: 9.821ns (Levels of Logic = 2)
Source: gray_cnt_FFd1 (FF)
Destination: gray_cnt_FFd2 (FF)
Source Clock: clka rising
Destination Clock: clka rising
Data Path: gray_cnt_FFd1 to gray_cnt_FFd2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 1 1.292 1.150 gray_cnt_FFd1 (gray_cnt_FFd11)
BUFG:I->O 37 0.773 4.050 gray_cnt_FFd1_BUFG (gray_cnt_FFd1)
INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In)
FDC:D 0.753 gray_cnt_FFd2
----------------------------------------
Total 9.821ns (3.471ns logic, 6.350ns route)
(35.3% logic, 64.7% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'gray_cnt_FFd11'
Clock period: 10.147ns (frequency: 98.551MHz)
Total number of paths / destination ports: 389 / 44
-------------------------------------------------------------------------
Delay: 10.147ns (Levels of Logic = 4)
Source: ps2/timer_r_7 (FF)
Destination: ps2/bitcnt_r_1 (FF)
Source Clock: gray_cnt_FFd11 rising
Destination Clock: gray_cnt_FFd11 rising
Data Path: ps2/timer_r_7 to ps2/bitcnt_r_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 1.292 1.340 ps2/timer_r_7 (ps2/timer_r_7)
LUT4:I0->O 1 0.653 1.150 ps2/_cmp_eq00018 (ps2/_cmp_eq0001_map32)
LUT4:I0->O 6 0.653 1.850 ps2/_cmp_eq000156 (ps2/_cmp_eq0001)
LUT4_D:I3->O 1 0.653 1.150 ps2/bitcnt_x<1>111 (ps2/N3)
LUT4:I1->O 1 0.653 0.000 ps2/bitcnt_x<1>1 (ps2/bitcnt_x<1>)
FDC:D 0.753 ps2/bitcnt_r_1
----------------------------------------
Total 10.147ns (4.657ns logic, 5.490ns route)
(45.9% logic, 54.1% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd11'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 2.827ns (Levels of Logic = 1)
Source: ps2_clk (PAD)
Destination: ps2/ps2_clk_r_0 (FF)
Destination Clock: gray_cnt_FFd11 rising
Data Path: ps2_clk to ps2/ps2_clk_r_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.924 1.150 ps2_clk_IBUF (ps2_clk_IBUF)
FDP:D 0.753 ps2/ps2_clk_r_0
----------------------------------------
Total 2.827ns (1.677ns logic, 1.150ns route)
(59.3% logic, 40.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gray_cnt_FFd11'
Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Offset: 8.329ns (Levels of Logic = 1)
Source: ps2/sc_r_6 (FF)
Destination: fpga_din_d0 (PAD)
Source Clock: gray_cnt_FFd11 rising
Data Path: ps2/sc_r_6 to fpga_din_d0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 3 1.292 1.480 ps2/sc_r_6 (ps2/sc_r_6)
OBUF:I->O 5.557 fpga_din_d0_OBUF (fpga_din_d0)
----------------------------------------
Total 8.329ns (6.849ns logic, 1.480ns route)
(82.2% logic, 17.8% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'ps2/rdy_r'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 8.189ns (Levels of Logic = 1)
Source: rdy (FF)
Destination: fpga_d1 (PAD)
Source Clock: ps2/rdy_r rising
Data Path: rdy to fpga_d1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 1.292 1.340 rdy (rdy)
OBUF:I->O 5.557 fpga_d1_OBUF (fpga_d1)
----------------------------------------
Total 8.189ns (6.849ns logic, 1.340ns route)
(83.6% logic, 16.4% route)
=========================================================================
CPU : 7.48 / 7.59 s | Elapsed : 8.00 / 8.00 s
-->
Total memory usage is 239200 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 18 ( 0 filtered)
Number of infos : 3 ( 0 filtered)

48
xilinx/ps2/fpga.twr Normal file
View File

@@ -0,0 +1,48 @@
--------------------------------------------------------------------------------
Release 8.2i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
trce -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise -e 3 -l 3 -s 5
-xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
Design file: fpga.ncd
Physical constraint file: fpga.pcf
Device,speed: xc2s200,-5 (PRODUCTION 1.27 2006-05-03)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clka
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clka | 6.308| | | |
---------------+---------+---------+---------+---------+
Analysis completed Thu Dec 21 09:18:57 2006
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 194 MB

279
xilinx/ps2/fpga.twx Normal file
View File

@@ -0,0 +1,279 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead, (twWarn | twDebug | twInfo)*, twBody, twSum?, twFoot, twClientInfo?)>
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstList?, twConstSummaryTable?, twUnmetConstCnt?, twDebug*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG)*, twUnmetConstCnt?, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG)*, twUnmetConstCnt?, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt*, twPathRptBanner, twPathRpt*) | (twPathRpt*, twRacePathRpt?) | (twNetRpt*)))>
<!ATTLIST twConst twConstType (twPathConst | twNetConst) "twPathConst">
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntHold, twMinPer?, twMaxDel?, twMaxFreq?, twMaxNetDel?, twMaxNetSkew?, twMinOff?, twMaxOff?)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupRiseSlack CDATA #IMPLIED>
<!ATTLIST twSUHSlackTime twSetupFallSlack CDATA #IMPLIED>
<!ATTLIST twSUHSlackTime twHoldRiseSlack CDATA #IMPLIED>
<!ATTLIST twSUHSlackTime twHoldFallSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead><twExecVer>Release 8.2i Trace </twExecVer><twCopyright>Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>trce -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise -e 3 -l 3 -s 5
-xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf
</twCmdLine><twDesign>fpga.ncd</twDesign><twPCF>fpga.pcf</twPCF><twDevInfo arch="spartan2"><twDevName>xc2s200</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.27 2006-05-03</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twErr"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twBody><twErrRpt><twDataSheet twNameLen="15"><twClk2SUList twDestWidth = "4"><twDest>clka</twDest><twClk2SU><twSrc>clka</twSrc><twRiseRise>6.308</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twFoot><twTimestamp>Thu Dec 21 09:18:57 2006</twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 194 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

7
xilinx/ps2/fpga.unroutes Normal file
View File

@@ -0,0 +1,7 @@
Release 8.2i - par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Thu Dec 21 09:18:52 2006
There are 0 unrouted networks:

29
xilinx/ps2/fpga.ut Normal file
View File

@@ -0,0 +1,29 @@
-w
-g DebugBitstream:No
-g Binary:no
-g Gclkdel0:11111
-g Gclkdel1:11111
-g Gclkdel2:11111
-g Gclkdel3:11111
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GSR_cycle:6
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No

3
xilinx/ps2/fpga.xpi Normal file
View File

@@ -0,0 +1,3 @@
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF

54
xilinx/ps2/fpga.xst Normal file
View File

@@ -0,0 +1,54 @@
set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn fpga.prj
-ifmt mixed
-ofn fpga
-ofmt NGC
-p xc2s200-5-fg256
-top fpga
-opt_mode Speed
-opt_level 1
-iuc NO
-lso fpga.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-mult_style lut
-iobuf YES
-max_fanout 100
-bufg 4
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-tristate2logic Yes
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

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Release 8.2i Map I.31
Xilinx Mapping Report File for Design 'fpga'
Design Information
------------------
Command Line : map -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise
-p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd
fpga.pcf
Target Device : xc2s200
Target Package : fg256
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.34.32.1 $
Mapped Date : Thu Dec 21 09:18:40 2006
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Logic Utilization:
Number of Slice Flip Flops: 37 out of 4,704 1%
Number of 4 input LUTs: 39 out of 4,704 1%
Logic Distribution:
Number of occupied Slices: 39 out of 2,352 1%
Number of Slices containing only related logic: 39 out of 39 100%
Number of Slices containing unrelated logic: 0 out of 39 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 52 out of 4,704 1%
Number used as logic: 39
Number used as a route-thru: 13
Number of bonded IOBs: 11 out of 176 6%
IOB Flip Flops: 2
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 1 out of 4 25%
Total equivalent gate count for design: 630
Additional JTAG gate count for IOBs: 576
Peak Memory Usage: 356 MB
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network clkb has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 11
more times for the following (max. 5 shown):
vga_hsync_n,
vga_red0,
vga_red1,
vga_red2,
vga_green0
To see the details of these warning messages, please use the -detail switch.
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol
"gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1) has a mix of clock and
non-clock loads. The non-clock loads are:
Pin D of gray_cnt_FFd2
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clka | GCLKIOB | INPUT | LVTTL | | | | | |
| fpga_d1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| fpga_d2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| fpga_d3 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| fpga_d4 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| fpga_d5 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| fpga_d6 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| fpga_d7 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| fpga_din_d0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ps2_clk | IOB | INPUT | LVTTL | | | INFF | | IFD |
| ps2_data | IOB | INPUT | LVTTL | | | INFF | | IFD |
| reset_n | IOB | INPUT | LVTTL | | | | | |
+------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
No timing report for this architecture.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

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#Release 8.2i - par I.31
#Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
#Thu Dec 21 09:18:51 2006
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: fpga_map.ncd
#OUTPUT FILE: fpga_pad.csv
#PART TYPE: xc2s200
#SPEED GRADE: -5
#PACKAGE: fg256
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,DCI Value,IO Register,Signal Integrity,
A1,,,GND,,,,,,,,,,,,,
A2,,IOB,IO,UNUSED,,7,,,,,,,,,,
A3,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
A4,,IOB,IO,UNUSED,,0,,,,,,,,,,
A5,,IOB,IO,UNUSED,,0,,,,,,,,,,
A6,,IOB,IO,UNUSED,,0,,,,,,,,,,
A7,,IOB,IO,UNUSED,,0,,,,,,,,,,
A8,,IOB,IO,UNUSED,,1,,,,,,,,,,
A9,,IOB,IO,UNUSED,,1,,,,,,,,,,
A10,,IOB,IO,UNUSED,,1,,,,,,,,,,
A11,,IOB,IO,UNUSED,,1,,,,,,,,,,
A12,,IOB,IO,UNUSED,,1,,,,,,,,,,
A13,,IOB,IO,UNUSED,,1,,,,,,,,,,
A14,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
A15,,,TDI,,,,,,,,,,,,,
A16,,,GND,,,,,,,,,,,,,
B1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
B2,,,GND,,,,,,,,,,,,,
B3,,IOB,IO,UNUSED,,0,,,,,,,,,,
B4,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
B5,,IOB,IO,UNUSED,,0,,,,,,,,,,
B6,,IOB,IO,UNUSED,,0,,,,,,,,,,
B7,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
B8,,GCLKIOB,GCK3,UNUSED,,0,,,,,,,,,,
B9,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
B10,,IOB,IO,UNUSED,,1,,,,,,,,,,
B11,,IOB,IO,UNUSED,,1,,,,,,,,,,
B12,,IOB,IO,UNUSED,,1,,,,,,,,,,
B13,,IOB,IO_CS,UNUSED,,1,,,,,,,,,,
B14,,,TDO,,,,,,,,,,,,,
B15,,,GND,,,,,,,,,,,,,
B16,,IOB,IO,UNUSED,,2,,,,,,,,,,
C1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
C2,,IOB,IO,UNUSED,,7,,,,,,,,,,
C3,,,VCCINT,,,,,,,,2.5,,,,,
C4,,,TCK,,,,,,,,,,,,,
C5,,IOB,IO,UNUSED,,0,,,,,,,,,,
C6,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
C7,,IOB,IO,UNUSED,,0,,,,,,,,,,
C8,,IOB,IO,UNUSED,,0,,,,,,,,,,
C9,,GCLKIOB,GCK2,UNUSED,,1,,,,,,,,,,
C10,,IOB,IO,UNUSED,,1,,,,,,,,,,
C11,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
C12,,IOB,IO,UNUSED,,1,,,,,,,,,,
C13,,IOB,IO_WRITE,UNUSED,,1,,,,,,,,,,
C14,,,VCCINT,,,,,,,,2.5,,,,,
C15,,IOB,IO_DOUT_BUSY,UNUSED,,2,,,,,,,,,,
C16,,IOB,IO,UNUSED,,2,,,,,,,,,,
D1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
D2,,IOB,IO,UNUSED,,7,,,,,,,,,,
D3,,,TMS,,,,,,,,,,,,,
D4,,,VCCINT,,,,,,,,2.5,,,,,
D5,,IOB,IO,UNUSED,,0,,,,,,,,,,
D6,,IOB,IO,UNUSED,,0,,,,,,,,,,
D7,,IOB,IO,UNUSED,,0,,,,,,,,,,
D8,,IOB,IO,UNUSED,,0,,,,,,,,,,
D9,,IOB,IO,UNUSED,,1,,,,,,,,,,
D10,,IOB,IO,UNUSED,,1,,,,,,,,,,
D11,,IOB,IO,UNUSED,,1,,,,,,,,,,
D12,,IOB,IO,UNUSED,,1,,,,,,,,,,
D13,,,VCCINT,,,,,,,,2.5,,,,,
D14,fpga_din_d0,IOB,IO_DIN_D0,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
D15,,,CCLK,,,,,,,,,,,,,
D16,,IOB,IO,UNUSED,,2,,,,,,,,,,
E1,ps2_data,IOB,IO,INPUT,LVTTL,7,,,,IFD,,LOCATED,,YES,NONE,
E2,,IOB,IO,UNUSED,,7,,,,,,,,,,
E3,reset_n,IOB,IO,INPUT,LVTTL,7,,,,NONE,,LOCATED,,NO,NONE,
E4,,IOB,IO,UNUSED,,7,,,,,,,,,,
E5,,,VCCINT,,,,,,,,2.5,,,,,
E6,,IOB,IO,UNUSED,,0,,,,,,,,,,
E7,,IOB,IO,UNUSED,,0,,,,,,,,,,
E8,,,VCCO_0,,,0,,,,,any******,,,,,
E9,,,VCCO_1,,,1,,,,,any******,,,,,
E10,,IOB,IO,UNUSED,,1,,,,,,,,,,
E11,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
E12,,,VCCINT,,,,,,,,2.5,,,,,
E13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
E14,,IOB,IO,UNUSED,,2,,,,,,,,,,
E15,,IOB,IO,UNUSED,,2,,,,,,,,,,
E16,fpga_d1,IOB,IO_D1,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
F1,,IOB,IO,UNUSED,,7,,,,,,,,,,
F2,,IOB,IO,UNUSED,,7,,,,,,,,,,
F3,,IOB,IO,UNUSED,,7,,,,,,,,,,
F4,ps2_clk,IOB,IO,INPUT,LVTTL,7,,,,IFD,,LOCATED,,YES,NONE,
F5,,IOB,IO,UNUSED,,7,,,,,,,,,,
F6,,,GND,,,,,,,,,,,,,
F7,,,GND,,,,,,,,,,,,,
F8,,,VCCO_0,,,0,,,,,any******,,,,,
F9,,,VCCO_1,,,1,,,,,any******,,,,,
F10,,,GND,,,,,,,,,,,,,
F11,,,GND,,,,,,,,,,,,,
F12,,IOB,IO,UNUSED,,2,,,,,,,,,,
F13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
F14,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
F15,fpga_d2,IOB,IO_D2,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
F16,,IOB,IO,UNUSED,,2,,,,,,,,,,
G1,,PCIIOB,IO_IRDY,UNUSED,,7,,,,,,,,,,
G2,,IOB,IO,UNUSED,,7,,,,,,,,,,
G3,,IOB,IO,UNUSED,,7,,,,,,,,,,
G4,,IOB,IO,UNUSED,,7,,,,,,,,,,
G5,,IOB,IO,UNUSED,,7,,,,,,,,,,
G6,,,GND,,,,,,,,,,,,,
G7,,,GND,,,,,,,,,,,,,
G8,,,GND,,,,,,,,,,,,,
G9,,,GND,,,,,,,,,,,,,
G10,,,GND,,,,,,,,,,,,,
G11,,,GND,,,,,,,,,,,,,
G12,,IOB,IO,UNUSED,,2,,,,,,,,,,
G13,,IOB,IO,UNUSED,,2,,,,,,,,,,
G14,,IOB,IO,UNUSED,,2,,,,,,,,,,
G15,,IOB,IO,UNUSED,,2,,,,,,,,,,
G16,fpga_d3,IOB,IO_D3,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
H1,,IOB,IO,UNUSED,,6,,,,,,,,,,
H2,,IOB,IO,UNUSED,,7,,,,,,,,,,
H3,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
H4,,IOB,IO,UNUSED,,7,,,,,,,,,,
H5,,,VCCO_7,,,7,,,,,any******,,,,,
H6,,,VCCO_7,,,7,,,,,any******,,,,,
H7,,,GND,,,,,,,,,,,,,
H8,,,GND,,,,,,,,,,,,,
H9,,,GND,,,,,,,,,,,,,
H10,,,GND,,,,,,,,,,,,,
H11,,,VCCO_2,,,2,,,,,3.30,,,,,
H12,,,VCCO_2,,,2,,,,,3.30,,,,,
H13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
H14,,IOB,IO,UNUSED,,2,,,,,,,,,,
H15,,IOB,IO,UNUSED,,2,,,,,,,,,,
H16,,PCIIOB,IO_IRDY,UNUSED,,2,,,,,,,,,,
J1,,IOB,IO,UNUSED,,6,,,,,,,,,,
J2,,PCIIOB,IO_TRDY,UNUSED,,6,,,,,,,,,,
J3,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
J4,,IOB,IO,UNUSED,,6,,,,,,,,,,
J5,,,VCCO_6,,,6,,,,,any******,,,,,
J6,,,VCCO_6,,,6,,,,,any******,,,,,
J7,,,GND,,,,,,,,,,,,,
J8,,,GND,,,,,,,,,,,,,
J9,,,GND,,,,,,,,,,,,,
J10,,,GND,,,,,,,,,,,,,
J11,,,VCCO_3,,,3,,,,,3.30,,,,,
J12,,,VCCO_3,,,3,,,,,3.30,,,,,
J13,,IOB,IO,UNUSED,,2,,,,,,,,,,
J14,,IOB,IO,UNUSED,,3,,,,,,,,,,
J15,,PCIIOB,IO_TRDY,UNUSED,,3,,,,,,,,,,
J16,fpga_d4,IOB,IO_D4,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
K1,,IOB,IO,UNUSED,,6,,,,,,,,,,
K2,,IOB,IO,UNUSED,,6,,,,,,,,,,
K3,,IOB,IO,UNUSED,,6,,,,,,,,,,
K4,,IOB,IO,UNUSED,,6,,,,,,,,,,
K5,,IOB,IO,UNUSED,,6,,,,,,,,,,
K6,,,GND,,,,,,,,,,,,,
K7,,,GND,,,,,,,,,,,,,
K8,,,GND,,,,,,,,,,,,,
K9,,,GND,,,,,,,,,,,,,
K10,,,GND,,,,,,,,,,,,,
K11,,,GND,,,,,,,,,,,,,
K12,,IOB,IO,UNUSED,,3,,,,,,,,,,
K13,,IOB,IO,UNUSED,,3,,,,,,,,,,
K14,,IOB,IO,UNUSED,,3,,,,,,,,,,
K15,,IOB,IO,UNUSED,,3,,,,,,,,,,
K16,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
L1,,IOB,IO,UNUSED,,6,,,,,,,,,,
L2,,IOB,IO,UNUSED,,6,,,,,,,,,,
L3,,IOB,IO,UNUSED,,6,,,,,,,,,,
L4,,IOB,IO,UNUSED,,6,,,,,,,,,,
L5,,IOB,IO,UNUSED,,6,,,,,,,,,,
L6,,,GND,,,,,,,,,,,,,
L7,,,GND,,,,,,,,,,,,,
L8,,,VCCO_5,,,5,,,,,any******,,,,,
L9,,,VCCO_4,,,4,,,,,any******,,,,,
L10,,,GND,,,,,,,,,,,,,
L11,,,GND,,,,,,,,,,,,,
L12,,IOB,IO,UNUSED,,3,,,,,,,,,,
L13,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
L14,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
L15,,IOB,IO,UNUSED,,3,,,,,,,,,,
L16,,IOB,IO,UNUSED,,3,,,,,,,,,,
M1,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
M2,,IOB,IO,UNUSED,,6,,,,,,,,,,
M3,,IOB,IO,UNUSED,,6,,,,,,,,,,
M4,,IOB,IO,UNUSED,,6,,,,,,,,,,
M5,,,VCCINT,,,,,,,,2.5,,,,,
M6,,IOB,IO,UNUSED,,5,,,,,,,,,,
M7,,IOB,IO,UNUSED,,5,,,,,,,,,,
M8,,,VCCO_5,,,5,,,,,any******,,,,,
M9,,,VCCO_4,,,4,,,,,any******,,,,,
M10,,IOB,IO,UNUSED,,4,,,,,,,,,,
M11,,IOB,IO,UNUSED,,4,,,,,,,,,,
M12,,,VCCINT,,,,,,,,2.5,,,,,
M13,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
M14,,IOB,IO,UNUSED,,3,,,,,,,,,,
M15,,IOB,IO,UNUSED,,3,,,,,,,,,,
M16,fpga_d5,IOB,IO_D5,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N1,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
N2,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
N3,,,M0,,,,,,,,,,,,,
N4,,,VCCINT,,,,,,,,2.5,,,,,
N5,,IOB,IO,UNUSED,,5,,,,,,,,,,
N6,,IOB,IO,UNUSED,,5,,,,,,,,,,
N7,,IOB,IO,UNUSED,,5,,,,,,,,,,
N8,,GCLKIOB,GCK0,UNUSED,,4,,,,,,,,,,
N9,,IOB,IO,UNUSED,,4,,,,,,,,,,
N10,,IOB,IO,UNUSED,,4,,,,,,,,,,
N11,,IOB,IO,UNUSED,,4,,,,,,,,,,
N12,,IOB,IO,UNUSED,,4,,,,,,,,,,
N13,,,VCCINT,,,,,,,,2.5,,,,,
N14,fpga_d7,IOB,IO_D7,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N15,,IOB,IO_INIT,UNUSED,,3,,,,,,,,,,
N16,fpga_d6,IOB,IO_D6,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P1,,IOB,IO,UNUSED,,6,,,,,,,,,,
P2,,,M1,,,,,,,,,,,,,
P3,,,VCCINT,,,,,,,,2.5,,,,,
P4,,,NC,,,,,,,,,,,,,
P5,,IOB,IO,UNUSED,,5,,,,,,,,,,
P6,,IOB,IO,UNUSED,,5,,,,,,,,,,
P7,,IOB,IO,UNUSED,,5,,,,,,,,,,
P8,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
P9,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
P10,,IOB,IO,UNUSED,,4,,,,,,,,,,
P11,,IOB,IO,UNUSED,,4,,,,,,,,,,
P12,,IOB,IO,UNUSED,,4,,,,,,,,,,
P13,,IOB,IO,UNUSED,,4,,,,,,,,,,
P14,,,VCCINT,,,,,,,,2.5,,,,,
P15,,,PROGRAM,,,,,,,,,,,,,
P16,,IOB,IO,UNUSED,,3,,,,,,,,,,
R1,,IOB,IO,UNUSED,,6,,,,,,,,,,
R2,,,GND,,,,,,,,,,,,,
R3,,,M2,,,,,,,,,,,,,
R4,,,NC,,,,,,,,,,,,,
R5,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
R6,,IOB,IO,UNUSED,,5,,,,,,,,,,
R7,,IOB,IO,UNUSED,,5,,,,,,,,,,
R8,clka,GCLKIOB,GCK1,INPUT,LVTTL,5,,,,NONE,,LOCATED,,NO,NONE,
R9,,IOB,IO,UNUSED,,4,,,,,,,,,,
R10,,IOB,IO,UNUSED,,4,,,,,,,,,,
R11,,IOB,IO,UNUSED,,4,,,,,,,,,,
R12,,IOB,IO,UNUSED,,4,,,,,,,,,,
R13,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
R14,,,DONE,,,,,,,,,,,,,
R15,,,GND,,,,,,,,,,,,,
R16,,IOB,IO,UNUSED,,3,,,,,,,,,,
T1,,,GND,,,,,,,,,,,,,
T2,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
T3,,IOB,IO,UNUSED,,5,,,,,,,,,,
T4,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
T5,,IOB,IO,UNUSED,,5,,,,,,,,,,
T6,,IOB,IO,UNUSED,,5,,,,,,,,,,
T7,,IOB,IO,UNUSED,,5,,,,,,,,,,
T8,,IOB,IO,UNUSED,,5,,,,,,,,,,
T9,,IOB,IO,UNUSED,,4,,,,,,,,,,
T10,,IOB,IO,UNUSED,,4,,,,,,,,,,
T11,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
T12,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
T13,,IOB,IO,UNUSED,,4,,,,,,,,,,
T14,,IOB,IO,UNUSED,,4,,,,,,,,,,
T15,,IOB,IO,UNUSED,,3,,,,,,,,,,
T16,,,GND,,,,,,,,,,,,,
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
1 #Release 8.2i - par I.31
2 #Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
3 #Thu Dec 21 09:18:51 2006
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
8 # to support parsing.
9 #
10 #INPUT FILE: fpga_map.ncd
11 #OUTPUT FILE: fpga_pad.csv
12 #PART TYPE: xc2s200
13 #SPEED GRADE: -5
14 #PACKAGE: fg256
15 #
16 # Pinout by Pin Number:
17 #
18 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
19 Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,DCI Value,IO Register,Signal Integrity,
20 A1,,,GND,,,,,,,,,,,,,
21 A2,,IOB,IO,UNUSED,,7,,,,,,,,,,
22 A3,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
23 A4,,IOB,IO,UNUSED,,0,,,,,,,,,,
24 A5,,IOB,IO,UNUSED,,0,,,,,,,,,,
25 A6,,IOB,IO,UNUSED,,0,,,,,,,,,,
26 A7,,IOB,IO,UNUSED,,0,,,,,,,,,,
27 A8,,IOB,IO,UNUSED,,1,,,,,,,,,,
28 A9,,IOB,IO,UNUSED,,1,,,,,,,,,,
29 A10,,IOB,IO,UNUSED,,1,,,,,,,,,,
30 A11,,IOB,IO,UNUSED,,1,,,,,,,,,,
31 A12,,IOB,IO,UNUSED,,1,,,,,,,,,,
32 A13,,IOB,IO,UNUSED,,1,,,,,,,,,,
33 A14,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
34 A15,,,TDI,,,,,,,,,,,,,
35 A16,,,GND,,,,,,,,,,,,,
36 B1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
37 B2,,,GND,,,,,,,,,,,,,
38 B3,,IOB,IO,UNUSED,,0,,,,,,,,,,
39 B4,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
40 B5,,IOB,IO,UNUSED,,0,,,,,,,,,,
41 B6,,IOB,IO,UNUSED,,0,,,,,,,,,,
42 B7,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
43 B8,,GCLKIOB,GCK3,UNUSED,,0,,,,,,,,,,
44 B9,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
45 B10,,IOB,IO,UNUSED,,1,,,,,,,,,,
46 B11,,IOB,IO,UNUSED,,1,,,,,,,,,,
47 B12,,IOB,IO,UNUSED,,1,,,,,,,,,,
48 B13,,IOB,IO_CS,UNUSED,,1,,,,,,,,,,
49 B14,,,TDO,,,,,,,,,,,,,
50 B15,,,GND,,,,,,,,,,,,,
51 B16,,IOB,IO,UNUSED,,2,,,,,,,,,,
52 C1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
53 C2,,IOB,IO,UNUSED,,7,,,,,,,,,,
54 C3,,,VCCINT,,,,,,,,2.5,,,,,
55 C4,,,TCK,,,,,,,,,,,,,
56 C5,,IOB,IO,UNUSED,,0,,,,,,,,,,
57 C6,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,,
58 C7,,IOB,IO,UNUSED,,0,,,,,,,,,,
59 C8,,IOB,IO,UNUSED,,0,,,,,,,,,,
60 C9,,GCLKIOB,GCK2,UNUSED,,1,,,,,,,,,,
61 C10,,IOB,IO,UNUSED,,1,,,,,,,,,,
62 C11,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
63 C12,,IOB,IO,UNUSED,,1,,,,,,,,,,
64 C13,,IOB,IO_WRITE,UNUSED,,1,,,,,,,,,,
65 C14,,,VCCINT,,,,,,,,2.5,,,,,
66 C15,,IOB,IO_DOUT_BUSY,UNUSED,,2,,,,,,,,,,
67 C16,,IOB,IO,UNUSED,,2,,,,,,,,,,
68 D1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
69 D2,,IOB,IO,UNUSED,,7,,,,,,,,,,
70 D3,,,TMS,,,,,,,,,,,,,
71 D4,,,VCCINT,,,,,,,,2.5,,,,,
72 D5,,IOB,IO,UNUSED,,0,,,,,,,,,,
73 D6,,IOB,IO,UNUSED,,0,,,,,,,,,,
74 D7,,IOB,IO,UNUSED,,0,,,,,,,,,,
75 D8,,IOB,IO,UNUSED,,0,,,,,,,,,,
76 D9,,IOB,IO,UNUSED,,1,,,,,,,,,,
77 D10,,IOB,IO,UNUSED,,1,,,,,,,,,,
78 D11,,IOB,IO,UNUSED,,1,,,,,,,,,,
79 D12,,IOB,IO,UNUSED,,1,,,,,,,,,,
80 D13,,,VCCINT,,,,,,,,2.5,,,,,
81 D14,fpga_din_d0,IOB,IO_DIN_D0,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
82 D15,,,CCLK,,,,,,,,,,,,,
83 D16,,IOB,IO,UNUSED,,2,,,,,,,,,,
84 E1,ps2_data,IOB,IO,INPUT,LVTTL,7,,,,IFD,,LOCATED,,YES,NONE,
85 E2,,IOB,IO,UNUSED,,7,,,,,,,,,,
86 E3,reset_n,IOB,IO,INPUT,LVTTL,7,,,,NONE,,LOCATED,,NO,NONE,
87 E4,,IOB,IO,UNUSED,,7,,,,,,,,,,
88 E5,,,VCCINT,,,,,,,,2.5,,,,,
89 E6,,IOB,IO,UNUSED,,0,,,,,,,,,,
90 E7,,IOB,IO,UNUSED,,0,,,,,,,,,,
91 E8,,,VCCO_0,,,0,,,,,any******,,,,,
92 E9,,,VCCO_1,,,1,,,,,any******,,,,,
93 E10,,IOB,IO,UNUSED,,1,,,,,,,,,,
94 E11,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,,
95 E12,,,VCCINT,,,,,,,,2.5,,,,,
96 E13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
97 E14,,IOB,IO,UNUSED,,2,,,,,,,,,,
98 E15,,IOB,IO,UNUSED,,2,,,,,,,,,,
99 E16,fpga_d1,IOB,IO_D1,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
100 F1,,IOB,IO,UNUSED,,7,,,,,,,,,,
101 F2,,IOB,IO,UNUSED,,7,,,,,,,,,,
102 F3,,IOB,IO,UNUSED,,7,,,,,,,,,,
103 F4,ps2_clk,IOB,IO,INPUT,LVTTL,7,,,,IFD,,LOCATED,,YES,NONE,
104 F5,,IOB,IO,UNUSED,,7,,,,,,,,,,
105 F6,,,GND,,,,,,,,,,,,,
106 F7,,,GND,,,,,,,,,,,,,
107 F8,,,VCCO_0,,,0,,,,,any******,,,,,
108 F9,,,VCCO_1,,,1,,,,,any******,,,,,
109 F10,,,GND,,,,,,,,,,,,,
110 F11,,,GND,,,,,,,,,,,,,
111 F12,,IOB,IO,UNUSED,,2,,,,,,,,,,
112 F13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
113 F14,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
114 F15,fpga_d2,IOB,IO_D2,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
115 F16,,IOB,IO,UNUSED,,2,,,,,,,,,,
116 G1,,PCIIOB,IO_IRDY,UNUSED,,7,,,,,,,,,,
117 G2,,IOB,IO,UNUSED,,7,,,,,,,,,,
118 G3,,IOB,IO,UNUSED,,7,,,,,,,,,,
119 G4,,IOB,IO,UNUSED,,7,,,,,,,,,,
120 G5,,IOB,IO,UNUSED,,7,,,,,,,,,,
121 G6,,,GND,,,,,,,,,,,,,
122 G7,,,GND,,,,,,,,,,,,,
123 G8,,,GND,,,,,,,,,,,,,
124 G9,,,GND,,,,,,,,,,,,,
125 G10,,,GND,,,,,,,,,,,,,
126 G11,,,GND,,,,,,,,,,,,,
127 G12,,IOB,IO,UNUSED,,2,,,,,,,,,,
128 G13,,IOB,IO,UNUSED,,2,,,,,,,,,,
129 G14,,IOB,IO,UNUSED,,2,,,,,,,,,,
130 G15,,IOB,IO,UNUSED,,2,,,,,,,,,,
131 G16,fpga_d3,IOB,IO_D3,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
132 H1,,IOB,IO,UNUSED,,6,,,,,,,,,,
133 H2,,IOB,IO,UNUSED,,7,,,,,,,,,,
134 H3,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,,
135 H4,,IOB,IO,UNUSED,,7,,,,,,,,,,
136 H5,,,VCCO_7,,,7,,,,,any******,,,,,
137 H6,,,VCCO_7,,,7,,,,,any******,,,,,
138 H7,,,GND,,,,,,,,,,,,,
139 H8,,,GND,,,,,,,,,,,,,
140 H9,,,GND,,,,,,,,,,,,,
141 H10,,,GND,,,,,,,,,,,,,
142 H11,,,VCCO_2,,,2,,,,,3.30,,,,,
143 H12,,,VCCO_2,,,2,,,,,3.30,,,,,
144 H13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,,
145 H14,,IOB,IO,UNUSED,,2,,,,,,,,,,
146 H15,,IOB,IO,UNUSED,,2,,,,,,,,,,
147 H16,,PCIIOB,IO_IRDY,UNUSED,,2,,,,,,,,,,
148 J1,,IOB,IO,UNUSED,,6,,,,,,,,,,
149 J2,,PCIIOB,IO_TRDY,UNUSED,,6,,,,,,,,,,
150 J3,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
151 J4,,IOB,IO,UNUSED,,6,,,,,,,,,,
152 J5,,,VCCO_6,,,6,,,,,any******,,,,,
153 J6,,,VCCO_6,,,6,,,,,any******,,,,,
154 J7,,,GND,,,,,,,,,,,,,
155 J8,,,GND,,,,,,,,,,,,,
156 J9,,,GND,,,,,,,,,,,,,
157 J10,,,GND,,,,,,,,,,,,,
158 J11,,,VCCO_3,,,3,,,,,3.30,,,,,
159 J12,,,VCCO_3,,,3,,,,,3.30,,,,,
160 J13,,IOB,IO,UNUSED,,2,,,,,,,,,,
161 J14,,IOB,IO,UNUSED,,3,,,,,,,,,,
162 J15,,PCIIOB,IO_TRDY,UNUSED,,3,,,,,,,,,,
163 J16,fpga_d4,IOB,IO_D4,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
164 K1,,IOB,IO,UNUSED,,6,,,,,,,,,,
165 K2,,IOB,IO,UNUSED,,6,,,,,,,,,,
166 K3,,IOB,IO,UNUSED,,6,,,,,,,,,,
167 K4,,IOB,IO,UNUSED,,6,,,,,,,,,,
168 K5,,IOB,IO,UNUSED,,6,,,,,,,,,,
169 K6,,,GND,,,,,,,,,,,,,
170 K7,,,GND,,,,,,,,,,,,,
171 K8,,,GND,,,,,,,,,,,,,
172 K9,,,GND,,,,,,,,,,,,,
173 K10,,,GND,,,,,,,,,,,,,
174 K11,,,GND,,,,,,,,,,,,,
175 K12,,IOB,IO,UNUSED,,3,,,,,,,,,,
176 K13,,IOB,IO,UNUSED,,3,,,,,,,,,,
177 K14,,IOB,IO,UNUSED,,3,,,,,,,,,,
178 K15,,IOB,IO,UNUSED,,3,,,,,,,,,,
179 K16,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
180 L1,,IOB,IO,UNUSED,,6,,,,,,,,,,
181 L2,,IOB,IO,UNUSED,,6,,,,,,,,,,
182 L3,,IOB,IO,UNUSED,,6,,,,,,,,,,
183 L4,,IOB,IO,UNUSED,,6,,,,,,,,,,
184 L5,,IOB,IO,UNUSED,,6,,,,,,,,,,
185 L6,,,GND,,,,,,,,,,,,,
186 L7,,,GND,,,,,,,,,,,,,
187 L8,,,VCCO_5,,,5,,,,,any******,,,,,
188 L9,,,VCCO_4,,,4,,,,,any******,,,,,
189 L10,,,GND,,,,,,,,,,,,,
190 L11,,,GND,,,,,,,,,,,,,
191 L12,,IOB,IO,UNUSED,,3,,,,,,,,,,
192 L13,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
193 L14,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
194 L15,,IOB,IO,UNUSED,,3,,,,,,,,,,
195 L16,,IOB,IO,UNUSED,,3,,,,,,,,,,
196 M1,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
197 M2,,IOB,IO,UNUSED,,6,,,,,,,,,,
198 M3,,IOB,IO,UNUSED,,6,,,,,,,,,,
199 M4,,IOB,IO,UNUSED,,6,,,,,,,,,,
200 M5,,,VCCINT,,,,,,,,2.5,,,,,
201 M6,,IOB,IO,UNUSED,,5,,,,,,,,,,
202 M7,,IOB,IO,UNUSED,,5,,,,,,,,,,
203 M8,,,VCCO_5,,,5,,,,,any******,,,,,
204 M9,,,VCCO_4,,,4,,,,,any******,,,,,
205 M10,,IOB,IO,UNUSED,,4,,,,,,,,,,
206 M11,,IOB,IO,UNUSED,,4,,,,,,,,,,
207 M12,,,VCCINT,,,,,,,,2.5,,,,,
208 M13,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,,
209 M14,,IOB,IO,UNUSED,,3,,,,,,,,,,
210 M15,,IOB,IO,UNUSED,,3,,,,,,,,,,
211 M16,fpga_d5,IOB,IO_D5,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
212 N1,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
213 N2,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,,
214 N3,,,M0,,,,,,,,,,,,,
215 N4,,,VCCINT,,,,,,,,2.5,,,,,
216 N5,,IOB,IO,UNUSED,,5,,,,,,,,,,
217 N6,,IOB,IO,UNUSED,,5,,,,,,,,,,
218 N7,,IOB,IO,UNUSED,,5,,,,,,,,,,
219 N8,,GCLKIOB,GCK0,UNUSED,,4,,,,,,,,,,
220 N9,,IOB,IO,UNUSED,,4,,,,,,,,,,
221 N10,,IOB,IO,UNUSED,,4,,,,,,,,,,
222 N11,,IOB,IO,UNUSED,,4,,,,,,,,,,
223 N12,,IOB,IO,UNUSED,,4,,,,,,,,,,
224 N13,,,VCCINT,,,,,,,,2.5,,,,,
225 N14,fpga_d7,IOB,IO_D7,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
226 N15,,IOB,IO_INIT,UNUSED,,3,,,,,,,,,,
227 N16,fpga_d6,IOB,IO_D6,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
228 P1,,IOB,IO,UNUSED,,6,,,,,,,,,,
229 P2,,,M1,,,,,,,,,,,,,
230 P3,,,VCCINT,,,,,,,,2.5,,,,,
231 P4,,,NC,,,,,,,,,,,,,
232 P5,,IOB,IO,UNUSED,,5,,,,,,,,,,
233 P6,,IOB,IO,UNUSED,,5,,,,,,,,,,
234 P7,,IOB,IO,UNUSED,,5,,,,,,,,,,
235 P8,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
236 P9,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
237 P10,,IOB,IO,UNUSED,,4,,,,,,,,,,
238 P11,,IOB,IO,UNUSED,,4,,,,,,,,,,
239 P12,,IOB,IO,UNUSED,,4,,,,,,,,,,
240 P13,,IOB,IO,UNUSED,,4,,,,,,,,,,
241 P14,,,VCCINT,,,,,,,,2.5,,,,,
242 P15,,,PROGRAM,,,,,,,,,,,,,
243 P16,,IOB,IO,UNUSED,,3,,,,,,,,,,
244 R1,,IOB,IO,UNUSED,,6,,,,,,,,,,
245 R2,,,GND,,,,,,,,,,,,,
246 R3,,,M2,,,,,,,,,,,,,
247 R4,,,NC,,,,,,,,,,,,,
248 R5,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
249 R6,,IOB,IO,UNUSED,,5,,,,,,,,,,
250 R7,,IOB,IO,UNUSED,,5,,,,,,,,,,
251 R8,clka,GCLKIOB,GCK1,INPUT,LVTTL,5,,,,NONE,,LOCATED,,NO,NONE,
252 R9,,IOB,IO,UNUSED,,4,,,,,,,,,,
253 R10,,IOB,IO,UNUSED,,4,,,,,,,,,,
254 R11,,IOB,IO,UNUSED,,4,,,,,,,,,,
255 R12,,IOB,IO,UNUSED,,4,,,,,,,,,,
256 R13,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
257 R14,,,DONE,,,,,,,,,,,,,
258 R15,,,GND,,,,,,,,,,,,,
259 R16,,IOB,IO,UNUSED,,3,,,,,,,,,,
260 T1,,,GND,,,,,,,,,,,,,
261 T2,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
262 T3,,IOB,IO,UNUSED,,5,,,,,,,,,,
263 T4,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,,
264 T5,,IOB,IO,UNUSED,,5,,,,,,,,,,
265 T6,,IOB,IO,UNUSED,,5,,,,,,,,,,
266 T7,,IOB,IO,UNUSED,,5,,,,,,,,,,
267 T8,,IOB,IO,UNUSED,,5,,,,,,,,,,
268 T9,,IOB,IO,UNUSED,,4,,,,,,,,,,
269 T10,,IOB,IO,UNUSED,,4,,,,,,,,,,
270 T11,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
271 T12,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,,
272 T13,,IOB,IO,UNUSED,,4,,,,,,,,,,
273 T14,,IOB,IO,UNUSED,,4,,,,,,,,,,
274 T15,,IOB,IO,UNUSED,,3,,,,,,,,,,
275 T16,,,GND,,,,,,,,,,,,,
276 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
277 #
278 #* Default value.
279 #** This default Pullup/Pulldown value can be overridden in Bitgen.
280 #****** Special VCCO requirements may apply. Please consult the device
281 # family datasheet for specific guideline on VCCO requirements.
282 #
283 #
284 #

286
xilinx/ps2/fpga_pad.txt Normal file
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@@ -0,0 +1,286 @@
Release 8.2i - par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Thu Dec 21 09:18:52 2006
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: fpga_map.ncd
OUTPUT FILE: fpga_pad.txt
PART TYPE: xc2s200
SPEED GRADE: -5
PACKAGE: fg256
Pinout by Pin Number:
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|DCI Value|IO Register|Signal Integrity|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | | |
|A2 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|A3 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | |
|A4 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A6 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A8 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A10 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A11 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A13 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A14 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | |
|A15 | | |TDI | | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | | |
|B1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | |
|B2 | | |GND | | | | | | | | | | | | |
|B3 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|B4 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | |
|B5 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|B6 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|B7 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | |
|B8 | |GCLKIOB |GCK3 |UNUSED | |0 | | | | | | | | | |
|B9 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | |
|B10 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|B11 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|B12 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|B13 | |IOB |IO_CS |UNUSED | |1 | | | | | | | | | |
|B14 | | |TDO | | | | | | | | | | | | |
|B15 | | |GND | | | | | | | | | | | | |
|B16 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|C1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | |
|C2 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|C3 | | |VCCINT | | | | | | | |2.5 | | | | |
|C4 | | |TCK | | | | | | | | | | | | |
|C5 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|C6 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | |
|C7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|C8 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|C9 | |GCLKIOB |GCK2 |UNUSED | |1 | | | | | | | | | |
|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|C11 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | |
|C12 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|C13 | |IOB |IO_WRITE |UNUSED | |1 | | | | | | | | | |
|C14 | | |VCCINT | | | | | | | |2.5 | | | | |
|C15 | |IOB |IO_DOUT_BUSY|UNUSED | |2 | | | | | | | | | |
|C16 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|D1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | |
|D2 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|D3 | | |TMS | | | | | | | | | | | | |
|D4 | | |VCCINT | | | | | | | |2.5 | | | | |
|D5 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|D6 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|D7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|D8 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|D9 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|D10 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|D11 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|D12 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|D13 | | |VCCINT | | | | | | | |2.5 | | | | |
|D14 |fpga_din_d0|IOB |IO_DIN_D0 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|D15 | | |CCLK | | | | | | | | | | | | |
|D16 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|E1 |ps2_data |IOB |IO |INPUT |LVTTL |7 | | | |IFD | |LOCATED | |YES |NONE |
|E2 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|E3 |reset_n |IOB |IO |INPUT |LVTTL |7 | | | |NONE | |LOCATED | |NO |NONE |
|E4 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|E5 | | |VCCINT | | | | | | | |2.5 | | | | |
|E6 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|E7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|E8 | | |VCCO_0 | | |0 | | | | |any******| | | | |
|E9 | | |VCCO_1 | | |1 | | | | |any******| | | | |
|E10 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|E11 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | |
|E12 | | |VCCINT | | | | | | | |2.5 | | | | |
|E13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | |
|E14 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|E15 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|E16 |fpga_d1 |IOB |IO_D1 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|F1 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|F2 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|F3 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|F4 |ps2_clk |IOB |IO |INPUT |LVTTL |7 | | | |IFD | |LOCATED | |YES |NONE |
|F5 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|F6 | | |GND | | | | | | | | | | | | |
|F7 | | |GND | | | | | | | | | | | | |
|F8 | | |VCCO_0 | | |0 | | | | |any******| | | | |
|F9 | | |VCCO_1 | | |1 | | | | |any******| | | | |
|F10 | | |GND | | | | | | | | | | | | |
|F11 | | |GND | | | | | | | | | | | | |
|F12 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|F13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | |
|F14 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | |
|F15 |fpga_d2 |IOB |IO_D2 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|F16 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|G1 | |PCIIOB |IO_IRDY |UNUSED | |7 | | | | | | | | | |
|G2 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|G3 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|G4 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|G5 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|G6 | | |GND | | | | | | | | | | | | |
|G7 | | |GND | | | | | | | | | | | | |
|G8 | | |GND | | | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | | |
|G10 | | |GND | | | | | | | | | | | | |
|G11 | | |GND | | | | | | | | | | | | |
|G12 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|G13 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|G14 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|G15 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|G16 |fpga_d3 |IOB |IO_D3 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|H1 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|H2 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|H3 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | |
|H4 | |IOB |IO |UNUSED | |7 | | | | | | | | | |
|H5 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|H6 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|H7 | | |GND | | | | | | | | | | | | |
|H8 | | |GND | | | | | | | | | | | | |
|H9 | | |GND | | | | | | | | | | | | |
|H10 | | |GND | | | | | | | | | | | | |
|H11 | | |VCCO_2 | | |2 | | | | |3.30 | | | | |
|H12 | | |VCCO_2 | | |2 | | | | |3.30 | | | | |
|H13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | |
|H14 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|H15 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|H16 | |PCIIOB |IO_IRDY |UNUSED | |2 | | | | | | | | | |
|J1 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|J2 | |PCIIOB |IO_TRDY |UNUSED | |6 | | | | | | | | | |
|J3 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | |
|J4 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|J5 | | |VCCO_6 | | |6 | | | | |any******| | | | |
|J6 | | |VCCO_6 | | |6 | | | | |any******| | | | |
|J7 | | |GND | | | | | | | | | | | | |
|J8 | | |GND | | | | | | | | | | | | |
|J9 | | |GND | | | | | | | | | | | | |
|J10 | | |GND | | | | | | | | | | | | |
|J11 | | |VCCO_3 | | |3 | | | | |3.30 | | | | |
|J12 | | |VCCO_3 | | |3 | | | | |3.30 | | | | |
|J13 | |IOB |IO |UNUSED | |2 | | | | | | | | | |
|J14 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|J15 | |PCIIOB |IO_TRDY |UNUSED | |3 | | | | | | | | | |
|J16 |fpga_d4 |IOB |IO_D4 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|K1 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|K2 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|K3 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|K4 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|K5 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|K6 | | |GND | | | | | | | | | | | | |
|K7 | | |GND | | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | | |
|K10 | | |GND | | | | | | | | | | | | |
|K11 | | |GND | | | | | | | | | | | | |
|K12 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|K13 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|K14 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|K15 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|K16 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | |
|L1 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|L2 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|L3 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|L4 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|L5 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|L6 | | |GND | | | | | | | | | | | | |
|L7 | | |GND | | | | | | | | | | | | |
|L8 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|L9 | | |VCCO_4 | | |4 | | | | |any******| | | | |
|L10 | | |GND | | | | | | | | | | | | |
|L11 | | |GND | | | | | | | | | | | | |
|L12 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|L13 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | |
|L14 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | |
|L15 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|L16 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|M1 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | |
|M2 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|M3 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|M4 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|M5 | | |VCCINT | | | | | | | |2.5 | | | | |
|M6 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|M7 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|M8 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|M9 | | |VCCO_4 | | |4 | | | | |any******| | | | |
|M10 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|M11 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |2.5 | | | | |
|M13 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | |
|M14 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|M15 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|M16 |fpga_d5 |IOB |IO_D5 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N1 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | |
|N2 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | |
|N3 | | |M0 | | | | | | | | | | | | |
|N4 | | |VCCINT | | | | | | | |2.5 | | | | |
|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|N6 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|N7 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|N8 | |GCLKIOB |GCK0 |UNUSED | |4 | | | | | | | | | |
|N9 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|N10 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|N11 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|N12 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|N13 | | |VCCINT | | | | | | | |2.5 | | | | |
|N14 |fpga_d7 |IOB |IO_D7 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N15 | |IOB |IO_INIT |UNUSED | |3 | | | | | | | | | |
|N16 |fpga_d6 |IOB |IO_D6 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P1 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|P2 | | |M1 | | | | | | | | | | | | |
|P3 | | |VCCINT | | | | | | | |2.5 | | | | |
|P4 | | |NC | | | | | | | | | | | | |
|P5 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|P6 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|P8 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | |
|P9 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | |
|P10 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|P11 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|P12 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|P13 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|P14 | | |VCCINT | | | | | | | |2.5 | | | | |
|P15 | | |PROGRAM | | | | | | | | | | | | |
|P16 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|R1 | |IOB |IO |UNUSED | |6 | | | | | | | | | |
|R2 | | |GND | | | | | | | | | | | | |
|R3 | | |M2 | | | | | | | | | | | | |
|R4 | | |NC | | | | | | | | | | | | |
|R5 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | |
|R6 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|R7 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|R8 |clka |GCLKIOB |GCK1 |INPUT |LVTTL |5 | | | |NONE | |LOCATED | |NO |NONE |
|R9 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|R10 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|R11 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|R12 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|R13 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | |
|R14 | | |DONE | | | | | | | | | | | | |
|R15 | | |GND | | | | | | | | | | | | |
|R16 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|T1 | | |GND | | | | | | | | | | | | |
|T2 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | |
|T3 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|T4 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | |
|T5 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|T6 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|T7 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|T8 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|T9 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|T10 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|T11 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | |
|T12 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | |
|T13 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|T14 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|T15 | |IOB |IO |UNUSED | |3 | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | | |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

165
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD COLSPAN='4'><B>PS2 Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ps2.ise</TD>
<TD BGCOLOR='#FFFF99'><B>Current State:</B></TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>fpga</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD ALIGN=LEFT>No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc2s200-5fg256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>21 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 8.2i</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
<TD>Wed Dec 27 10:45:57 2006</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>PS2 Partition Summary</B></TD></TR>
<TR><TD COLSPAN='4'>No partition information was found.</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='5'><B>Device Utilization Summary</B></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>37</TD>
<TD ALIGN=RIGHT>4,704</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>39</TD>
<TD ALIGN=RIGHT>4,704</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of occupied Slices</TD>
<TD ALIGN=RIGHT>39</TD>
<TD ALIGN=RIGHT>2,352</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>39</TD>
<TD ALIGN=RIGHT>39</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>39</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>52</TD>
<TD ALIGN=RIGHT>4,704</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>39</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as a route-thru</TD>
<TD ALIGN=RIGHT>13</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of bonded <A HREF_DISABLED='fpga_map.mrp?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>11</TD>
<TD ALIGN=RIGHT>176</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of GCLKs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>50%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of GCLKIOBs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>25%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total equivalent gate count for design</B></TD>
<TD ALIGN=RIGHT>630</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Additional JTAG gate count for IOBs</TD>
<TD ALIGN=RIGHT>576</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Performance Summary</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD><A HREF_DISABLED='fpga.pad?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD>
<TD><A HREF_DISABLED='fpga.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD><A HREF_DISABLED='fpga.par?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD><A HREF_DISABLED='fpga.par?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:27 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>18 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:36 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:44 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>3 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:52 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:57 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:19:06 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD>Xplorer Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
</TABLE>
</BODY></HTML>

412
xilinx/ps2/fpga_usage.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="18">
<DesignStatistics TimeStamp="Thu Dec 21 09:19:06 2006"><group name="NetStatistics">
<item name="NumNets_Active" rev="18">
<attrib name="value" value="89"/></item>
<item name="NumNets_Gnd" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BACKBONE" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BIHEX" rev="18">
<attrib name="value" value="44"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="18">
<attrib name="value" value="26"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="18">
<attrib name="value" value="32"/></item>
<item name="NumNodesOfType_Active_DUMMY" rev="18">
<attrib name="value" value="159"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="18">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_HLONG" rev="18">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="18">
<attrib name="value" value="165"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="18">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_OMUX" rev="18">
<attrib name="value" value="127"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="18">
<attrib name="value" value="74"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="18">
<attrib name="value" value="266"/></item>
<item name="NumNodesOfType_Active_UNIHEX" rev="18">
<attrib name="value" value="26"/></item>
<item name="NumNodesOfType_Active_VLONG" rev="18">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Gnd_DUMMY" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Gnd_INPUT" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Gnd_OMUX" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Gnd_OUTPUT" rev="18">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Gnd_SINGLE" rev="18">
<attrib name="value" value="1"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Thu Dec 21 09:19:06 2006"><group name="SiteSummary">
<item name="GCLK" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="GCLKIOB" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="GCLKIOB_GCLK_BUF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="GCLKIOB_PAD" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="GCLK_CE_POWER" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="GCLK_GCLK_BUFFER" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="IOB_DELAY" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_IFF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_INBUF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="IOB_OUTBUF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="8"/></item>
<item name="IOB_PAD" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="SLICE" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="39"/></item>
<item name="SLICE_CY0" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="SLICE_CYMUXF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
<item name="SLICE_CYMUXG" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="SLICE_F" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="SLICE_F5MUX" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="SLICE_FFX" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="15"/></item>
<item name="SLICE_FFY" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="SLICE_G" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="30"/></item>
<item name="SLICE_GNDF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="SLICE_GNDG" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="SLICE_XORF" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="SLICE_XORG" rev="18">
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Thu Dec 21 09:19:06 2006"><group name="IOB_IFF">
<item name="FFATTRBOX" rev="18">
<attrib name="ASYNC" value="2"/></item>
<item name="IFFINITATTR" rev="18">
<attrib name="HIGH" value="1"/><attrib name="LOW" value="1"/></item>
<item name="LATCH_OR_FF" rev="18">
<attrib name="FF" value="2"/></item>
</group>
<group name="SLICE_FFX">
<item name="INITX" rev="18">
<attrib name="HIGH" value="2"/><attrib name="LOW" value="13"/></item>
<item name="LATCH_OR_FF" rev="18">
<attrib name="FF" value="15"/></item>
<item name="SYNC_ATTR" rev="18">
<attrib name="ASYNC" value="15"/></item>
</group>
<group name="SLICE_FFY">
<item name="INITY" rev="18">
<attrib name="HIGH" value="2"/><attrib name="LOW" value="20"/></item>
<item name="LATCH_OR_FF" rev="18">
<attrib name="FF" value="22"/></item>
<item name="SYNC_ATTR" rev="18">
<attrib name="ASYNC" value="22"/></item>
</group>
<group name="GCLK_GCLK_BUFFER">
<item name="DISABLE_ATTR" rev="18">
<attrib name="LOW" value="2"/></item>
</group>
<group name="SLICE_F">
<item name="LUT_OR_MEM" rev="18">
<attrib name="LUT" value="22"/></item>
</group>
<group name="SLICE_G">
<item name="LUT_OR_MEM" rev="18">
<attrib name="LUT" value="30"/></item>
</group>
<group name="IOB_PAD">
<item name="DRIVEATTRBOX" rev="18">
<attrib name="12" value="8"/></item>
<item name="IOATTRBOX" rev="18">
<attrib name="LVTTL" value="11"/></item>
<item name="SLEW" rev="18">
<attrib name="SLOW" value="8"/></item>
</group>
<group name="IOB_OFF">
<item name="LATCH_OR_FF" rev="0">
<attrib name="FF" value="7"/></item>
<item name="OFFATTRBOX" rev="0">
<attrib name="LOW" value="7"/></item>
</group>
<group name="GCLKIOB_PAD">
<item name="IOATTRBOX" rev="18">
<attrib name="LVTTL" value="1"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Thu Dec 21 09:19:06 2006"><group name="IOB_IFF">
<item name="CE" rev="18">
<attrib name="value" value="1"/></item>
<item name="CK" rev="18">
<attrib name="value" value="2"/></item>
<item name="D" rev="18">
<attrib name="value" value="2"/></item>
<item name="INIT" rev="18">
<attrib name="value" value="2"/></item>
<item name="Q" rev="18">
<attrib name="value" value="2"/></item>
</group>
<group name="GCLK_CE_POWER">
<item name="1" rev="18">
<attrib name="value" value="2"/></item>
</group>
<group name="GCLK">
<item name="IN" rev="18">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="2"/></item>
</group>
<group name="IOB_O_VCC">
<item name="1" rev="0">
<attrib name="value" value="5"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="18">
<attrib name="value" value="8"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="8"/></item>
</group>
<group name="SLICE_CY0">
<item name="0" rev="18">
<attrib name="value" value="1"/></item>
</group>
<group name="IOB_DELAY">
<item name="IN" rev="18">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="2"/></item>
</group>
<group name="SLICE_GNDF">
<item name="0" rev="18">
<attrib name="value" value="6"/></item>
</group>
<group name="SLICE_FFX">
<item name="CE" rev="18">
<attrib name="value" value="4"/></item>
<item name="CK" rev="18">
<attrib name="value" value="15"/></item>
<item name="D" rev="18">
<attrib name="value" value="15"/></item>
<item name="INIT" rev="18">
<attrib name="value" value="15"/></item>
<item name="Q" rev="18">
<attrib name="value" value="15"/></item>
</group>
<group name="SLICE_GNDG">
<item name="0" rev="18">
<attrib name="value" value="5"/></item>
</group>
<group name="SLICE_FFY">
<item name="CE" rev="18">
<attrib name="value" value="5"/></item>
<item name="CK" rev="18">
<attrib name="value" value="22"/></item>
<item name="D" rev="18">
<attrib name="value" value="22"/></item>
<item name="INIT" rev="18">
<attrib name="value" value="22"/></item>
<item name="Q" rev="18">
<attrib name="value" value="22"/></item>
</group>
<group name="IOB_O_GROUND">
<item name="0" rev="0">
<attrib name="value" value="1"/></item>
</group>
<group name="GCLK_GCLK_BUFFER">
<item name="CE" rev="18">
<attrib name="value" value="2"/></item>
<item name="IN" rev="18">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="2"/></item>
</group>
<group name="SLICE_F5MUX">
<item name="F" rev="18">
<attrib name="value" value="2"/></item>
<item name="G" rev="18">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="2"/></item>
<item name="S0" rev="18">
<attrib name="value" value="2"/></item>
</group>
<group name="GCLKIOB">
<item name="GCLKOUT" rev="18">
<attrib name="value" value="1"/></item>
<item name="PAD" rev="18">
<attrib name="value" value="1"/></item>
</group>
<group name="SLICE_CYMUXF">
<item name="0" rev="18">
<attrib name="value" value="7"/></item>
<item name="1" rev="18">
<attrib name="value" value="7"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="7"/></item>
<item name="S0" rev="18">
<attrib name="value" value="7"/></item>
</group>
<group name="SLICE_CYMUXG">
<item name="0" rev="18">
<attrib name="value" value="6"/></item>
<item name="1" rev="18">
<attrib name="value" value="6"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="6"/></item>
<item name="S0" rev="18">
<attrib name="value" value="6"/></item>
</group>
<group name="IOB_INBUF">
<item name="IN" rev="18">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="3"/></item>
</group>
<group name="SLICE">
<item name="BX" rev="18">
<attrib name="value" value="9"/></item>
<item name="BY" rev="18">
<attrib name="value" value="9"/></item>
<item name="CE" rev="18">
<attrib name="value" value="5"/></item>
<item name="CIN" rev="18">
<attrib name="value" value="6"/></item>
<item name="CLK" rev="18">
<attrib name="value" value="24"/></item>
<item name="COUT" rev="18">
<attrib name="value" value="6"/></item>
<item name="F1" rev="18">
<attrib name="value" value="22"/></item>
<item name="F2" rev="18">
<attrib name="value" value="16"/></item>
<item name="F3" rev="18">
<attrib name="value" value="9"/></item>
<item name="F4" rev="18">
<attrib name="value" value="8"/></item>
<item name="G1" rev="18">
<attrib name="value" value="30"/></item>
<item name="G2" rev="18">
<attrib name="value" value="24"/></item>
<item name="G3" rev="18">
<attrib name="value" value="13"/></item>
<item name="G4" rev="18">
<attrib name="value" value="11"/></item>
<item name="SR" rev="18">
<attrib name="value" value="24"/></item>
<item name="X" rev="18">
<attrib name="value" value="13"/></item>
<item name="XQ" rev="18">
<attrib name="value" value="15"/></item>
<item name="Y" rev="18">
<attrib name="value" value="15"/></item>
<item name="YQ" rev="18">
<attrib name="value" value="22"/></item>
</group>
<group name="SLICE_F">
<item name="A1" rev="18">
<attrib name="value" value="21"/></item>
<item name="A2" rev="18">
<attrib name="value" value="16"/></item>
<item name="A3" rev="18">
<attrib name="value" value="9"/></item>
<item name="A4" rev="18">
<attrib name="value" value="8"/></item>
<item name="D" rev="18">
<attrib name="value" value="22"/></item>
</group>
<group name="SLICE_G">
<item name="A1" rev="18">
<attrib name="value" value="29"/></item>
<item name="A2" rev="18">
<attrib name="value" value="24"/></item>
<item name="A3" rev="18">
<attrib name="value" value="13"/></item>
<item name="A4" rev="18">
<attrib name="value" value="11"/></item>
<item name="D" rev="18">
<attrib name="value" value="30"/></item>
</group>
<group name="IOB_PAD">
<item name="PAD" rev="18">
<attrib name="value" value="11"/></item>
</group>
<group name="IOB_OFF">
<item name="CK" rev="0">
<attrib name="value" value="7"/></item>
<item name="D" rev="0">
<attrib name="value" value="7"/></item>
<item name="Q" rev="0">
<attrib name="value" value="7"/></item>
</group>
<group name="IOB">
<item name="CLK" rev="18">
<attrib name="value" value="2"/></item>
<item name="I" rev="18">
<attrib name="value" value="1"/></item>
<item name="ICE" rev="18">
<attrib name="value" value="1"/></item>
<item name="IQ" rev="18">
<attrib name="value" value="2"/></item>
<item name="O" rev="18">
<attrib name="value" value="8"/></item>
<item name="PAD" rev="18">
<attrib name="value" value="11"/></item>
<item name="SR" rev="18">
<attrib name="value" value="2"/></item>
</group>
<group name="SLICE_XORF">
<item name="0" rev="18">
<attrib name="value" value="6"/></item>
<item name="1" rev="18">
<attrib name="value" value="6"/></item>
<item name="O" rev="18">
<attrib name="value" value="6"/></item>
</group>
<group name="SLICE_XORG">
<item name="0" rev="18">
<attrib name="value" value="7"/></item>
<item name="1" rev="18">
<attrib name="value" value="7"/></item>
<item name="O" rev="18">
<attrib name="value" value="7"/></item>
</group>
<group name="GCLKIOB_GCLK_BUF">
<item name="IN" rev="18">
<attrib name="value" value="1"/></item>
<item name="OUT" rev="18">
<attrib name="value" value="1"/></item>
</group>
<group name="GCLKIOB_PAD">
<item name="PAD" rev="18">
<attrib name="value" value="1"/></item>
</group>
</ReportPinData>
<CmdHistory>
</CmdHistory>
</DesignSummary>

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xilinx/ps2/ps2.ntrc_log Normal file
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2
xilinx/ps2/xst/work/hdllib.ref Normal file
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MO fpga NULL ../../v/fpga2.v vlg22/fpga.bin 1166710699
MO ps2 NULL ../../v/ps2.v vlg61/ps2.bin 1166710699

BIN
xilinx/ps2/xst/work/vlg22/fpga.bin Normal file
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89
xilinx/scancode/_xmsgs/xst.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">7</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">sc</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">ascii</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">ps2_clk</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">ps2_data</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_hsync_n</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_red0</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_red1</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_red2</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_green0</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_green1</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_green2</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">clkb</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_blue0</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_blue1</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_blue2</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">vga_vsync_n</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">vsync</arg>&gt; is never used or assigned.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">kb_ascii_rdy</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">hsync</arg>&gt; is never used or assigned.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">kb_release</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">pixel</arg>&gt; is never used or assigned.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">strobe_out</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">scancode_convert</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">key_up</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">scancode_convert</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">scancode_convert/strobe_out</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">fpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">scancode_convert/key_up</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">fpga</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">gray_cnt_FFd1</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>
<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

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xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr

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work

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verilog work "../../v/scancode.v"
verilog work "../../v/fpga3.v"

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Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s
-->
Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s
-->
Reading design: fpga.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "fpga.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "fpga"
Output Format : NGC
Target Device : xc2s200-5-fg256
---- Source Options
Top Module Name : fpga
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Multiplier Style : lut
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Write Timing Constraints : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
lso : fpga.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
tristate2logic : Yes
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../../v/scancode.v" in library work
Compiling verilog include file "../../v/scancode_rom.v"
Module <scancode_rom> compiled
Compiling verilog file "../../v/fpga3.v" in library work
Module <scancode_convert> compiled
Module <fpga> compiled
No errors in compilation
Analysis of file <"fpga.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <fpga> in library <work>.
Analyzing hierarchy for module <scancode_convert> in library <work> with parameters.
C_KEYRELEASE = "001000"
C_IDLE = "000010"
C_HOLD = "100000"
C_INIT = "000001"
C_KEYPRESS = "000100"
C_RELEASE = "010000"
Analyzing hierarchy for module <scancode_rom> in library <work>.
Building hierarchy successfully finished.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <fpga>.
Module <fpga> is correct for synthesis.
Analyzing module <scancode_convert> in library <work>.
C_INIT = 6'b000001
C_IDLE = 6'b000010
C_KEYPRESS = 6'b000100
C_KEYRELEASE = 6'b001000
C_RELEASE = 6'b010000
C_HOLD = 6'b100000
"../../v/scancode.v" line 129: Found Full Case directive in module <scancode_convert>.
Module <scancode_convert> is correct for synthesis.
Analyzing module <scancode_rom> in library <work>.
Module <scancode_rom> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <scancode_rom>.
Related source file is "../../v/scancode_rom.v".
Unit <scancode_rom> synthesized.
Synthesizing Unit <scancode_convert>.
Related source file is "../../v/scancode.v".
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 6 |
| Transitions | 13 |
| Inputs | 7 |
| Outputs | 6 |
| Clock | clock (rising_edge) |
| Reset | reset_n (negative) |
| Reset type | asynchronous |
| Reset State | 000001 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
WARNING:Xst:737 - Found 7-bit latch for signal <sc>.
WARNING:Xst:737 - Found 8-bit latch for signal <ascii>.
Found 1-bit register for signal <strobe_out>.
Found 1-bit register for signal <key_up>.
Found 8-bit subtractor for signal <$addsub0000> created at line 184.
Found 1-bit register for signal <capslock>.
Found 1-bit register for signal <ctrl>.
Found 1-bit register for signal <release_prefix>.
Found 1-bit register for signal <shift>.
Summary:
inferred 1 Finite State Machine(s).
inferred 6 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
Unit <scancode_convert> synthesized.
Synthesizing Unit <fpga>.
Related source file is "../../v/fpga3.v".
WARNING:Xst:647 - Input <ps2_clk> is never used.
WARNING:Xst:647 - Input <ps2_data> is never used.
WARNING:Xst:1306 - Output <vga_hsync_n> is never assigned.
WARNING:Xst:1306 - Output <vga_red0> is never assigned.
WARNING:Xst:1306 - Output <vga_red1> is never assigned.
WARNING:Xst:1306 - Output <vga_red2> is never assigned.
WARNING:Xst:1306 - Output <vga_green0> is never assigned.
WARNING:Xst:1306 - Output <vga_green1> is never assigned.
WARNING:Xst:1306 - Output <vga_green2> is never assigned.
WARNING:Xst:647 - Input <clkb> is never used.
WARNING:Xst:1306 - Output <vga_blue0> is never assigned.
WARNING:Xst:1306 - Output <vga_blue1> is never assigned.
WARNING:Xst:1306 - Output <vga_blue2> is never assigned.
WARNING:Xst:1306 - Output <vga_vsync_n> is never assigned.
WARNING:Xst:1780 - Signal <vsync> is never used or assigned.
WARNING:Xst:646 - Signal <kb_ascii_rdy> is assigned but never used.
WARNING:Xst:1780 - Signal <hsync> is never used or assigned.
WARNING:Xst:646 - Signal <kb_release> is assigned but never used.
WARNING:Xst:1780 - Signal <pixel> is never used or assigned.
Found finite state machine <FSM_1> for signal <gray_cnt>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 4 |
| Inputs | 0 |
| Outputs | 2 |
| Clock | clka (rising_edge) |
| Reset | reset_n (negative) |
| Reset type | asynchronous |
| Reset State | 00 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 3-bit up counter for signal <clk8>.
Found 1-bit register for signal <kb_rdy>.
Found 8-bit up counter for signal <kb_scancode>.
Summary:
inferred 1 Finite State Machine(s).
inferred 2 Counter(s).
inferred 1 D-type flip-flop(s).
Unit <fpga> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
8-bit subtractor : 1
# Counters : 2
3-bit up counter : 1
8-bit up counter : 1
# Registers : 7
1-bit register : 7
# Latches : 2
7-bit latch : 1
8-bit latch : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <gray_cnt> on signal <gray_cnt[1:2]> with gray encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
11 | 11
10 | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <scancode_convert/state> on signal <state[1:3]> with sequential encoding.
--------------------
State | Encoding
--------------------
000001 | 000
000010 | 001
010000 | 010
001000 | 011
000100 | 100
100000 | 101
--------------------
Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
WARNING:Xst:1291 - FF/Latch <strobe_out> is unconnected in block <scancode_convert>.
WARNING:Xst:1291 - FF/Latch <key_up> is unconnected in block <scancode_convert>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Adders/Subtractors : 1
8-bit subtractor : 1
# Counters : 2
3-bit up counter : 1
8-bit up counter : 1
# Registers : 12
Flip-Flops : 12
# Latches : 2
7-bit latch : 1
8-bit latch : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <fpga> ...
Optimizing unit <scancode_convert> ...
Optimizing unit <scancode_rom> ...
Mapping all equations...
WARNING:Xst:1291 - FF/Latch <scancode_convert/strobe_out> is unconnected in block <fpga>.
WARNING:Xst:1291 - FF/Latch <scancode_convert/key_up> is unconnected in block <fpga>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 4.
Final Macro Processing ...
Processing Unit <fpga> :
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <gray_cnt_FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <fpga> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 21
Flip-Flops : 21
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : fpga.ngr
Top Level Output File Name : fpga
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 24
Cell Usage :
# BELS : 191
# GND : 1
# INV : 5
# LUT1 : 7
# LUT2 : 13
# LUT3 : 22
# LUT3_D : 1
# LUT3_L : 2
# LUT4 : 106
# LUT4_D : 4
# LUT4_L : 1
# MUXCY : 7
# MUXF5 : 14
# VCC : 1
# XORCY : 7
# FlipFlops/Latches : 36
# FDC : 5
# FDCE : 12
# FDE : 1
# FDP : 3
# LD : 8
# LDE : 7
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 9
# IBUF : 1
# OBUF : 8
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s200fg256-5
Number of Slices: 88 out of 2352 3%
Number of Slice Flip Flops: 28 out of 4704 0%
Number of 4 input LUTs: 161 out of 4704 3%
Number of IOs: 24
Number of bonded IOBs: 10 out of 180 5%
IOB Flip Flops: 8
Number of GCLKs: 1 out of 4 25%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
----------------------------------------------------------------+----------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
----------------------------------------------------------------+----------------------------------+-------+
gray_cnt_FFd1 | NONE(kb_scancode_2) | 19 |
clka | BUFGP | 2 |
scancode_convert/strobe_out_set(scancode_convert/state_Out11:O) | NONE(*)(scancode_convert/ascii_0)| 8 |
scancode_convert/_cmp_eq0005(scancode_convert/state_FFd1-In21:O)| NONE(*)(scancode_convert/sc_3) | 7 |
----------------------------------------------------------------+----------------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
-------------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-------------------------------------+------------------------+-------+
clk8_Aset_inv(clk8_Aset_inv1_INV_0:O)| NONE(kb_scancode_2) | 20 |
-------------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 11.005ns (Maximum Frequency: 90.868MHz)
Minimum input arrival time before clock: 3.150ns
Maximum output required time after clock: 8.128ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'gray_cnt_FFd1'
Clock period: 11.005ns (frequency: 90.868MHz)
Total number of paths / destination ports: 260 / 31
-------------------------------------------------------------------------
Delay: 11.005ns (Levels of Logic = 4)
Source: kb_scancode_2 (FF)
Destination: scancode_convert/state_FFd3 (FF)
Source Clock: gray_cnt_FFd1 rising
Destination Clock: gray_cnt_FFd1 rising
Data Path: kb_scancode_2 to scancode_convert/state_FFd3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 8 1.292 2.050 kb_scancode_2 (kb_scancode_2)
LUT4_D:I1->O 2 0.653 1.340 scancode_convert/_cmp_eq000211 (scancode_convert/N21)
LUT4:I0->O 3 0.653 1.480 scancode_convert/_cmp_eq0000 (scancode_convert/_cmp_eq0000)
MUXF5:S->O 1 0.981 1.150 scancode_convert/state_FFd3-In_SW0_SW0 (N1336)
LUT4:I1->O 1 0.653 0.000 scancode_convert/state_FFd3-In (scancode_convert/state_FFd3-In)
FDC:D 0.753 scancode_convert/state_FFd3
----------------------------------------
Total 11.005ns (4.985ns logic, 6.020ns route)
(45.3% logic, 54.7% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clka'
Clock period: 7.048ns (frequency: 141.884MHz)
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay: 7.048ns (Levels of Logic = 1)
Source: gray_cnt_FFd1 (FF)
Destination: gray_cnt_FFd2 (FF)
Source Clock: clka rising
Destination Clock: clka rising
Data Path: gray_cnt_FFd1 to gray_cnt_FFd2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 20 1.292 3.200 gray_cnt_FFd1 (gray_cnt_FFd1)
INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In)
FDC:D 0.753 gray_cnt_FFd2
----------------------------------------
Total 7.048ns (2.698ns logic, 4.350ns route)
(38.3% logic, 61.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd1'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 3.150ns (Levels of Logic = 1)
Source: reset_n (PAD)
Destination: kb_rdy (FF)
Destination Clock: gray_cnt_FFd1 rising
Data Path: reset_n to kb_rdy
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.924 1.340 reset_n_IBUF (reset_n_IBUF)
FDE:CE 0.886 kb_rdy
----------------------------------------
Total 3.150ns (1.810ns logic, 1.340ns route)
(57.5% logic, 42.5% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'scancode_convert/strobe_out_set'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 8.128ns (Levels of Logic = 1)
Source: scancode_convert/ascii_7 (LATCH)
Destination: fpga_din_d0 (PAD)
Source Clock: scancode_convert/strobe_out_set falling
Data Path: scancode_convert/ascii_7 to fpga_din_d0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 1.421 1.150 scancode_convert/ascii_7 (scancode_convert/ascii_7)
OBUF:I->O 5.557 fpga_din_d0_OBUF (fpga_din_d0)
----------------------------------------
Total 8.128ns (6.978ns logic, 1.150ns route)
(85.9% logic, 14.1% route)
=========================================================================
CPU : 13.09 / 13.20 s | Elapsed : 14.00 / 14.00 s
-->
Total memory usage is 245536 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 25 ( 0 filtered)
Number of infos : 2 ( 0 filtered)

54
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn fpga.prj
-ifmt mixed
-ofn fpga
-ofmt NGC
-p xc2s200-5-fg256
-top fpga
-opt_mode Speed
-opt_level 1
-iuc NO
-lso fpga.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-mult_style lut
-iobuf YES
-max_fanout 100
-bufg 4
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-tristate2logic Yes
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

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xilinx/scancode/fpga_summary.html Normal file
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD COLSPAN='4'><B>SCANCODE Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>scancode.ise</TD>
<TD BGCOLOR='#FFFF99'><B>Current State:</B></TD>
<TD>Synthesized</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>fpga</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD ALIGN=LEFT>No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc2s200-5fg256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>25 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 8.2i</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
<TD>Wed Dec 27 11:41:43 2006</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>SCANCODE Partition Summary</B></TD></TR>
<TR><TD COLSPAN='4'>No partition information was found.</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD></TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slices</TD>
<TD ALIGN=RIGHT>88</TD>
<TD ALIGN=RIGHT>2352</TD>
<TD ALIGN=RIGHT>3%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>28</TD>
<TD ALIGN=RIGHT>4704</TD>
<TD ALIGN=RIGHT>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>161</TD>
<TD ALIGN=RIGHT>4704</TD>
<TD ALIGN=RIGHT>3%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
<TD ALIGN=RIGHT>10</TD>
<TD ALIGN=RIGHT>180</TD>
<TD ALIGN=RIGHT>5%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GCLKs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>25%</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Dec 27 11:41:42 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>25 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD>Xplorer Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
</TABLE>
</BODY></HTML>

0
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MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167237688
MO scancode_convert NULL ../../v/scancode.v vlg3C/scancode__convert.bin 1167237688
MO fpga NULL ../../v/fpga3.v vlg22/fpga.bin 1167237688
MO test NULL ../../v/scancode.v vlg34/test.bin 1167237381

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">63</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">69</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">75</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">80</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">87</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">92</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">93</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">101</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">109</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
<msg type="error" file="Xst" num="850" delta="unknown" >&quot;<arg fmt="%s" index="1">../../v/scancode2.v</arg>&quot; line <arg fmt="%d" index="2">110</arg>: Unsupported <arg fmt="%s" index="3">Event Control Statement</arg>.
</msg>
</messages>

1
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xst -ise "/mwave/work/nt/xess/xilinx/scancode2/scancode2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr

1
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work

2
xilinx/scancode2/fpga.prj Normal file
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verilog work "../../v/scancode2.v"
verilog work "../../v/fpga3.v"

152
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Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s
-->
Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s
-->
Reading design: fpga.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "fpga.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "fpga"
Output Format : NGC
Target Device : xc2s200-5-fg256
---- Source Options
Top Module Name : fpga
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Multiplier Style : lut
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Write Timing Constraints : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
lso : fpga.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
tristate2logic : Yes
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../../v/scancode2.v" in library work
Compiling verilog include file "../../v/scancode_rom.v"
Module <scancode_rom> compiled
Module <scancode_convert> compiled
Compiling verilog file "../../v/fpga3.v" in library work
Module <test> compiled
Module <fpga> compiled
No errors in compilation
Analysis of file <"fpga.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <fpga> in library <work>.
Analyzing hierarchy for module <scancode_convert> in library <work>.
Analyzing hierarchy for module <scancode_rom> in library <work>.
Building hierarchy successfully finished.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <fpga>.
Module <fpga> is correct for synthesis.
Analyzing module <scancode_convert> in library <work>.
ERROR:Xst:850 - "../../v/scancode2.v" line 63: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 69: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 75: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 80: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 87: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 92: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 93: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 101: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 109: Unsupported Event Control Statement.
ERROR:Xst:850 - "../../v/scancode2.v" line 110: Unsupported Event Control Statement.
Found 10 error(s). Aborting synthesis.
-->
Total memory usage is 216028 kilobytes
Number of errors : 10 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

54
xilinx/scancode2/fpga.xst Normal file
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn fpga.prj
-ifmt mixed
-ofn fpga
-ofmt NGC
-p xc2s200-5-fg256
-top fpga
-opt_mode Speed
-opt_level 1
-iuc NO
-lso fpga.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-mult_style lut
-iobuf YES
-max_fanout 100
-bufg 4
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-tristate2logic Yes
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

53
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD COLSPAN='4'><B>SCANCODE2 Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>scancode2.ise</TD>
<TD BGCOLOR='#FFFF99'><B>Current State:</B></TD>
<TD>Synthesized</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>fpga</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>10 Errors</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc2s200-5fg256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT>No Warnings</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 8.2i</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
<TD>Wed Dec 27 11:33:33 2006</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>SCANCODE2 Partition Summary</B></TD></TR>
<TR><TD COLSPAN='4'>No partition information was found.</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Dec 27 11:33:31 2006</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>10 Errors</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD>Xplorer Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
</TABLE>
</BODY></HTML>

0
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MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167237210
MO scancode_convert NULL ../../v/scancode2.v vlg3C/scancode__convert.bin 1167237210
MO fpga NULL ../../v/fpga3.v vlg22/fpga.bin 1167237210
MO test NULL ../../v/scancode2.v vlg34/test.bin 1167237210

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/mwave/work/nt/xess/xilinx/vga/fpga.ngc 1167708110
OK

11
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net vga/crt/_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
</messages>

45
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>
<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFG symbol &quot;gray_cnt_FFd1_BUFG&quot; (output signal=gray_cnt_FFd1)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin D of gray_cnt_FFd2</arg>
</msg>
<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFG symbol &quot;vga/crtclk_BUFG&quot; (output signal=vga/crtclk)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin D of vga/crtclk</arg>
</msg>
<msg type="warning" file="Pack" num="249" delta="unknown" >The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing.
<arg fmt="%s" index="1">vga/crt/Madd_ram_addr_Madd_cy&lt;7&gt;</arg>
<arg fmt="%s" index="2">vga/crt/Madd_ram_addr_Madd_cy&lt;8&gt;</arg>
</msg>
<msg type="warning" file="Pack" num="249" delta="unknown" >The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing.
<arg fmt="%s" index="1">vga/Madd_ram_addr_video_Madd_cy&lt;7&gt;</arg>
<arg fmt="%s" index="2">vga/Madd_ram_addr_video_Madd_cy&lt;8&gt;</arg>
</msg>
<msg type="warning" file="Pack" num="249" delta="unknown" >The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing.
<arg fmt="%s" index="1">vga/vgacore/Mcount_hcnt_cy&lt;0&gt;</arg>
<arg fmt="%s" index="2">vga/vgacore/Mcount_hcnt_cy&lt;1&gt;</arg>
</msg>
<msg type="warning" file="Pack" num="249" delta="unknown" >The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing.
<arg fmt="%s" index="1">vga/vgacore/Mcount_vcnt_cy&lt;0&gt;</arg>
<arg fmt="%s" index="2">vga/vgacore/Mcount_vcnt_cy&lt;1&gt;</arg>
</msg>
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net vga/crt/_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
</messages>

11
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="NetListWriters" num="633" delta="unknown" >The generated Verilog netlist contains Xilinx <arg fmt="%s" index="1">SIMPRIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">SIMPRIM</arg> simulation library for correct compilation and simulation.
</msg>
</messages>

29
xilinx/vga/_xmsgs/ngdbuild.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="NgdBuild" num="526" delta="unknown" >On the <arg fmt="%s" index="1">RAMB4_S1_S1</arg> symbol &quot;<arg fmt="%s" index="2">vga/inst_Mram_mem8</arg>&quot;, the following properties are undefined: <arg fmt="%s" index="3">INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F</arg>. A default value of all zeroes will be used.
</msg>
<msg type="info" file="NgdBuild" num="526" delta="unknown" >On the <arg fmt="%s" index="1">RAMB4_S1_S1</arg> symbol &quot;<arg fmt="%s" index="2">vga/inst_Mram_mem11</arg>&quot;, the following properties are undefined: <arg fmt="%s" index="3">INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F</arg>. A default value of all zeroes will be used.
</msg>
<msg type="info" file="NgdBuild" num="526" delta="unknown" >On the <arg fmt="%s" index="1">RAMB4_S1_S1</arg> symbol &quot;<arg fmt="%s" index="2">vga/inst_Mram_mem21</arg>&quot;, the following properties are undefined: <arg fmt="%s" index="3">INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F</arg>. A default value of all zeroes will be used.
</msg>
<msg type="info" file="NgdBuild" num="526" delta="unknown" >On the <arg fmt="%s" index="1">RAMB4_S1_S1</arg> symbol &quot;<arg fmt="%s" index="2">vga/inst_Mram_mem31</arg>&quot;, the following properties are undefined: <arg fmt="%s" index="3">INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F</arg>. A default value of all zeroes will be used.
</msg>
<msg type="info" file="NgdBuild" num="526" delta="unknown" >On the <arg fmt="%s" index="1">RAMB4_S1_S1</arg> symbol &quot;<arg fmt="%s" index="2">vga/inst_Mram_mem41</arg>&quot;, the following properties are undefined: <arg fmt="%s" index="3">INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F</arg>. A default value of all zeroes will be used.
</msg>
<msg type="info" file="NgdBuild" num="526" delta="unknown" >On the <arg fmt="%s" index="1">RAMB4_S1_S1</arg> symbol &quot;<arg fmt="%s" index="2">vga/inst_Mram_mem51</arg>&quot;, the following properties are undefined: <arg fmt="%s" index="3">INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F</arg>. A default value of all zeroes will be used.
</msg>
<msg type="info" file="NgdBuild" num="526" delta="unknown" >On the <arg fmt="%s" index="1">RAMB4_S1_S1</arg> symbol &quot;<arg fmt="%s" index="2">vga/inst_Mram_mem61</arg>&quot;, the following properties are undefined: <arg fmt="%s" index="3">INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F</arg>. A default value of all zeroes will be used.
</msg>
</messages>

13
xilinx/vga/_xmsgs/par.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="unknown" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;. For a balance between the fastest runtime and best performance, set the effort level to &quot;med&quot;.
</msg>
<msg type="info" file="Timing" num="2761" delta="unknown" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
</messages>

12
xilinx/vga/_xmsgs/trce.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="unknown" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="unknown" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
</messages>

89
xilinx/vga/_xmsgs/xst.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">keyrel_r</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="653" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">keyrel_x</arg>&gt; is used but never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">printable</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">clr_offset</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">ram_wclk</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2371" delta="unknown" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rom_addr_char&lt;7&gt;</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">resetVGA</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">done</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">kb_bsy</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">hloc&lt;2:0&gt;</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">vloc&lt;9&gt;</arg>&gt; is assigned but never used.
</msg>
<msg type="info" file="Xst" num="1767" delta="unknown" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">rom_addr_char_7</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">vga</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2261" delta="unknown" >The FF/Latch &lt;<arg fmt="%s" index="1">pixelData_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">vga</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">8 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;pixelData_1&gt; &lt;pixelData_2&gt; &lt;pixelData_3&gt; &lt;pixelData_4&gt; &lt;pixelData_5&gt; &lt;pixelData_6&gt; &lt;pixelData_7&gt; &lt;pixelData_8&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">enable</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">vgacore</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">done</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">crt</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1988" delta="unknown" >Unit &lt;<arg fmt="%s" index="1">vgacore</arg>&gt;: instances &lt;<arg fmt="%s" index="2">Mcompar__cmp_lt0000</arg>&gt;, &lt;<arg fmt="%s" index="3">Mcompar__cmp_ge0001</arg>&gt; of unit &lt;<arg fmt="%s" index="4">LPM_COMPARE_1</arg>&gt; and unit &lt;<arg fmt="%s" index="5">LPM_COMPARE_6</arg>&gt; are dual, second instance is removed
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">inst_Mram_mem71</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">vga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">vga/crt_data_7</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">fpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">vga/crt/ram_data_7</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">fpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">vga/crt/done</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">fpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">vga/vgacore/enable</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">fpga</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">vga/scancode_convert/ascii_7</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">fpga</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">vga/ps2/ps2_clk_r_1</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>
<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">vga/ps2/sc_r_7</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>
<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

104
xilinx/vga/fpga.bgn Normal file
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Release 8.2i - Bitgen I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file 'v200.nph' in environment
/opt/Xilinx.
"fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5
Opened constraints file fpga.pcf.
Mon Jan 1 22:22:58 2007
bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No fpga.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 4** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
| M1Pin | Pullup** |
+----------------------+----------------------+
| M2Pin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GSR_cycle | 6** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| Gclkdel0 | 11111** |
+----------------------+----------------------+
| Gclkdel1 | 11111** |
+----------------------+----------------------+
| Gclkdel2 | 11111** |
+----------------------+----------------------+
| Gclkdel3 | 11111** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
DRC detected 0 errors and 1 warnings.
Creating bit map...
Saving bit stream in "fpga.bit".
Bitstream generation is complete.

BIN
xilinx/vga/fpga.bit Normal file
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Binary file not shown.

66
xilinx/vga/fpga.bld Normal file
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Release 8.2i ngdbuild I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -ise /mwave/work/nt/xess/xilinx/vga/vga.ise -intstyle ise
-dd _ngo -nt timestamp -uc /mwave/work/nt/xess/v/fpga.ucf -p xc2s200-fg256-5
fpga.ngc fpga.ngd
Reading NGO file '/mwave/work/nt/xess/xilinx/vga/fpga.ngc' ...
Applying constraints in "/mwave/work/nt/xess/v/fpga.ucf" to the design...
Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...
INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem8", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem11", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem21", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem31", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem41", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem51", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem61", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 242404 kilobytes
Writing NGD file "fpga.ngd" ...
Writing NGDBUILD log file "fpga.bld"...

516
xilinx/vga/fpga.cmd_log Normal file
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xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
netgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim fpga.ngc fpga_synthesis.v
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
netgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -s 5 -pcf fpga.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim fpga.ncd fpga_timesim.v
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd
xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr
ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd
map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf
par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd

4
xilinx/vga/fpga.drc Normal file
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WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
DRC detected 0 errors and 1 warnings.

1
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work

3
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3
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3
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286
xilinx/vga/fpga.pad Normal file
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Release 8.2i - par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Mon Jan 1 22:22:43 2007
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: fpga_map.ncd
OUTPUT FILE: fpga.pad
PART TYPE: xc2s200
SPEED GRADE: -5
PACKAGE: fg256
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|DCI Value|IO Register|Signal Integrity|
A1|||GND|||||||||||||
A2||IOB|IO|UNUSED||7||||||||||
A3||IOB|IO_VREF_0|UNUSED||0||||||||||
A4||IOB|IO|UNUSED||0||||||||||
A5||IOB|IO|UNUSED||0||||||||||
A6||IOB|IO|UNUSED||0||||||||||
A7||IOB|IO|UNUSED||0||||||||||
A8||IOB|IO|UNUSED||1||||||||||
A9||IOB|IO|UNUSED||1||||||||||
A10||IOB|IO|UNUSED||1||||||||||
A11||IOB|IO|UNUSED||1||||||||||
A12||IOB|IO|UNUSED||1||||||||||
A13||IOB|IO|UNUSED||1||||||||||
A14||IOB|IO_VREF_1|UNUSED||1||||||||||
A15|||TDI|||||||||||||
A16|||GND|||||||||||||
B1||IOB|IO_VREF_7|UNUSED||7||||||||||
B2|||GND|||||||||||||
B3||IOB|IO|UNUSED||0||||||||||
B4||IOB|IO_VREF_0|UNUSED||0||||||||||
B5||IOB|IO|UNUSED||0||||||||||
B6||IOB|IO|UNUSED||0||||||||||
B7||IOB|IO_VREF_0|UNUSED||0||||||||||
B8||GCLKIOB|GCK3|UNUSED||0||||||||||
B9||IOB|IO_VREF_1|UNUSED||1||||||||||
B10||IOB|IO|UNUSED||1||||||||||
B11||IOB|IO|UNUSED||1||||||||||
B12||IOB|IO|UNUSED||1||||||||||
B13||IOB|IO_CS|UNUSED||1||||||||||
B14|||TDO|||||||||||||
B15|||GND|||||||||||||
B16||IOB|IO|UNUSED||2||||||||||
C1||IOB|IO_VREF_7|UNUSED||7||||||||||
C2||IOB|IO|UNUSED||7||||||||||
C3|||VCCINT||||||||2.5|||||
C4|||TCK|||||||||||||
C5||IOB|IO|UNUSED||0||||||||||
C6||IOB|IO_VREF_0|UNUSED||0||||||||||
C7||IOB|IO|UNUSED||0||||||||||
C8||IOB|IO|UNUSED||0||||||||||
C9||GCLKIOB|GCK2|UNUSED||1||||||||||
C10||IOB|IO|UNUSED||1||||||||||
C11||IOB|IO_VREF_1|UNUSED||1||||||||||
C12||IOB|IO|UNUSED||1||||||||||
C13||IOB|IO_WRITE|UNUSED||1||||||||||
C14|||VCCINT||||||||2.5|||||
C15||IOB|IO_DOUT_BUSY|UNUSED||2||||||||||
C16||IOB|IO|UNUSED||2||||||||||
D1||IOB|IO_VREF_7|UNUSED||7||||||||||
D2||IOB|IO|UNUSED||7||||||||||
D3|||TMS|||||||||||||
D4|||VCCINT||||||||2.5|||||
D5||IOB|IO|UNUSED||0||||||||||
D6||IOB|IO|UNUSED||0||||||||||
D7||IOB|IO|UNUSED||0||||||||||
D8||IOB|IO|UNUSED||0||||||||||
D9||IOB|IO|UNUSED||1||||||||||
D10||IOB|IO|UNUSED||1||||||||||
D11||IOB|IO|UNUSED||1||||||||||
D12||IOB|IO|UNUSED||1||||||||||
D13|||VCCINT||||||||2.5|||||
D14|fpga_din_d0|IOB|IO_DIN_D0|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
D15|||CCLK|||||||||||||
D16||IOB|IO|UNUSED||2||||||||||
E1|ps2_data|IOB|IO|INPUT|LVTTL|7||||IFD||LOCATED||YES|NONE|
E2||IOB|IO|UNUSED||7||||||||||
E3|reset_n|IOB|IO|INPUT|LVTTL|7||||NONE||LOCATED||NO|NONE|
E4||IOB|IO|UNUSED||7||||||||||
E5|||VCCINT||||||||2.5|||||
E6||IOB|IO|UNUSED||0||||||||||
E7||IOB|IO|UNUSED||0||||||||||
E8|||VCCO_0|||0|||||any******|||||
E9|||VCCO_1|||1|||||any******|||||
E10||IOB|IO|UNUSED||1||||||||||
E11||IOB|IO_VREF_1|UNUSED||1||||||||||
E12|||VCCINT||||||||2.5|||||
E13||IOB|IO_VREF_2|UNUSED||2||||||||||
E14||IOB|IO|UNUSED||2||||||||||
E15||IOB|IO|UNUSED||2||||||||||
E16|fpga_d1|IOB|IO_D1|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
F1||IOB|IO|UNUSED||7||||||||||
F2||IOB|IO|UNUSED||7||||||||||
F3||IOB|IO|UNUSED||7||||||||||
F4|ps2_clk|IOB|IO|INPUT|LVTTL|7||||IFD||LOCATED||YES|NONE|
F5||IOB|IO|UNUSED||7||||||||||
F6|||GND|||||||||||||
F7|||GND|||||||||||||
F8|||VCCO_0|||0|||||any******|||||
F9|||VCCO_1|||1|||||any******|||||
F10|||GND|||||||||||||
F11|||GND|||||||||||||
F12||IOB|IO|UNUSED||2||||||||||
F13||IOB|IO_VREF_2|UNUSED||2||||||||||
F14||IOB|IO_VREF_2|UNUSED||2||||||||||
F15|fpga_d2|IOB|IO_D2|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
F16||IOB|IO|UNUSED||2||||||||||
G1||PCIIOB|IO_IRDY|UNUSED||7||||||||||
G2||IOB|IO|UNUSED||7||||||||||
G3||IOB|IO|UNUSED||7||||||||||
G4||IOB|IO|UNUSED||7||||||||||
G5||IOB|IO|UNUSED||7||||||||||
G6|||GND|||||||||||||
G7|||GND|||||||||||||
G8|||GND|||||||||||||
G9|||GND|||||||||||||
G10|||GND|||||||||||||
G11|||GND|||||||||||||
G12||IOB|IO|UNUSED||2||||||||||
G13||IOB|IO|UNUSED||2||||||||||
G14||IOB|IO|UNUSED||2||||||||||
G15||IOB|IO|UNUSED||2||||||||||
G16|fpga_d3|IOB|IO_D3|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
H1||IOB|IO|UNUSED||6||||||||||
H2|vga_green0|IOB|IO|OUTPUT|LVTTL|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
H3||IOB|IO_VREF_7|UNUSED||7||||||||||
H4|vga_blue0|IOB|IO|OUTPUT|LVTTL|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
H5|||VCCO_7|||7|||||3.30|||||
H6|||VCCO_7|||7|||||3.30|||||
H7|||GND|||||||||||||
H8|||GND|||||||||||||
H9|||GND|||||||||||||
H10|||GND|||||||||||||
H11|||VCCO_2|||2|||||3.30|||||
H12|||VCCO_2|||2|||||3.30|||||
H13||IOB|IO_VREF_2|UNUSED||2||||||||||
H14||IOB|IO|UNUSED||2||||||||||
H15||IOB|IO|UNUSED||2||||||||||
H16||PCIIOB|IO_IRDY|UNUSED||2||||||||||
J1|vga_red0|IOB|IO|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
J2||PCIIOB|IO_TRDY|UNUSED||6||||||||||
J3||IOB|IO_VREF_6|UNUSED||6||||||||||
J4||IOB|IO|UNUSED||6||||||||||
J5|||VCCO_6|||6|||||3.30|||||
J6|||VCCO_6|||6|||||3.30|||||
J7|||GND|||||||||||||
J8|||GND|||||||||||||
J9|||GND|||||||||||||
J10|||GND|||||||||||||
J11|||VCCO_3|||3|||||3.30|||||
J12|||VCCO_3|||3|||||3.30|||||
J13||IOB|IO|UNUSED||2||||||||||
J14||IOB|IO|UNUSED||3||||||||||
J15||PCIIOB|IO_TRDY|UNUSED||3||||||||||
J16|fpga_d4|IOB|IO_D4|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
K1|vga_vsync_n|IOB|IO|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
K2||IOB|IO|UNUSED||6||||||||||
K3|vga_blue1|IOB|IO|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
K4|vga_hsync_n|IOB|IO|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
K5|vga_green1|IOB|IO|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
K6|||GND|||||||||||||
K7|||GND|||||||||||||
K8|||GND|||||||||||||
K9|||GND|||||||||||||
K10|||GND|||||||||||||
K11|||GND|||||||||||||
K12||IOB|IO|UNUSED||3||||||||||
K13||IOB|IO|UNUSED||3||||||||||
K14||IOB|IO|UNUSED||3||||||||||
K15||IOB|IO|UNUSED||3||||||||||
K16||IOB|IO_VREF_3|UNUSED||3||||||||||
L1||IOB|IO|UNUSED||6||||||||||
L2||IOB|IO|UNUSED||6||||||||||
L3||IOB|IO|UNUSED||6||||||||||
L4||IOB|IO|UNUSED||6||||||||||
L5|vga_blue2|IOB|IO|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
L6|||GND|||||||||||||
L7|||GND|||||||||||||
L8|||VCCO_5|||5|||||3.30|||||
L9|||VCCO_4|||4|||||any******|||||
L10|||GND|||||||||||||
L11|||GND|||||||||||||
L12||IOB|IO|UNUSED||3||||||||||
L13||IOB|IO_VREF_3|UNUSED||3||||||||||
L14||IOB|IO_VREF_3|UNUSED||3||||||||||
L15||IOB|IO|UNUSED||3||||||||||
L16||IOB|IO|UNUSED||3||||||||||
M1|vga_red1|IOB|IO_VREF_6|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
M2||IOB|IO|UNUSED||6||||||||||
M3||IOB|IO|UNUSED||6||||||||||
M4||IOB|IO|UNUSED||6||||||||||
M5|||VCCINT||||||||2.5|||||
M6||IOB|IO|UNUSED||5||||||||||
M7||IOB|IO|UNUSED||5||||||||||
M8|||VCCO_5|||5|||||3.30|||||
M9|||VCCO_4|||4|||||any******|||||
M10||IOB|IO|UNUSED||4||||||||||
M11||IOB|IO|UNUSED||4||||||||||
M12|||VCCINT||||||||2.5|||||
M13||IOB|IO_VREF_3|UNUSED||3||||||||||
M14||IOB|IO|UNUSED||3||||||||||
M15||IOB|IO|UNUSED||3||||||||||
M16|fpga_d5|IOB|IO_D5|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
N1||IOB|IO_VREF_6|UNUSED||6||||||||||
N2||IOB|IO_VREF_6|UNUSED||6||||||||||
N3|||M0|||||||||||||
N4|||VCCINT||||||||2.5|||||
N5||IOB|IO|UNUSED||5||||||||||
N6||IOB|IO|UNUSED||5||||||||||
N7||IOB|IO|UNUSED||5||||||||||
N8||GCLKIOB|GCK0|UNUSED||4||||||||||
N9||IOB|IO|UNUSED||4||||||||||
N10||IOB|IO|UNUSED||4||||||||||
N11||IOB|IO|UNUSED||4||||||||||
N12||IOB|IO|UNUSED||4||||||||||
N13|||VCCINT||||||||2.5|||||
N14|fpga_d7|IOB|IO_D7|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
N15||IOB|IO_INIT|UNUSED||3||||||||||
N16|fpga_d6|IOB|IO_D6|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
P1||IOB|IO|UNUSED||6||||||||||
P2|||M1|||||||||||||
P3|||VCCINT||||||||2.5|||||
P4|||NC|||||||||||||
P5||IOB|IO|UNUSED||5||||||||||
P6||IOB|IO|UNUSED||5||||||||||
P7||IOB|IO|UNUSED||5||||||||||
P8||IOB|IO_VREF_5|UNUSED||5||||||||||
P9||IOB|IO_VREF_4|UNUSED||4||||||||||
P10||IOB|IO|UNUSED||4||||||||||
P11||IOB|IO|UNUSED||4||||||||||
P12||IOB|IO|UNUSED||4||||||||||
P13||IOB|IO|UNUSED||4||||||||||
P14|||VCCINT||||||||2.5|||||
P15|||PROGRAM|||||||||||||
P16||IOB|IO|UNUSED||3||||||||||
R1|vga_green2|IOB|IO|OUTPUT|LVTTL|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
R2|||GND|||||||||||||
R3|||M2|||||||||||||
R4|||NC|||||||||||||
R5||IOB|IO_VREF_5|UNUSED||5||||||||||
R6||IOB|IO|UNUSED||5||||||||||
R7||IOB|IO|UNUSED||5||||||||||
R8|clka|GCLKIOB|GCK1|INPUT|LVTTL|5||||NONE||LOCATED||NO|NONE|
R9||IOB|IO|UNUSED||4||||||||||
R10||IOB|IO|UNUSED||4||||||||||
R11||IOB|IO|UNUSED||4||||||||||
R12||IOB|IO|UNUSED||4||||||||||
R13||IOB|IO_VREF_4|UNUSED||4||||||||||
R14|||DONE|||||||||||||
R15|||GND|||||||||||||
R16||IOB|IO|UNUSED||3||||||||||
T1|||GND|||||||||||||
T2|vga_red2|IOB|IO_VREF_5|OUTPUT|LVTTL|5|12|SLOW|NONE**|||LOCATED||NO|NONE|
T3||IOB|IO|UNUSED||5||||||||||
T4||IOB|IO_VREF_5|UNUSED||5||||||||||
T5||IOB|IO|UNUSED||5||||||||||
T6||IOB|IO|UNUSED||5||||||||||
T7||IOB|IO|UNUSED||5||||||||||
T8||IOB|IO|UNUSED||5||||||||||
T9||IOB|IO|UNUSED||4||||||||||
T10||IOB|IO|UNUSED||4||||||||||
T11||IOB|IO_VREF_4|UNUSED||4||||||||||
T12||IOB|IO_VREF_4|UNUSED||4||||||||||
T13||IOB|IO|UNUSED||4||||||||||
T14||IOB|IO|UNUSED||4||||||||||
T15||IOB|IO|UNUSED||3||||||||||
T16|||GND|||||||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

211
xilinx/vga/fpga.par Normal file
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@@ -0,0 +1,211 @@
Release 8.2i par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
wide:: Mon Jan 01 22:22:21 2007
par -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
Constraints file: fpga.pcf.
Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
"fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.27 2006-05-03".
Device Utilization Summary:
Number of BLOCKRAMs 7 out of 14 50%
Number of GCLKs 3 out of 4 75%
Number of External GCLKIOBs 1 out of 4 25%
Number of LOCed GCLKIOBs 1 out of 1 100%
Number of External IOBs 22 out of 176 12%
Number of LOCed IOBs 22 out of 22 100%
Number of SLICEs 402 out of 2352 17%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:98a557) REAL time: 4 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs
Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 4 secs
Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 4 secs
Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs
Phase 6.8
..................................................
..............
......................................................
.......................................
..........................................
.................................
Phase 6.8 (Checksum:bfc6cd) REAL time: 9 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 9 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 14 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 14 secs
Writing design to file fpga.ncd
Total REAL time to Placer completion: 14 secs
Total CPU time to Placer completion: 14 secs
Starting Router
Phase 1: 3141 unrouted; REAL time: 16 secs
Phase 2: 3034 unrouted; REAL time: 16 secs
Phase 3: 910 unrouted; REAL time: 17 secs
Phase 4: 910 unrouted; (187799) REAL time: 17 secs
Phase 5: 909 unrouted; (0) REAL time: 18 secs
Phase 6: 0 unrouted; (0) REAL time: 20 secs
Phase 7: 0 unrouted; (0) REAL time: 20 secs
Phase 8: 0 unrouted; (0) REAL time: 20 secs
Total REAL time to Router completion: 20 secs
Total CPU time to Router completion: 18 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| gray_cnt_FFd1 | GCLKBUF3| No | 78 | 0.209 | 0.796 |
+---------------------+--------------+------+------+------------+-------------+
| vga/crtclk | GCLKBUF0| No | 30 | 0.098 | 0.768 |
+---------------------+--------------+------+------+------------+-------------+
| clka_BUFGP | GCLKBUF1| No | 1 | 0.000 | 0.747 |
+---------------------+--------------+------+------+------------+-------------+
| vga/crt/ram_wclk | Local| | 14 | 1.258 | 3.885 |
+---------------------+--------------+------+------+------------+-------------+
| vga/charload | Local| | 15 | 1.888 | 5.945 |
+---------------------+--------------+------+------+------------+-------------+
| vga/vgacore/hblank | Local| | 12 | 0.087 | 3.941 |
+---------------------+--------------+------+------+------------+-------------+
| vga/pclk<2> | Local| | 9 | 0.715 | 2.527 |
+---------------------+--------------+------+------+------------+-------------+
| vga/crt/_or0000 | Local| | 2 | 0.000 | 0.700 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
The Delay Summary Report
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 2.379
The MAXIMUM PIN DELAY IS: 7.048
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 6.411
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 8.00 d >= 8.00
--------- --------- --------- --------- --------- ---------
574 826 763 511 459 0
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic | Absolute |Number of
| | | Levels | Slack |errors
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net gra | N/A | 11.183ns | 5 | N/A | N/A
y_cnt_FFd1 | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net vga | N/A | 8.284ns | 4 | N/A | N/A
/crtclk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | N/A | 7.120ns | 1 | N/A | N/A
a_BUFGP | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net vga | N/A | 10.431ns | 0 | N/A | N/A
/crt/ram_wclk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net vga | N/A | 9.916ns | 4 | N/A | N/A
/vgacore/hblank | | | | |
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 22 secs
Total CPU time to PAR completion: 20 secs
Peak Memory Usage: 323 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file fpga.ncd
PAR done!

29
xilinx/vga/fpga.pcf Normal file
View File

@@ -0,0 +1,29 @@
//! **************************************************************************
// Written by: Map I.31 on Mon Jan 01 22:22:14 2007
//! **************************************************************************
SCHEMATIC START;
COMP "ps2_clk" LOCATE = SITE "F4" LEVEL 1;
COMP "fpga_d1" LOCATE = SITE "E16" LEVEL 1;
COMP "fpga_d2" LOCATE = SITE "F15" LEVEL 1;
COMP "fpga_d3" LOCATE = SITE "G16" LEVEL 1;
COMP "fpga_d4" LOCATE = SITE "J16" LEVEL 1;
COMP "fpga_d5" LOCATE = SITE "M16" LEVEL 1;
COMP "fpga_d6" LOCATE = SITE "N16" LEVEL 1;
COMP "fpga_d7" LOCATE = SITE "N14" LEVEL 1;
COMP "ps2_data" LOCATE = SITE "E1" LEVEL 1;
COMP "fpga_din_d0" LOCATE = SITE "D14" LEVEL 1;
COMP "vga_blue0" LOCATE = SITE "H4" LEVEL 1;
COMP "vga_blue1" LOCATE = SITE "K3" LEVEL 1;
COMP "vga_vsync_n" LOCATE = SITE "K1" LEVEL 1;
COMP "vga_blue2" LOCATE = SITE "L5" LEVEL 1;
COMP "vga_hsync_n" LOCATE = SITE "K4" LEVEL 1;
COMP "clka" LOCATE = SITE "R8" LEVEL 1;
COMP "vga_red0" LOCATE = SITE "J1" LEVEL 1;
COMP "vga_red1" LOCATE = SITE "M1" LEVEL 1;
COMP "vga_red2" LOCATE = SITE "T2" LEVEL 1;
COMP "reset_n" LOCATE = SITE "E3" LEVEL 1;
COMP "vga_green0" LOCATE = SITE "H2" LEVEL 1;
COMP "vga_green1" LOCATE = SITE "K5" LEVEL 1;
COMP "vga_green2" LOCATE = SITE "R1" LEVEL 1;
SCHEMATIC END;

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