19 lines
1.2 KiB
Plaintext
19 lines
1.2 KiB
Plaintext
WARNING:PhysDesignRules:372 - Gated clock. Clock net ram_rd is sourced by a
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combinatorial pin. This is not good design practice. Use the CE pin to
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control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:367 - The signal <slideswitch<4>_IBUF> is incomplete.
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The signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal <slideswitch<5>_IBUF> is incomplete.
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The signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal <slideswitch<6>_IBUF> is incomplete.
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The signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal <slideswitch<7>_IBUF> is incomplete.
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The signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal <button<0>_IBUF> is incomplete. The
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signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal <button<1>_IBUF> is incomplete. The
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signal does not drive any load pins in the design.
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WARNING:PhysDesignRules:367 - The signal <button<2>_IBUF> is incomplete. The
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signal does not drive any load pins in the design.
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DRC detected 0 errors and 8 warnings.
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