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brad
2010-04-24 10:35:11 +00:00
parent e379c07159
commit 9bbe1a147e
54 changed files with 2381 additions and 1889 deletions
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4
xilinx/pdp8/_ngo/netlist.lst
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@@ -1,2 +1,2 @@
/home/brad/pdp8/xilinx/pdp8/top.ngc 1271420145
OK
C:\brad\pdp8\xilinx\pdp8\top.ngc 1272077251
OK

40
xilinx/pdp8/_xmsgs/bitgen.xmsgs
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@@ -1,8 +1,32 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net ram_rd is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;4&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;5&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;6&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;7&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;button&lt;0&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;button&lt;1&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;button&lt;2&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
</messages>

110
xilinx/pdp8/_xmsgs/map.xmsgs
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@@ -1,49 +1,61 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">slideswitch&lt;7&gt;</arg> has no load.
</msg>
<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">26</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">slideswitch&lt;6&gt;,
slideswitch&lt;5&gt;,
slideswitch&lt;4&gt;,
button&lt;2&gt;,
button&lt;1&gt;</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>
<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFG symbol &quot;clk_BUFG&quot; (output signal=clk),
BUFG symbol &quot;io/tt/baud_rate_generator/rx_baud_clk_BUFG&quot; (output signal=io/tt/baud_rate_generator/rx_baud_clk),
BUFGP symbol &quot;sysclk_BUFGP&quot; (output signal=sysclk_BUFGP)</arg>
</msg>
<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>
<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_clk/clk_BUFG&quot; (output signal=clk)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin D of clk</arg>
</msg>
<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_io/tt/baud_rate_generator/rx_baud_clk/io/tt/baud_rate_generator/rx_baud_clk_BUFG&quot; (output signal=io/tt/baud_rate_generator/rx_baud_clk)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin D of io/tt/baud_rate_generator/rx_baud_clk</arg>
</msg>
<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0009&lt;4&gt;129</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0009&lt;7&gt;73_SW11_f5</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing.
</msg>
<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0009&lt;4&gt;129</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0009&lt;8&gt;73_SW11_f5</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing.
</msg>
<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0009&lt;4&gt;129</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0009&lt;6&gt;73_SW1</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">slideswitch&lt;7&gt;_IBUF</arg> has no load.
</msg>
<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">6</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">slideswitch&lt;6&gt;_IBUF,
slideswitch&lt;5&gt;_IBUF,
slideswitch&lt;4&gt;_IBUF,
button&lt;2&gt;_IBUF,
button&lt;1&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>
<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFG symbol &quot;clk_BUFG&quot; (output signal=clk),
BUFG symbol &quot;io/tt/baud_rate_generator/rx_baud_clk_BUFG&quot; (output signal=io/tt/baud_rate_generator/rx_baud_clk),
BUFGP symbol &quot;sysclk_BUFGP&quot; (output signal=sysclk_BUFGP)</arg>
</msg>
<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_clk/clk_BUFG&quot; (output signal=clk)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin D of clk</arg>
</msg>
<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFGMUX symbol &quot;physical_group_io/tt/baud_rate_generator/rx_baud_clk/io/tt/baud_rate_generator/rx_baud_clk_BUFG&quot; (output signal=io/tt/baud_rate_generator/rx_baud_clk)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
<arg fmt="%s" index="2">Pin D of io/tt/baud_rate_generator/rx_baud_clk</arg>
</msg>
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net ram_rd is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;4&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;5&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;6&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;slideswitch&lt;7&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;button&lt;0&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;button&lt;1&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367">The signal &lt;button&lt;2&gt;_IBUF&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
</messages>

16
xilinx/pdp8/_xmsgs/ngdbuild.xmsgs
View File

@@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

87
xilinx/pdp8/_xmsgs/par.xmsgs
View File

@@ -1,28 +1,59 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="unknown" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;. For a balance between the fastest runtime and best performance, set the effort level to &quot;med&quot;.
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/tt/baud_rate_generator/tx_baud_clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/kw/kw_src_clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/tt/baud_rate_generator/rx_baud_clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">reset_sw/slowclk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">clk</arg> may have excessive skew because
</msg>
<msg type="info" file="Timing" num="2761" delta="unknown" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="unknown" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;. For a balance between the fastest runtime and best performance, set the effort level to &quot;med&quot;.
</msg>
<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">slideswitch&lt;4&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">slideswitch&lt;5&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">slideswitch&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">slideswitch&lt;7&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">button&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">button&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">button&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">ram_rd</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/kw/kw_src_clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/tt/baud_rate_generator/tx_baud_clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">show_pc/aclk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">reset_sw/slowclk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/tt/baud_rate_generator/rx_baud_clk</arg> may have excessive skew because
</msg>
<msg type="info" file="Timing" num="2761" delta="unknown" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
<msg type="warning" file="Par" num="284" delta="unknown" >There are <arg fmt="%d" index="1">7</arg> sourceless or loadless signals in this design. This design will not pass the DRC check run by Bitgen.
</msg>
</messages>

24
xilinx/pdp8/_xmsgs/trce.xmsgs
View File

@@ -1,12 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="unknown" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="unknown" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="unknown" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="unknown" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
</messages>

307
xilinx/pdp8/_xmsgs/xst.xmsgs
View File

@@ -1,161 +1,146 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">is_write</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">PEF</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">NXD</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">WLS</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">fetch</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">execute</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">deferred</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">clk</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">reset</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">mb&lt;11:3&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">clk</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">tx_over_run</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rx_frame_err</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rx_over_run</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">reset</arg>&gt; is never used.
</msg>
<msg type="info" file="Xst" num="1442" delta="unknown" >HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">mb&lt;11:3&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">tto_empty</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="1305" delta="unknown" >Output &lt;<arg fmt="%s" index="1">ide_error</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ata_out&lt;15:12&gt;</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">err</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">mb&lt;11:3&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ide_error</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">PEF</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">buffer_rd</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">active</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">slideswitch&lt;7:4&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">sevenseg</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">sevenseg_an</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">button&lt;2:0&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="1306" delta="unknown" >Output &lt;<arg fmt="%s" index="1">led</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="653" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">switches</arg>&gt; is used but never assigned. Tied to value <arg fmt="%s" index="2">000000000000</arg>.
</msg>
<msg type="info" file="Xst" num="1767" delta="unknown" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
</msg>
<msg type="info" file="Xst" num="1651" delta="unknown" >Address input of ROM &lt;<arg fmt="%s" index="1">Mrom__AUX_15</arg>&gt; is tied to register &lt;<arg fmt="%s" index="2">ir</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2502" delta="unknown" >HDL ADVISOR - Asynchronous or synchronous initialization of this register prevents it from being combined with the ROM for implementation as read-only block RAM.
</msg>
<msg type="info" file="Xst" num="1647" delta="unknown" >Data output of ROM &lt;<arg fmt="%s" index="1">Mrom__mux0005</arg>&gt; is tied to register &lt;<arg fmt="%s" index="2">interrupt_inhibit_clear</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2506" delta="unknown" >In order to maximize performance and save block RAM resources, this small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
</msg>
<msg type="info" file="Xst" num="1647" delta="unknown" >Data output of ROM &lt;<arg fmt="%s" index="1">Mrom__mux0003</arg>&gt; is tied to register &lt;<arg fmt="%s" index="2">tx_int</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2506" delta="unknown" >In order to maximize performance and save block RAM resources, this small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
</msg>
<msg type="warning" file="Xst" num="1426" delta="unknown" >The value init of the FF/Latch <arg fmt="%s" index="1">onetime</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">debounce</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_12</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_13</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_14</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_15</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2146" delta="unknown" >In block &lt;<arg fmt="%s" index="1">ide_disk</arg>&gt;, <arg fmt="%s" index="2">Counter</arg> &lt;<arg fmt="%s" index="3">offset</arg>&gt; </msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_12</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_13</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_14</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_15</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">io/tt/tt_uart/rx_d2</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>
<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">is_write</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">PEF</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">NXD</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="info" file="Xst" num="1304" delta="unknown" >Contents of register &lt;<arg fmt="%s" index="1">WLS</arg>&gt; in unit &lt;<arg fmt="%s" index="2">pdp8_rf</arg>&gt; never changes during circuit operation. The register is replaced by logic.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">fetch</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">execute</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">deferred</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">mb&lt;11:3&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">clk</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">tx_over_run</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rx_frame_err</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rx_over_run</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">reset</arg>&gt; is never used.
</msg>
<msg type="info" file="Xst" num="1442" delta="unknown" >HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
</msg>
<msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">12</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">reset</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">mb&lt;11:3&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">tto_empty</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="1305" delta="unknown" >Output &lt;<arg fmt="%s" index="1">ide_error</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ata_out&lt;15:12&gt;</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">err</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">mb&lt;11:3&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ide_error</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">PEF</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">buffer_rd</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">active</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">slideswitch&lt;7:4&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">button&lt;2:0&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="653" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">switches</arg>&gt; is used but never assigned. Tied to value <arg fmt="%s" index="2">000000000000</arg>.
</msg>
<msg type="info" file="Xst" num="1767" delta="unknown" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
</msg>
<msg type="info" file="Xst" num="1651" delta="unknown" >Address input of ROM &lt;<arg fmt="%s" index="1">Mrom__AUX_16</arg>&gt; is tied to register &lt;<arg fmt="%s" index="2">ir</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2502" delta="unknown" >HDL ADVISOR - Asynchronous or synchronous initialization of this register prevents it from being combined with the ROM for implementation as read-only block RAM.
</msg>
<msg type="info" file="Xst" num="1647" delta="unknown" >Data output of ROM &lt;<arg fmt="%s" index="1">Mrom__mux0005</arg>&gt; is tied to register &lt;<arg fmt="%s" index="2">interrupt_inhibit_clear</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2506" delta="unknown" >In order to maximize performance and save block RAM resources, this small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
</msg>
<msg type="warning" file="Xst" num="1426" delta="unknown" >The value init of the FF/Latch <arg fmt="%s" index="1">onetime</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">debounce</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_12</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_13</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_14</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">ata_out_15</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ide1</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2146" delta="unknown" >In block &lt;<arg fmt="%s" index="1">ide_disk</arg>&gt;, <arg fmt="%s" index="2">Counter</arg> &lt;<arg fmt="%s" index="3">offset</arg>&gt; </msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_12</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_13</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_14</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">io/tf/disk/ide1/ata_out_15</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">top</arg>&gt;.
</msg>
<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">io/tt/tt_uart/rx_d2</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>
<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>

BIN
xilinx/pdp8/pdp8.ise
View File

Binary file not shown.

BIN
xilinx/pdp8/pdp8.ise_ISE_Backup
View File

Binary file not shown.

24
xilinx/pdp8/pdp8.ntrc_log
View File

@@ -6,3 +6,27 @@ Map NTRC: "/top" : OUT_OF_DATE
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Map NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Map NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Map NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Map NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Map NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Map NTRC: "/top" : OUT_OF_DATE

205
xilinx/pdp8/top.bgn
View File

@@ -1,103 +1,120 @@
Release 8.2i - Bitgen I.31
Release 8.2.03i - Bitgen I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s1000.nph' in environment
/opt/Xilinx.
Loading device for application Rf_Device from file '3s1000.nph' in environment
C:\Xilinx.
"top" is an NCD, version 3.1, device xc3s1000, package ft256, speed -5
Opened constraints file top.pcf.
Fri Apr 16 08:19:36 2010
bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No top.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 6** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DCMShutdown | Disable** |
+----------------------+----------------------+
| DCIUpdateMode | AsRequired** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| HswapenPin | Pullup* |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
| M1Pin | Pullup** |
+----------------------+----------------------+
| M2Pin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| Match_cycle | Auto** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
Fri Apr 23 22:48:38 2010
C:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No top.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 6** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DCMShutdown | Disable** |
+----------------------+----------------------+
| DCIUpdateMode | AsRequired** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| HswapenPin | Pullup* |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
| M1Pin | Pullup** |
+----------------------+----------------------+
| M2Pin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| Match_cycle | Auto** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
Running DRC.
DRC detected 0 errors and 0 warnings.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ram_rd is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <slideswitch<4>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<5>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<6>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<7>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<0>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
DRC detected 0 errors and 8 warnings.
Creating bit map...
Saving bit stream in "top.bit".
Bitstream generation is complete.

BIN
xilinx/pdp8/top.bit
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Binary file not shown.

13
xilinx/pdp8/top.bld
View File

@@ -1,10 +1,13 @@
Release 8.2i ngdbuild I.31
Release 8.2.03i ngdbuild I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -ise /home/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise
-dd _ngo -nt timestamp -i -p xc3s1000-ft256-5 top.ngc top.ngd
Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise
C:/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise -dd _ngo -nt timestamp -uc
C:/brad/pdp8/synth/s3board.ucf -p xc3s1000-ft256-5 top.ngc top.ngd
Reading NGO file '/home/brad/pdp8/xilinx/pdp8/top.ngc' ...
Reading NGO file 'C:/brad/pdp8/xilinx/pdp8/top.ngc' ...
Applying constraints in "C:/brad/pdp8/synth/s3board.ucf" to the design...
Checking timing specifications ...
Checking Partitions ...
@@ -21,7 +24,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 247480 kilobytes
Total memory usage is 73504 kilobytes
Writing NGD file "top.ngd" ...

35
xilinx/pdp8/top.cmd_log
View File

@@ -9,3 +9,38 @@ map -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-
par -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
trce -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf
bitgen -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -f top.ut top.ncd
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
par -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
trce -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf
bitgen -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -f top.ut top.ncd
ngdbuild -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -uc "C:/brad/pdp8/synth/s3board.ucf" -p xc3s1000-ft256-5 "top.ngc" top.ngd
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -uc "C:/brad/pdp8/synth/s3board.ucf" -p xc3s1000-ft256-5 "top.ngc" top.ngd
ngdbuild -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -uc "C:/brad/pdp8/synth/s3board.ucf" -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
par -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
trce -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf C:/brad/pdp8/synth/s3board.ucf
bitgen -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -f top.ut top.ncd
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -uc "C:/brad/pdp8/synth/s3board.ucf" -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
par -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
trce -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf C:/brad/pdp8/synth/s3board.ucf
bitgen -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -f top.ut top.ncd
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -uc "C:/brad/pdp8/synth/s3board.ucf" -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
par -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
trce -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf C:/brad/pdp8/synth/s3board.ucf
bitgen -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -f top.ut top.ncd
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -uc "C:/brad/pdp8/synth/s3board.ucf" -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
par -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
trce -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf C:/brad/pdp8/synth/s3board.ucf
bitgen -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -f top.ut top.ncd

19
xilinx/pdp8/top.drc
View File

@@ -1 +1,18 @@
DRC detected 0 errors and 0 warnings.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ram_rd is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <slideswitch<4>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<5>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<6>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<7>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<0>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
DRC detected 0 errors and 8 warnings.

2
xilinx/pdp8/top.ncd
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2
xilinx/pdp8/top.ngc
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2
xilinx/pdp8/top.ngd
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2
xilinx/pdp8/top.ngr
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292
xilinx/pdp8/top.pad
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@@ -1,7 +1,7 @@
Release 8.2i - par I.31
Release 8.2.03i - par I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Fri Apr 16 08:17:40 2010
Fri Apr 23 22:48:26 2010
# NOTE: This file is designed to be imported into a spreadsheet program
@@ -21,120 +21,120 @@ Pinout by Pin Number:
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|DCI Value|IO Register|Signal Integrity|
A1|||GND|||||||||||||
A2|||TDI|||||||||||||
A3|slideswitch<1>|IOB|IO/VREF_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
A4||DIFFM|IO_L01P_0/VRN_0|UNUSED||0||||||||||
A5||IOB|IO|UNUSED||0||||||||||
A3|ide_data_bus<13>|IOB|IO/VREF_0|TRISTATE|LVTTL|0|12|SLOW|NONE**|||LOCATED||NO|NONE|
A4|ide_data_bus<14>|IOB|IO_L01P_0/VRN_0|TRISTATE|LVTTL|0|12|SLOW|NONE**|||LOCATED||NO|NONE|
A5|ide_data_bus<15>|IOB|IO|TRISTATE|LVTTL|0|12|SLOW|NONE**|||LOCATED||NO|NONE|
A6|||VCCAUX||||||||2.5|||||
A7||IOB|IO|UNUSED||0||||||||||
A8||DIFFM|IO_L32P_0/GCLK6|UNUSED||0||||||||||
A9||IOB|IO|UNUSED||1||||||||||
A10||DIFFS|IO_L31N_1/VREF_1|UNUSED||1||||||||||
A8|ide_diow|IOB|IO_L32P_0/GCLK6|OUTPUT|LVTTL|0|12|SLOW|NONE**|||LOCATED||NO|NONE|
A9|ide_cs<0>|IOB|IO|OUTPUT|LVTTL|1|12|SLOW|NONE**|||LOCATED||NO|NONE|
A10|ide_cs<1>|IOB|IO_L31N_1/VREF_1|OUTPUT|LVTTL|1|12|SLOW|NONE**|||LOCATED||NO|NONE|
A11|||VCCAUX||||||||2.5|||||
A12||IOB|IO|UNUSED||1||||||||||
A13||DIFFS|IO_L10N_1/VREF_1|UNUSED||1||||||||||
A14||DIFFS|IO_L01N_1/VRP_1|UNUSED||1||||||||||
A15|||TDO|||||||||||||
A16|||GND|||||||||||||
B1||DIFFM|IO_L01P_7/VRN_7|UNUSED||7||||||||||
B1|sram1_io<7>|IOB|IO_L01P_7/VRN_7|BIDIR|LVCMOS25|7|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
B2|||GND|||||||||||||
B3|||PROG_B|||||||||||||
B4||DIFFS|IO_L01N_0/VRP_0|UNUSED||0||||||||||
B5|ide_da<0>|IOB|IO_L25P_0|OUTPUT|LVCMOS25|0|12|SLOW|NONE**|||||NO|NONE|
B4|ide_data_bus<1>|IOB|IO_L01N_0/VRP_0|BIDIR|LVTTL|0|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
B5|ide_data_bus<0>|IOB|IO_L25P_0|BIDIR|LVTTL|0|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
B6||DIFFM|IO_L28P_0|UNUSED||0||||||||||
B7||DIFFM|IO_L30P_0|UNUSED||0||||||||||
B8||DIFFS|IO_L32N_0/GCLK7|UNUSED||0||||||||||
B9|||GND|||||||||||||
B10|sram1_io<15>|IOB|IO_L31P_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
B11|sram1_io<12>|IOB|IO_L29N_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
B12||DIFFS|IO_L27N_1|UNUSED||1||||||||||
B13||DIFFM|IO_L10P_1|UNUSED||1||||||||||
B14||DIFFM|IO_L01P_1/VRN_1|UNUSED||1||||||||||
B10|ide_dior|IOB|IO_L31P_1|OUTPUT|LVTTL|1|12|SLOW|NONE**|||LOCATED||NO|NONE|
B11||DIFFS|IO_L29N_1|UNUSED||1||||||||||
B12|ide_da<0>|IOB|IO_L27N_1|OUTPUT|LVTTL|1|12|SLOW|NONE**|||LOCATED||NO|NONE|
B13|ide_da<1>|IOB|IO_L10P_1|OUTPUT|LVTTL|1|12|SLOW|NONE**|||LOCATED||NO|NONE|
B14|ide_da<2>|IOB|IO_L01P_1/VRN_1|OUTPUT|LVTTL|1|12|SLOW|NONE**|||LOCATED||NO|NONE|
B15|||GND|||||||||||||
B16||DIFFS|IO_L01N_2/VRP_2|UNUSED||2||||||||||
C1||DIFFS|IO_L01N_7/VRP_7|UNUSED||7||||||||||
C2|sram2_io<9>|IOB|IO_L16N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
C3|sram2_lb_n|IOB|IO_L16P_7/VREF_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
C1|sram1_io<6>|IOB|IO_L01N_7/VRP_7|BIDIR|LVCMOS25|7|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
C2|sram1_io<5>|IOB|IO_L16N_7|BIDIR|LVCMOS25|7|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
C3|sram2_io<12>|IOB|IO_L16P_7/VREF_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
C4|||HSWAP_EN|||||||||||||
C5|slideswitch<3>|IOB|IO_L25N_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
C6||DIFFS|IO_L28N_0|UNUSED||0||||||||||
C7||DIFFS|IO_L30N_0|UNUSED||0||||||||||
C8||DIFFM|IO_L31P_0/VREF_0|UNUSED||0||||||||||
C9|sysclk|IOB|IO_L32N_1/GCLK5|INPUT|LVCMOS25|1||||NONE||||NO|NONE|
C5|ide_data_bus<8>|IOB|IO_L25N_0|BIDIR|LVTTL|0|12|SLOW|NONE**|IFD||LOCATED||YES|NONE|
C6|ide_data_bus<9>|IOB|IO_L28N_0|BIDIR|LVTTL|0|12|SLOW|NONE**|IFD||LOCATED||YES|NONE|
C7|ide_data_bus<10>|IOB|IO_L30N_0|BIDIR|LVTTL|0|12|SLOW|NONE**|IFD||LOCATED||YES|NONE|
C8|ide_data_bus<11>|IOB|IO_L31P_0/VREF_0|BIDIR|LVTTL|0|12|SLOW|NONE**|IFD||LOCATED||YES|NONE|
C9|ide_data_bus<12>|IOB|IO_L32N_1/GCLK5|TRISTATE|LVTTL|1|12|SLOW|NONE**|||LOCATED||NO|NONE|
C10||IOB|IO|UNUSED||1||||||||||
C11|sram1_io<13>|IOB|IO_L29P_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
C11||DIFFM|IO_L29P_1|UNUSED||1||||||||||
C12||DIFFM|IO_L27P_1|UNUSED||1||||||||||
C13|||TMS|||||||||||||
C14|||TCK|||||||||||||
C15||DIFFS|IO_L16N_2|UNUSED||2||||||||||
C16||DIFFM|IO_L01P_2/VRN_2|UNUSED||2||||||||||
D1|sram2_ub_n|IOB|IO_L17N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
D2|sram2_io<8>|IOB|IO_L17P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
D3|sram1_ub_n|IOB|IO_L19P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
D1|sram2_io<7>|IOB|IO_L17N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
D2|sram2_io<8>|IOB|IO_L17P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
D3|sram1_io<8>|IOB|IO_L19P_7|BIDIR|LVCMOS25|7|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
D4|||VCCINT||||||||1.2|||||
D5|slideswitch<0>|IOB|IO/VREF_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
D6|slideswitch<2>|IOB|IO_L27P_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
D7||DIFFM|IO_L29P_0|UNUSED||0||||||||||
D8||DIFFS|IO_L31N_0|UNUSED||0||||||||||
D9|sram_a<17>|IOB|IO_L32P_1/GCLK4|OUTPUT|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
D10||DIFFS|IO_L30N_1|UNUSED||1||||||||||
D5|ide_data_bus<7>|IOB|IO/VREF_0|BIDIR|LVTTL|0|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
D6|ide_data_bus<6>|IOB|IO_L27P_0|BIDIR|LVTTL|0|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
D7|ide_data_bus<4>|IOB|IO_L29P_0|BIDIR|LVTTL|0|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
D8|ide_data_bus<3>|IOB|IO_L31N_0|BIDIR|LVTTL|0|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
D9||DIFFM|IO_L32P_1/GCLK4|UNUSED||1||||||||||
D10|ide_data_bus<2>|IOB|IO_L30N_1|BIDIR|LVTTL|1|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
D11||DIFFS|IO_L28N_1|UNUSED||1||||||||||
D12||IOB|IO/VREF_1|UNUSED||1||||||||||
D13|||VCCINT||||||||1.2|||||
D14||DIFFM|IO_L16P_2|UNUSED||2||||||||||
D14|sevenseg_an<0>|IOB|IO_L16P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
D15||DIFFS|IO_L17N_2|UNUSED||2||||||||||
D16||DIFFM|IO_L17P_2/VREF_2|UNUSED||2||||||||||
E1|sram2_io<12>|IOB|IO_L20N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E2|sram2_io<10>|IOB|IO_L20P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E3|sram2_io<11>|IOB|IO_L19N_7/VREF_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E4|sram2_io<14>|IOB|IO_L21P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E1|sram2_io<6>|IOB|IO_L20N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
E2|sram2_io<9>|IOB|IO_L20P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
E3|sram_a<8>|IOB|IO_L19N_7/VREF_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
E4|sram_a<9>|IOB|IO_L21P_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
E5|||VCCINT||||||||1.2|||||
E6||DIFFS|IO_L27N_0|UNUSED||0||||||||||
E7||DIFFS|IO_L29N_0|UNUSED||0||||||||||
E8|||VCCO_0|||0|||||2.50|||||
E9|||VCCO_1|||1|||||2.50|||||
E10|sram1_io<14>|IOB|IO_L30P_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
E7|ide_data_bus<5>|IOB|IO_L29N_0|BIDIR|LVTTL|0|24|SLOW|NONE**|IFD||LOCATED||YES|NONE|
E8|||VCCO_0|||0|||||3.30|||||
E9|||VCCO_1|||1|||||3.30|||||
E10||DIFFM|IO_L30P_1|UNUSED||1||||||||||
E11||DIFFM|IO_L28P_1|UNUSED||1||||||||||
E12|||VCCINT||||||||1.2|||||
E13||DIFFS|IO_L19N_2|UNUSED||2||||||||||
E14||DIFFM|IO_L19P_2|UNUSED||2||||||||||
E13|sevenseg_an<3>|IOB|IO_L19N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
E14|sevenseg<7>|IOB|IO_L19P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
E15||DIFFS|IO_L20N_2|UNUSED||2||||||||||
E16||DIFFM|IO_L20P_2|UNUSED||2||||||||||
F1|||VCCAUX||||||||2.5|||||
F2|sram2_io<15>|IOB|IO_L22N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F3|sram_a<15>|IOB|IO_L22P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F4|sram2_io<13>|IOB|IO_L21N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F5||DIFFM|IO_L23P_7|UNUSED||7||||||||||
F2|sram1_io<10>|IOB|IO_L22N_7|BIDIR|LVCMOS25|7|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
F3|sram_a<6>|IOB|IO_L22P_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
F4|sram_a<7>|IOB|IO_L21N_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
F5|sram2_io<11>|IOB|IO_L23P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
F6|||GND|||||||||||||
F7|||VCCO_0|||0|||||2.50|||||
F8|||VCCO_0|||0|||||2.50|||||
F9|||VCCO_1|||1|||||2.50|||||
F10|||VCCO_1|||1|||||2.50|||||
F7|||VCCO_0|||0|||||3.30|||||
F8|||VCCO_0|||0|||||3.30|||||
F9|||VCCO_1|||1|||||3.30|||||
F10|||VCCO_1|||1|||||3.30|||||
F11|||GND|||||||||||||
F12||DIFFS|IO_L21N_2|UNUSED||2||||||||||
F13||DIFFM|IO_L21P_2|UNUSED||2||||||||||
F14||DIFFS|IO_L22N_2|UNUSED||2||||||||||
F12|slideswitch<0>|IOB|IO_L21N_2|INPUT|LVCMOS25|2||||NONE||LOCATED||NO|NONE|
F13|sevenseg<2>|IOB|IO_L21P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
F14|sevenseg_an<2>|IOB|IO_L22N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
F15||DIFFM|IO_L22P_2|UNUSED||2||||||||||
F16|||VCCAUX||||||||2.5|||||
G1|ide_data_bus<2>|IOB|IO_L40P_7|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
G2|ide_data_bus<7>|IOB|IO|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
G3|ide_diow|IOB|IO_L24N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G4|ide_dior|IOB|IO_L24P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G5|sram_a<16>|IOB|IO_L23N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G1|sram2_io<10>|IOB|IO_L40P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
G2|sram2_io<5>|IOB|IO|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||LOCATED||NO|NONE|
G3|sram_we_n|IOB|IO_L24N_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
G4|sram_a<5>|IOB|IO_L24P_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
G5|sram_a<10>|IOB|IO_L23N_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
G6|||VCCO_7|||7|||||2.50|||||
G7|||GND|||||||||||||
G8|||GND|||||||||||||
G9|||GND|||||||||||||
G10|||GND|||||||||||||
G11|||VCCO_2|||2|||||2.50|||||
G12||DIFFS|IO_L23N_2/VREF_2|UNUSED||2||||||||||
G13||DIFFM|IO_L23P_2|UNUSED||2||||||||||
G14||DIFFS|IO_L24N_2|UNUSED||2||||||||||
G15|rs232_txd|IOB|IO_L24P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
G12|slideswitch<1>|IOB|IO_L23N_2/VREF_2|INPUT|LVCMOS25|2||||NONE||LOCATED||NO|NONE|
G13|sevenseg<6>|IOB|IO_L23P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
G14|sevenseg_an<1>|IOB|IO_L24N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||LOCATED||NO|NONE|
G15||DIFFM|IO_L24P_2|UNUSED||2||||||||||
G16||DIFFM|IO|UNUSED||2||||||||||
H1|ide_data_bus<4>|IOB|IO_L40N_7/VREF_7|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
H1|sram1_io<11>|IOB|IO_L40N_7/VREF_7|BIDIR|LVCMOS25|7|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
H2|||GND|||||||||||||
H3|ide_data_bus<5>|IOB|IO_L39N_7|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
H4|button<3>|IOB|IO_L39P_7|INPUT|LVCMOS25|7||||IFD||||YES|NONE|
H3|sram_a<11>|IOB|IO_L39N_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
H4|sram_a<12>|IOB|IO_L39P_7|OUTPUT|LVCMOS25|7|12|FAST|NONE**|||LOCATED||NO|NONE|
H5|||VCCO_7|||7|||||2.50|||||
H6|||VCCO_7|||7|||||2.50|||||
H7|||GND|||||||||||||
@@ -143,14 +143,14 @@ H9|||GND|||||||||||||
H10|||GND|||||||||||||
H11|||VCCO_2|||2|||||2.50|||||
H12|||VCCO_2|||2|||||2.50|||||
H13||DIFFS|IO_L39N_2|UNUSED||2||||||||||
H14|sram_oe_n|IOB|IO_L39P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H15|sram_we_n|IOB|IO_L40N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H16|sram_a<7>|IOB|IO_L40P_2/VREF_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
J1|ide_data_bus<0>|IOB|IO_L40P_6/VREF_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J2|ide_data_bus<3>|IOB|IO_L40N_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J3|ide_data_bus<10>|IOB|IO_L39P_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J4|ide_data_bus<1>|IOB|IO_L39N_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
H13|slideswitch<3>|IOB|IO_L39N_2|INPUT|LVCMOS25|2||||NONE||LOCATED||NO|NONE|
H14|slideswitch<2>|IOB|IO_L39P_2|INPUT|LVCMOS25|2||||NONE||LOCATED||NO|NONE|
H15||DIFFS|IO_L40N_2|UNUSED||2||||||||||
H16||DIFFM|IO_L40P_2/VREF_2|UNUSED||2||||||||||
J1|sram2_io<4>|IOB|IO_L40P_6/VREF_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
J2|sram1_io<12>|IOB|IO_L40N_6|TRISTATE|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
J3|sram_a<14>|IOB|IO_L39P_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
J4|sram_a<13>|IOB|IO_L39N_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
J5|||VCCO_6|||6|||||2.50|||||
J6|||VCCO_6|||6|||||2.50|||||
J7|||GND|||||||||||||
@@ -159,120 +159,120 @@ J9|||GND|||||||||||||
J10|||GND|||||||||||||
J11|||VCCO_3|||3|||||2.50|||||
J12|||VCCO_3|||3|||||2.50|||||
J13|sram1_io<3>|IOB|IO_L39P_3|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
J14|sram1_io<4>|IOB|IO_L39N_3|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
J13|slideswitch<5>|IOB|IO_L39P_3|INPUT|LVCMOS25|3||||NONE||LOCATED||NO|NONE|
J14|slideswitch<4>|IOB|IO_L39N_3|INPUT|LVCMOS25|3||||NONE||LOCATED||NO|NONE|
J15|||GND|||||||||||||
J16|sram_a<0>|IOB|IO_L40N_3/VREF_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K1|ide_data_bus<11>|IOB|IO|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
K2|ide_data_bus<9>|IOB|IO_L24P_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
K3|ide_data_bus<8>|IOB|IO_L24N_6/VREF_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
K4|ide_cs<0>|IOB|IO_L23P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
K5|ide_data_bus<6>|IOB|IO_L23N_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J16||DIFFS|IO_L40N_3/VREF_3|UNUSED||3||||||||||
K1|sram2_io<3>|IOB|IO|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
K2|sram2_io<13>|IOB|IO_L24P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
K3|sram_a<15>|IOB|IO_L24N_6/VREF_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
K4|sram_oe_n|IOB|IO_L23P_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
K5|sram_a<16>|IOB|IO_L23N_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
K6|||VCCO_6|||6|||||2.50|||||
K7|||GND|||||||||||||
K8|||GND|||||||||||||
K9|||GND|||||||||||||
K10|||GND|||||||||||||
K11|||VCCO_3|||3|||||2.50|||||
K12|sram_a<13>|IOB|IO_L23N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K13|sram1_io<6>|IOB|IO_L24P_3|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
K14|sram_a<14>|IOB|IO_L24N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K15|sram1_io<5>|IOB|IO|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
K16|sram_a<3>|IOB|IO_L40P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K12|led<0>|IOB|IO_L23N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
K13|slideswitch<7>|IOB|IO_L24P_3|INPUT|LVCMOS25|3||||NONE||LOCATED||NO|NONE|
K14|slideswitch<6>|IOB|IO_L24N_3|INPUT|LVCMOS25|3||||NONE||LOCATED||NO|NONE|
K15||DIFFS|IO|UNUSED||3||||||||||
K16||DIFFM|IO_L40P_3|UNUSED||3||||||||||
L1|||VCCAUX||||||||2.5|||||
L2|ide_data_bus<12>|IOB|IO_L22P_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L3|ide_data_bus<14>|IOB|IO_L22N_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L4|ide_data_bus<15>|IOB|IO_L21P_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L5|ide_data_bus<13>|IOB|IO_L21N_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L2|sram1_io<13>|IOB|IO_L22P_6|TRISTATE|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
L3|sram_a<17>|IOB|IO_L22N_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
L4|sram_a<4>|IOB|IO_L21P_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
L5|sram_a<0>|IOB|IO_L21N_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
L6|||GND|||||||||||||
L7|||VCCO_5|||5|||||2.50|||||
L8|||VCCO_5|||5|||||2.50|||||
L9|||VCCO_4|||4|||||2.50|||||
L10|||VCCO_4|||4|||||2.50|||||
L11|||GND|||||||||||||
L12|sram_a<10>|IOB|IO_L23P_3/VREF_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L13|sram_a<11>|IOB|IO_L21N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L14|sram_a<9>|IOB|IO_L22P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L15|sram_a<8>|IOB|IO_L22N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L12|led<2>|IOB|IO_L23P_3/VREF_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
L13|button<2>|IOB|IO_L21N_3|INPUT|LVCMOS25|3||||NONE||LOCATED||NO|NONE|
L14|button<3>|IOB|IO_L22P_3|INPUT|LVCMOS25|3||||IFD||LOCATED||YES|NONE|
L15||DIFFS|IO_L22N_3|UNUSED||3||||||||||
L16|||VCCAUX||||||||2.5|||||
M1|sram2_io<6>|IOB|IO_L20P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M2|sram2_io<5>|IOB|IO_L20N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M3|sram2_io<4>|IOB|IO_L19P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M4|sram2_io<3>|IOB|IO_L19N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M1|sram2_io<14>|IOB|IO_L20P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
M2|sram2_io<2>|IOB|IO_L20N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
M3|sram_a<3>|IOB|IO_L19P_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
M4|sram_a<2>|IOB|IO_L19N_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
M5|||VCCINT||||||||1.2|||||
M6||DIFFM|IO_L28P_5/D7|UNUSED||5||||||||||
M7||DIFFM|IO_L30P_5|UNUSED||5||||||||||
M8|||VCCO_5|||5|||||2.50|||||
M9|||VCCO_4|||4|||||2.50|||||
M10||DIFFS|IO_L29N_4|UNUSED||4||||||||||
M11|sram_a<2>|IOB|IO_L27N_4/DIN/D0|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
M11||DIFFS|IO_L27N_4/DIN/D0|UNUSED||4||||||||||
M12|||VCCINT||||||||1.2|||||
M13|sram_a<5>|IOB|IO_L21P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
M14||DIFFS|IO_L19N_3|UNUSED||3||||||||||
M15|sram_a<12>|IOB|IO_L20P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
M16|sram_a<6>|IOB|IO_L20N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
N1|sram2_io<2>|IOB|IO_L17P_6/VREF_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N2|sram2_io<1>|IOB|IO_L17N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N3|sram2_io<0>|IOB|IO_L16P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M13|button<0>|IOB|IO_L21P_3|INPUT|LVCMOS25|3||||NONE||LOCATED||NO|NONE|
M14|button<1>|IOB|IO_L19N_3|INPUT|LVCMOS25|3||||NONE||LOCATED||NO|NONE|
M15||DIFFM|IO_L20P_3|UNUSED||3||||||||||
M16||DIFFS|IO_L20N_3|UNUSED||3||||||||||
N1|sram2_io<15>|IOB|IO_L17P_6/VREF_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
N2|sram2_io<1>|IOB|IO_L17N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
N3|sram_a<1>|IOB|IO_L16P_6|OUTPUT|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
N4|||VCCINT||||||||1.2|||||
N5||IOB|IO|UNUSED||5||||||||||
N5|sram2_ce_n|IOB|IO|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||LOCATED||NO|NONE|
N6||DIFFS|IO_L28N_5/D6|UNUSED||5||||||||||
N7||DIFFS|IO_L30N_5|UNUSED||5||||||||||
N8|sram1_io<0>|IOB|IO_L32P_5/GCLK2|BIDIR|LVCMOS25|5|12|SLOW|NONE**|NONE||||NO|NONE|
N9|sram1_io<8>|IOB|IO_L31N_4/INIT_B|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
N7|sram1_io<0>|IOB|IO_L30N_5|BIDIR|LVCMOS25|5|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
N8||DIFFM|IO_L32P_5/GCLK2|UNUSED||5||||||||||
N9||DIFFS|IO_L31N_4/INIT_B|UNUSED||4||||||||||
N10||DIFFM|IO_L29P_4|UNUSED||4||||||||||
N11|rs232_rxd|IOB|IO_L27P_4/D1|INPUT|LVCMOS25|4||||IFD||||YES|NONE|
N12|sram1_io<9>|IOB|IO/VREF_4|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
N11||DIFFM|IO_L27P_4/D1|UNUSED||4||||||||||
N12|led<5>|IOB|IO/VREF_4|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||LOCATED||NO|NONE|
N13|||VCCINT||||||||1.2|||||
N14||DIFFM|IO_L19P_3|UNUSED||3||||||||||
N15||DIFFM|IO_L17P_3/VREF_3|UNUSED||3||||||||||
N16||DIFFS|IO_L17N_3|UNUSED||3||||||||||
P1|sram2_ce_n|IOB|IO_L01P_6/VRN_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
P2|sram1_lb_n|IOB|IO_L16N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N14|led<3>|IOB|IO_L19P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
N15|sevenseg<5>|IOB|IO_L17P_3/VREF_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
N16|sevenseg<1>|IOB|IO_L17N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
P1|sram1_io<14>|IOB|IO_L01P_6/VRN_6|TRISTATE|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
P2|sram2_io<0>|IOB|IO_L16N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||LOCATED||NO|NONE|
P3|||M0|||||||||||||
P4|||M2|||||||||||||
P5|ide_cs<1>|IOB|IO_L27P_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
P6||DIFFM|IO_L29P_5/VREF_5|UNUSED||5||||||||||
P7||IOB|IO|UNUSED||5||||||||||
P8|sram1_io<1>|IOB|IO_L32N_5/GCLK3|BIDIR|LVCMOS25|5|12|SLOW|NONE**|NONE||||NO|NONE|
P9|sram_a<4>|IOB|IO_L31P_4/DOUT/BUSY|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
P5|sram2_lb_n|IOB|IO_L27P_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||LOCATED||NO|NONE|
P6|sram1_lb_n|IOB|IO_L29P_5/VREF_5|OUTPUT|LVCMOS25|5|12|FAST|NONE**|||LOCATED||NO|NONE|
P7|sram1_ce_n|IOB|IO|OUTPUT|LVCMOS25|5|12|FAST|NONE**|||LOCATED||NO|NONE|
P8|sram1_io<9>|IOB|IO_L32N_5/GCLK3|BIDIR|LVCMOS25|5|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
P9||DIFFM|IO_L31P_4/DOUT/BUSY|UNUSED||4||||||||||
P10||DIFFS|IO_L30N_4/D2|UNUSED||4||||||||||
P11||DIFFS|IO_L28N_4|UNUSED||4||||||||||
P12||DIFFS|IO_L25N_4|UNUSED||4||||||||||
P13||IOB|IO/VREF_4|UNUSED||4||||||||||
P14||DIFFM|IO_L16P_3|UNUSED||3||||||||||
P15||DIFFS|IO_L16N_3|UNUSED||3||||||||||
P16||DIFFS|IO_L01N_3/VRP_3|UNUSED||3||||||||||
R1||DIFFS|IO_L01N_6/VRP_6|UNUSED||6||||||||||
P11|led<7>|IOB|IO_L28N_4|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||LOCATED||NO|NONE|
P12|led<6>|IOB|IO_L25N_4|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||LOCATED||NO|NONE|
P13|led<4>|IOB|IO/VREF_4|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||LOCATED||NO|NONE|
P14|led<1>|IOB|IO_L16P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
P15|sevenseg<4>|IOB|IO_L16N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
P16|sevenseg<0>|IOB|IO_L01N_3/VRP_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
R1|sram1_io<15>|IOB|IO_L01N_6/VRP_6|TRISTATE|LVCMOS25|6|12|FAST|NONE**|||LOCATED||NO|NONE|
R2|||GND|||||||||||||
R3||DIFFM|IO_L01P_5/CS_B|UNUSED||5||||||||||
R4|sram2_io<7>|IOB|IO_L10P_5/VRN_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
R5|ide_da<1>|IOB|IO_L27N_5/VREF_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
R6||DIFFS|IO_L29N_5|UNUSED||5||||||||||
R4|sram2_ub_n|IOB|IO_L10P_5/VRN_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||LOCATED||NO|NONE|
R5|sram1_io<4>|IOB|IO_L27N_5/VREF_5|BIDIR|LVCMOS25|5|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
R6|sram1_io<2>|IOB|IO_L29N_5|BIDIR|LVCMOS25|5|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
R7||DIFFM|IO_L31P_5/D5|UNUSED||5||||||||||
R8|||GND|||||||||||||
R9|sram1_io<11>|IOB|IO_L32N_4/GCLK1|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
R9||DIFFS|IO_L32N_4/GCLK1|UNUSED||4||||||||||
R10||DIFFM|IO_L30P_4/D3|UNUSED||4||||||||||
R11||DIFFM|IO_L28P_4|UNUSED||4||||||||||
R12||DIFFM|IO_L25P_4|UNUSED||4||||||||||
R13||DIFFS|IO_L01N_4/VRP_4|UNUSED||4||||||||||
R13|rs232_txd|IOB|IO_L01N_4/VRP_4|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||LOCATED||NO|NONE|
R14|||DONE|||||||||||||
R15|||GND|||||||||||||
R16||DIFFM|IO_L01P_3/VRN_3|UNUSED||3||||||||||
R16|sevenseg<3>|IOB|IO_L01P_3/VRN_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||LOCATED||NO|NONE|
T1|||GND|||||||||||||
T2|||M1|||||||||||||
T3||DIFFS|IO_L01N_5/RDWR_B|UNUSED||5||||||||||
T4||DIFFS|IO_L10N_5/VRP_5|UNUSED||5||||||||||
T5|ide_da<2>|IOB|IO|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
T4|sram1_ub_n|IOB|IO_L10N_5/VRP_5|OUTPUT|LVCMOS25|5|12|FAST|NONE**|||LOCATED||NO|NONE|
T5|sram1_io<3>|IOB|IO|BIDIR|LVCMOS25|5|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
T6|||VCCAUX||||||||2.5|||||
T7||DIFFS|IO_L31N_5/D4|UNUSED||5||||||||||
T8|sram1_io<2>|IOB|IO/VREF_5|BIDIR|LVCMOS25|5|12|SLOW|NONE**|NONE||||NO|NONE|
T9|sram1_io<7>|IOB|IO_L32P_4/GCLK0|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
T10|sram1_ce_n|IOB|IO/VREF_4|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
T8|sram1_io<1>|IOB|IO/VREF_5|BIDIR|LVCMOS25|5|12|FAST|NONE**|NONE||LOCATED||NO|NONE|
T9|sysclk|IOB|IO_L32P_4/GCLK0|INPUT|LVCMOS25|4||||NONE||LOCATED||NO|NONE|
T10||IOB|IO/VREF_4|UNUSED||4||||||||||
T11|||VCCAUX||||||||2.5|||||
T12|sram_a<1>|IOB|IO|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
T13||DIFFM|IO_L01P_4/VRN_4|UNUSED||4||||||||||
T14|sram1_io<10>|IOB|IO|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
T12||IOB|IO|UNUSED||4||||||||||
T13|rs232_rxd|IOB|IO_L01P_4/VRN_4|INPUT|LVCMOS25|4||||IFD||LOCATED||YES|NONE|
T14||DIFFS|IO|UNUSED||4||||||||||
T15|||CCLK|||||||||||||
T16|||GND|||||||||||||

169
xilinx/pdp8/top.par
View File

@@ -1,34 +1,34 @@
Release 8.2i par I.31
Release 8.2.03i par I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
wide:: Fri Apr 16 08:16:15 2010
LATITUDE:: Fri Apr 23 22:47:52 2010
par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
Constraints file: top.pcf.
Loading device for application Rf_Device from file '3s1000.nph' in environment /opt/Xilinx.
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
"top" is an NCD, version 3.1, device xc3s1000, package ft256, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.38 2006-05-03".
Device speed data version: "PRODUCTION 1.39 2006-08-18".
Device Utilization Summary:
Number of BUFGMUXs 3 out of 8 37%
Number of External IOBs 89 out of 173 51%
Number of LOCed IOBs 0 out of 89 0%
Number of External IOBs 116 out of 173 67%
Number of LOCed IOBs 116 out of 116 100%
Number of Slices 1135 out of 7680 14%
Number of Slices 1120 out of 7680 14%
Number of SLICEMs 96 out of 3840 2%
@@ -38,86 +38,88 @@ Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
WARNING:Par:288 - The signal slideswitch<4>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal slideswitch<5>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal slideswitch<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal slideswitch<7>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal button<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal button<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal button<2>_IBUF has no load. PAR will not attempt to route this signal.
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:98cab7) REAL time: 7 secs
Phase 1.1 (Checksum:98cb0b) REAL time: 4 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 7 secs
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 5 secs
Phase 3.2
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 5 secs
Phase 4.2
.
Phase 3.2 (Checksum:1c9c37d) REAL time: 12 secs
Phase 4.2 (Checksum:26259fc) REAL time: 7 secs
Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 12 secs
Phase 5.8
.........................................................
..........................................................
.........
.......
.......
....
Phase 5.8 (Checksum:b6bb50) REAL time: 15 secs
Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 12 secs
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 15 secs
Phase 6.8
.............
........
.................................
........
.....
.....
Phase 6.8 (Checksum:c1aa4b) REAL time: 30 secs
Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 25 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 30 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 51 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 51 secs
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 25 secs
Writing design to file top.ncd
Total REAL time to Placer completion: 54 secs
Total CPU time to Placer completion: 54 secs
Total REAL time to Placer completion: 26 secs
Total CPU time to Placer completion: 25 secs
Starting Router
Phase 1: 8419 unrouted; REAL time: 54 secs
Phase 1: 8578 unrouted; REAL time: 26 secs
Phase 2: 7883 unrouted; REAL time: 55 secs
Phase 2: 8072 unrouted; REAL time: 26 secs
Phase 3: 1987 unrouted; REAL time: 57 secs
Phase 3: 2222 unrouted; REAL time: 27 secs
Phase 4: 1987 unrouted; (77716) REAL time: 58 secs
Phase 4: 2222 unrouted; (56101) REAL time: 28 secs
Phase 5: 2030 unrouted; (0) REAL time: 59 secs
Phase 5: 2251 unrouted; (0) REAL time: 28 secs
Phase 6: 0 unrouted; (229) REAL time: 1 mins 5 secs
Phase 6: 0 unrouted; (0) REAL time: 31 secs
Phase 7: 0 unrouted; (229) REAL time: 1 mins 6 secs
Phase 7: 0 unrouted; (0) REAL time: 32 secs
Phase 8: 0 unrouted; (204) REAL time: 1 mins 12 secs
Phase 9: 0 unrouted; (121) REAL time: 1 mins 20 secs
Phase 10: 0 unrouted; (121) REAL time: 1 mins 21 secs
WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/tx_baud_clk may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:ram_rd may have excessive skew because
16 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:io/kw/kw_src_clk may have excessive skew because
6 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/rx_baud_clk may have excessive skew because
WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/tx_baud_clk may have excessive skew because
1 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:show_pc/aclk may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:reset_sw/slowclk may have excessive skew because
1 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:clk may have excessive skew because
1 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/rx_baud_clk may have excessive skew because
1 NON-CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 1 mins 21 secs
Total CPU time to Router completion: 1 mins 21 secs
Total REAL time to Router completion: 32 secs
Total CPU time to Router completion: 31 secs
Partition Implementation Status
-------------------------------
@@ -135,19 +137,23 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sysclk_BUFGP | BUFGMUX5| No | 23 | 0.107 | 0.729 |
| clk | BUFGMUX7| No | 377 | 0.372 | 0.987 |
+---------------------+--------------+------+------+------------+-------------+
| sysclk_BUFGP | BUFGMUX0| No | 47 | 0.198 | 0.837 |
+---------------------+--------------+------+------+------------+-------------+
|io/tt/baud_rate_gene | | | | | |
| rator/rx_baud_clk | BUFGMUX1| No | 24 | 0.208 | 0.861 |
| rator/rx_baud_clk | BUFGMUX2| No | 24 | 0.206 | 0.873 |
+---------------------+--------------+------+------+------------+-------------+
| clk | BUFGMUX7| No | 445 | 0.402 | 1.013 |
| io/kw/kw_src_clk | Local| | 7 | 0.913 | 1.831 |
+---------------------+--------------+------+------+------------+-------------+
| io/kw/kw_src_clk | Local| | 7 | 0.334 | 1.254 |
| ram_rd | Local| | 27 | 0.072 | 2.050 |
+---------------------+--------------+------+------+------------+-------------+
| reset_sw/slowclk | Local| | 8 | 0.475 | 3.214 |
| reset_sw/slowclk | Local| | 8 | 0.426 | 3.122 |
+---------------------+--------------+------+------+------------+-------------+
|io/tt/baud_rate_gene | | | | | |
| rator/tx_baud_clk | Local| | 10 | 1.260 | 2.212 |
| rator/tx_baud_clk | Local| | 10 | 0.011 | 1.999 |
+---------------------+--------------+------+------+------------+-------------+
| show_pc/aclk | Local| | 3 | 0.593 | 1.538 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@@ -161,15 +167,15 @@ the minimum and maximum path delays which includes logic delays.
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 1.193
The MAXIMUM PIN DELAY IS: 6.943
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 5.121
The AVERAGE CONNECTION DELAY for this design is: 1.144
The MAXIMUM PIN DELAY IS: 4.815
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 4.456
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
4218 2975 763 395 31 0
4547 2799 845 329 19 0
Timing Score: 0
@@ -180,23 +186,29 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Requested | Actual | Logic | Absolute |Number of
| | | Levels | Slack |errors
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | N/A | 11.634ns | 8 | N/A | N/A
Autotimespec constraint for clock net clk | N/A | 11.651ns | 7 | N/A | N/A
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net io/ | N/A | 3.636ns | 3 | N/A | N/A
Autotimespec constraint for clock net io/ | N/A | 4.230ns | 3 | N/A | N/A
kw/kw_src_clk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | N/A | 4.081ns | 13 | N/A | N/A
Autotimespec constraint for clock net sys | N/A | 4.720ns | 2 | N/A | N/A
clk_BUFGP | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net io/ | N/A | 5.078ns | 3 | N/A | N/A
Autotimespec constraint for clock net ram | N/A | 2.171ns | 1 | N/A | N/A
_rd | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net io/ | N/A | 5.007ns | 2 | N/A | N/A
tt/baud_rate_generator/rx_baud_clk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net res | N/A | 2.808ns | 0 | N/A | N/A
Autotimespec constraint for clock net res | N/A | 2.836ns | 0 | N/A | N/A
et_sw/slowclk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net io/ | N/A | 4.548ns | 1 | N/A | N/A
Autotimespec constraint for clock net io/ | N/A | 4.343ns | 2 | N/A | N/A
tt/baud_rate_generator/tx_baud_clk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sho | N/A | 2.638ns | 1 | N/A | N/A
w_pc/aclk | | | | |
------------------------------------------------------------------------------------------------------
All constraints were met.
@@ -208,16 +220,19 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 1 mins 25 secs
Total CPU time to PAR completion: 1 mins 25 secs
WARNING:Par:284 - There are 7 sourceless or loadless signals in this design. This design will not pass the DRC check run
by Bitgen.
Peak Memory Usage: 427 MB
Total REAL time to PAR completion: 34 secs
Total CPU time to PAR completion: 33 secs
Peak Memory Usage: 178 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 5
Number of warning messages: 15
Number of info messages: 1
Writing design to file top.ncd

130
xilinx/pdp8/top.pcf
View File

@@ -1,7 +1,123 @@
//! **************************************************************************
// Written by: Map I.31 on Fri Apr 16 08:16:08 2010
//! **************************************************************************
SCHEMATIC START;
NET "sysclk_BUFGP/IBUFG" BEL "sysclk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
SCHEMATIC END;
//! **************************************************************************
// Written by: Map I.34 on Fri Apr 23 22:47:47 2010
//! **************************************************************************
SCHEMATIC START;
COMP "sram1_ce_n" LOCATE = SITE "P7" LEVEL 1;
COMP "sram1_io<0>" LOCATE = SITE "N7" LEVEL 1;
COMP "sram1_io<1>" LOCATE = SITE "T8" LEVEL 1;
COMP "sram1_io<2>" LOCATE = SITE "R6" LEVEL 1;
COMP "sram1_io<3>" LOCATE = SITE "T5" LEVEL 1;
COMP "sram1_io<4>" LOCATE = SITE "R5" LEVEL 1;
COMP "sram1_io<5>" LOCATE = SITE "C2" LEVEL 1;
COMP "sram1_io<6>" LOCATE = SITE "C1" LEVEL 1;
COMP "sram1_io<7>" LOCATE = SITE "B1" LEVEL 1;
COMP "sram1_io<8>" LOCATE = SITE "D3" LEVEL 1;
COMP "sram2_ce_n" LOCATE = SITE "N5" LEVEL 1;
COMP "sram1_io<9>" LOCATE = SITE "P8" LEVEL 1;
COMP "sram1_lb_n" LOCATE = SITE "P6" LEVEL 1;
COMP "sram2_io<0>" LOCATE = SITE "P2" LEVEL 1;
COMP "sram2_io<1>" LOCATE = SITE "N2" LEVEL 1;
COMP "sram2_io<2>" LOCATE = SITE "M2" LEVEL 1;
COMP "sram2_io<3>" LOCATE = SITE "K1" LEVEL 1;
COMP "sram2_io<4>" LOCATE = SITE "J1" LEVEL 1;
COMP "sram2_io<5>" LOCATE = SITE "G2" LEVEL 1;
COMP "sram2_io<6>" LOCATE = SITE "E1" LEVEL 1;
COMP "sram2_lb_n" LOCATE = SITE "P5" LEVEL 1;
COMP "sram2_io<7>" LOCATE = SITE "D1" LEVEL 1;
COMP "sram2_io<8>" LOCATE = SITE "D2" LEVEL 1;
COMP "sram2_io<9>" LOCATE = SITE "E2" LEVEL 1;
COMP "sevenseg<0>" LOCATE = SITE "P16" LEVEL 1;
COMP "sram1_io<10>" LOCATE = SITE "F2" LEVEL 1;
COMP "sevenseg<1>" LOCATE = SITE "N16" LEVEL 1;
COMP "sram1_io<11>" LOCATE = SITE "H1" LEVEL 1;
COMP "sevenseg<2>" LOCATE = SITE "F13" LEVEL 1;
COMP "sram1_io<12>" LOCATE = SITE "J2" LEVEL 1;
COMP "sevenseg<3>" LOCATE = SITE "R16" LEVEL 1;
COMP "sram1_io<13>" LOCATE = SITE "L2" LEVEL 1;
COMP "sevenseg<4>" LOCATE = SITE "P15" LEVEL 1;
COMP "sram1_io<14>" LOCATE = SITE "P1" LEVEL 1;
COMP "sevenseg<5>" LOCATE = SITE "N15" LEVEL 1;
COMP "sram1_io<15>" LOCATE = SITE "R1" LEVEL 1;
COMP "sevenseg<6>" LOCATE = SITE "G13" LEVEL 1;
COMP "sevenseg<7>" LOCATE = SITE "E14" LEVEL 1;
COMP "sram1_ub_n" LOCATE = SITE "T4" LEVEL 1;
COMP "sysclk" LOCATE = SITE "T9" LEVEL 1;
COMP "sram2_ub_n" LOCATE = SITE "R4" LEVEL 1;
COMP "led<0>" LOCATE = SITE "K12" LEVEL 1;
COMP "led<1>" LOCATE = SITE "P14" LEVEL 1;
COMP "led<2>" LOCATE = SITE "L12" LEVEL 1;
COMP "led<3>" LOCATE = SITE "N14" LEVEL 1;
COMP "led<4>" LOCATE = SITE "P13" LEVEL 1;
COMP "led<5>" LOCATE = SITE "N12" LEVEL 1;
COMP "led<6>" LOCATE = SITE "P12" LEVEL 1;
COMP "led<7>" LOCATE = SITE "P11" LEVEL 1;
COMP "sram2_io<10>" LOCATE = SITE "G1" LEVEL 1;
COMP "sram2_io<11>" LOCATE = SITE "F5" LEVEL 1;
COMP "sram2_io<12>" LOCATE = SITE "C3" LEVEL 1;
COMP "sram2_io<13>" LOCATE = SITE "K2" LEVEL 1;
COMP "sram2_io<14>" LOCATE = SITE "M1" LEVEL 1;
COMP "sram2_io<15>" LOCATE = SITE "N1" LEVEL 1;
COMP "sram_oe_n" LOCATE = SITE "K4" LEVEL 1;
COMP "slideswitch<0>" LOCATE = SITE "F12" LEVEL 1;
COMP "slideswitch<1>" LOCATE = SITE "G12" LEVEL 1;
COMP "slideswitch<2>" LOCATE = SITE "H14" LEVEL 1;
COMP "slideswitch<3>" LOCATE = SITE "H13" LEVEL 1;
COMP "slideswitch<4>" LOCATE = SITE "J14" LEVEL 1;
COMP "slideswitch<5>" LOCATE = SITE "J13" LEVEL 1;
COMP "slideswitch<6>" LOCATE = SITE "K14" LEVEL 1;
COMP "slideswitch<7>" LOCATE = SITE "K13" LEVEL 1;
COMP "sram_we_n" LOCATE = SITE "G3" LEVEL 1;
COMP "ide_data_bus<0>" LOCATE = SITE "B5" LEVEL 1;
COMP "ide_data_bus<1>" LOCATE = SITE "B4" LEVEL 1;
COMP "ide_data_bus<2>" LOCATE = SITE "D10" LEVEL 1;
COMP "ide_data_bus<3>" LOCATE = SITE "D8" LEVEL 1;
COMP "ide_data_bus<4>" LOCATE = SITE "D7" LEVEL 1;
COMP "ide_data_bus<5>" LOCATE = SITE "E7" LEVEL 1;
COMP "ide_data_bus<6>" LOCATE = SITE "D6" LEVEL 1;
COMP "ide_data_bus<7>" LOCATE = SITE "D5" LEVEL 1;
COMP "ide_data_bus<8>" LOCATE = SITE "C5" LEVEL 1;
COMP "ide_data_bus<9>" LOCATE = SITE "C6" LEVEL 1;
COMP "ide_da<0>" LOCATE = SITE "B12" LEVEL 1;
COMP "ide_da<1>" LOCATE = SITE "B13" LEVEL 1;
COMP "ide_da<2>" LOCATE = SITE "B14" LEVEL 1;
COMP "ide_cs<0>" LOCATE = SITE "A9" LEVEL 1;
COMP "ide_cs<1>" LOCATE = SITE "A10" LEVEL 1;
COMP "rs232_rxd" LOCATE = SITE "T13" LEVEL 1;
COMP "rs232_txd" LOCATE = SITE "R13" LEVEL 1;
COMP "button<0>" LOCATE = SITE "M13" LEVEL 1;
COMP "button<1>" LOCATE = SITE "M14" LEVEL 1;
COMP "button<2>" LOCATE = SITE "L13" LEVEL 1;
COMP "button<3>" LOCATE = SITE "L14" LEVEL 1;
COMP "sevenseg_an<0>" LOCATE = SITE "D14" LEVEL 1;
COMP "sevenseg_an<1>" LOCATE = SITE "G14" LEVEL 1;
COMP "sevenseg_an<2>" LOCATE = SITE "F14" LEVEL 1;
COMP "sevenseg_an<3>" LOCATE = SITE "E13" LEVEL 1;
COMP "sram_a<10>" LOCATE = SITE "G5" LEVEL 1;
COMP "sram_a<11>" LOCATE = SITE "H3" LEVEL 1;
COMP "sram_a<12>" LOCATE = SITE "H4" LEVEL 1;
COMP "sram_a<13>" LOCATE = SITE "J4" LEVEL 1;
COMP "sram_a<14>" LOCATE = SITE "J3" LEVEL 1;
COMP "sram_a<15>" LOCATE = SITE "K3" LEVEL 1;
COMP "sram_a<16>" LOCATE = SITE "K5" LEVEL 1;
COMP "sram_a<17>" LOCATE = SITE "L3" LEVEL 1;
COMP "ide_data_bus<10>" LOCATE = SITE "C7" LEVEL 1;
COMP "ide_dior" LOCATE = SITE "B10" LEVEL 1;
COMP "ide_data_bus<11>" LOCATE = SITE "C8" LEVEL 1;
COMP "ide_data_bus<12>" LOCATE = SITE "C9" LEVEL 1;
COMP "sram_a<0>" LOCATE = SITE "L5" LEVEL 1;
COMP "ide_diow" LOCATE = SITE "A8" LEVEL 1;
COMP "ide_data_bus<13>" LOCATE = SITE "A3" LEVEL 1;
COMP "sram_a<1>" LOCATE = SITE "N3" LEVEL 1;
COMP "ide_data_bus<14>" LOCATE = SITE "A4" LEVEL 1;
COMP "sram_a<2>" LOCATE = SITE "M4" LEVEL 1;
COMP "ide_data_bus<15>" LOCATE = SITE "A5" LEVEL 1;
COMP "sram_a<3>" LOCATE = SITE "M3" LEVEL 1;
COMP "sram_a<4>" LOCATE = SITE "L4" LEVEL 1;
COMP "sram_a<5>" LOCATE = SITE "G4" LEVEL 1;
COMP "sram_a<6>" LOCATE = SITE "F3" LEVEL 1;
COMP "sram_a<7>" LOCATE = SITE "F4" LEVEL 1;
COMP "sram_a<8>" LOCATE = SITE "E3" LEVEL 1;
COMP "sram_a<9>" LOCATE = SITE "E4" LEVEL 1;
NET "sysclk_BUFGP/IBUFG" BEL "sysclk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
SCHEMATIC END;

29
xilinx/pdp8/top.prj
View File

@@ -1,13 +1,16 @@
verilog work "../../rtl/ide.v"
verilog work "../../rtl/uart.v"
verilog work "../../rtl/ram_256x12.v"
verilog work "../../rtl/ide_disk.v"
verilog work "../../rtl/brg.v"
verilog work "../../rtl/pdp8_tt.v"
verilog work "../../rtl/pdp8_rf.v"
verilog work "../../rtl/pdp8_kw.v"
verilog work "../../rtl/pdp8_ram.v"
verilog work "../../rtl/pdp8_io.v"
verilog work "../../rtl/pdp8.v"
verilog work "../../rtl/debounce.v"
verilog work "../../rtl/top.v"
verilog work "../../rtl/ide.v"
verilog work "../../rtl/uart.v"
verilog work "../../rtl/ram_256x12.v"
verilog work "../../rtl/ide_disk.v"
verilog work "../../rtl/brg.v"
verilog work "../../rtl/sevensegdecode.v"
verilog work "../../rtl/pdp8_tt.v"
verilog work "../../rtl/pdp8_rf.v"
verilog work "../../rtl/pdp8_kw.v"
verilog work "../../rtl/bootrom.v"
verilog work "../../rtl/pdp8_ram.v"
verilog work "../../rtl/pdp8_io.v"
verilog work "../../rtl/pdp8.v"
verilog work "../../rtl/display.v"
verilog work "../../rtl/debounce.v"
verilog work "../../rtl/top.v"

655
xilinx/pdp8/top.syr
View File

File diff suppressed because it is too large Load Diff

115
xilinx/pdp8/top.twr
View File

@@ -1,57 +1,58 @@
--------------------------------------------------------------------------------
Release 8.2i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
trce -ise /home/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise -e 3 -l 3 -s 5
-xml top top.ncd -o top.twr top.pcf
Design file: top.ncd
Physical constraint file: top.pcf
Device,speed: xc3s1000,-5 (PRODUCTION 1.38 2006-05-03)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock sysclk
--------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------+------------+------------+------------------+--------+
slideswitch<2>| 3.851(R)| -1.343(R)|sysclk_BUFGP | 0.000|
slideswitch<3>| 3.548(R)| -1.100(R)|sysclk_BUFGP | 0.000|
--------------+------------+------------+------------------+--------+
Clock to Setup on destination clock sysclk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sysclk | 4.081| | | |
---------------+---------+---------+---------+---------+
Analysis completed Fri Apr 16 08:17:51 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 267 MB
--------------------------------------------------------------------------------
Release 8.2.03i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
C:\Xilinx\bin\nt\trce.exe -ise C:/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise
-e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf
C:/brad/pdp8/synth/s3board.ucf
Design file: top.ncd
Physical constraint file: top.pcf
Device,speed: xc3s1000,-5 (PRODUCTION 1.39 2006-08-18)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock sysclk
--------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------+------------+------------+------------------+--------+
slideswitch<2>| 4.986(R)| -1.884(R)|sysclk_BUFGP | 0.000|
slideswitch<3>| 5.549(R)| -2.335(R)|sysclk_BUFGP | 0.000|
--------------+------------+------------+------------------+--------+
Clock to Setup on destination clock sysclk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sysclk | 4.720| | | |
---------------+---------+---------+---------+---------+
Analysis completed Fri Apr 23 22:48:33 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 144 MB

9
xilinx/pdp8/top.twx
View File

@@ -270,10 +270,11 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead><twExecVer>Release 8.2i Trace </twExecVer><twCopyright>Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>trce -ise /home/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise -e 3 -l 3 -s 5
-xml top top.ncd -o top.twr top.pcf
<twReport><twHead><twExecVer>Release 8.2.03i Trace </twExecVer><twCopyright>Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\bin\nt\trce.exe -ise C:/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise
-e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf
C:/brad/pdp8/synth/s3board.ucf
</twCmdLine><twDesign>top.ncd</twDesign><twPCF>top.pcf</twPCF><twDevInfo arch="spartan3"><twDevName>xc3s1000</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.38 2006-05-03</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twErr"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twBody><twErrRpt><twDataSheet twNameLen="15"><twSUH2ClkList twDestWidth = "14" twPhaseWidth = "12"><twDest>sysclk</twDest><twSUH2Clk ><twSrc>slideswitch&lt;2&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.851</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.343</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>slideswitch&lt;3&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.548</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.100</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2SUList twDestWidth = "6"><twDest>sysclk</twDest><twClk2SU><twSrc>sysclk</twSrc><twRiseRise>4.081</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twFoot><twTimestamp>Fri Apr 16 08:17:51 2010</twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
</twCmdLine><twDesign>top.ncd</twDesign><twPCF>top.pcf</twPCF><twDevInfo arch="spartan3"><twDevName>xc3s1000</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.39 2006-08-18</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twErr"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twBody><twErrRpt><twDataSheet twNameLen="15"><twSUH2ClkList twDestWidth = "14" twPhaseWidth = "12"><twDest>sysclk</twDest><twSUH2Clk ><twSrc>slideswitch&lt;2&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.986</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.884</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>slideswitch&lt;3&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">5.549</twSU2ClkTime><twH2ClkTime twEdge="twRising">-2.335</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2SUList twDestWidth = "6"><twDest>sysclk</twDest><twClk2SU><twSrc>sysclk</twSrc><twRiseRise>4.720</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twFoot><twTimestamp>Fri Apr 23 22:48:33 2010</twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 267 MB
Peak Memory Usage: 144 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

14
xilinx/pdp8/top.unroutes
View File

@@ -1,7 +1,17 @@
Release 8.2i - par I.31
Release 8.2.03i - par I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Fri Apr 16 08:17:41 2010
Fri Apr 23 22:48:26 2010
There are 0 unrouted networks:
There are 7 sourceless or loadless networks:
button<0>_IBUF
button<1>_IBUF
button<2>_IBUF
slideswitch<4>_IBUF
slideswitch<5>_IBUF
slideswitch<6>_IBUF
slideswitch<7>_IBUF

56
xilinx/pdp8/top.ut
View File

@@ -1,28 +1,28 @@
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:6
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCMShutdown:Disable
-g DCIUpdateMode:AsRequired
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Match_cycle:Auto
-g Security:None
-g DonePipe:No
-g DriveDone:No
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:6
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g DCMShutdown:Disable
-g DCIUpdateMode:AsRequired
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Match_cycle:Auto
-g Security:None
-g DonePipe:No
-g DriveDone:No

6
xilinx/pdp8/top.xpi
View File

@@ -1,3 +1,3 @@
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF

106
xilinx/pdp8/top.xst
View File

@@ -1,53 +1,53 @@
set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn top.prj
-ifmt mixed
-ofn top
-ofmt NGC
-p xc3s1000-5-ft256
-top top
-opt_mode Speed
-opt_level 1
-iuc NO
-lso top.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 8
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn top.prj
-ifmt mixed
-ofn top
-ofmt NGC
-p xc3s1000-5-ft256
-top top
-opt_mode Speed
-opt_level 1
-iuc NO
-lso top.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 8
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

2
xilinx/pdp8/top_last_par.ncd
View File

File diff suppressed because one or more lines are too long

250
xilinx/pdp8/top_map.mrp
View File

@@ -1,40 +1,43 @@
Release 8.2i Map I.31
Release 8.2.03i Map I.34
Xilinx Mapping Report File for Design 'top'
Design Information
------------------
Command Line : map -ise /home/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise -p
xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
Command Line : C:\Xilinx\bin\nt\map.exe -ise C:/brad/pdp8/xilinx/pdp8/pdp8.ise
-intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd
top.ngd top.pcf
Target Device : xc3s1000
Target Package : ft256
Target Speed : -5
Mapper Version : spartan3 -- $Revision: 1.34.32.1 $
Mapped Date : Fri Apr 16 08:15:59 2010
Mapped Date : Fri Apr 23 22:47:42 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 7
Number of warnings: 12
Logic Utilization:
Number of Slice Flip Flops: 519 out of 15,360 3%
Number of 4 input LUTs: 1,532 out of 15,360 9%
Total Number Slice Registers: 493 out of 15,360 3%
Number used as Flip Flops: 481
Number used as Latches: 12
Number of 4 input LUTs: 1,605 out of 15,360 10%
Logic Distribution:
Number of occupied Slices: 1,135 out of 7,680 14%
Number of Slices containing only related logic: 1,135 out of 1,135 100%
Number of Slices containing unrelated logic: 0 out of 1,135 0%
Number of occupied Slices: 1,120 out of 7,680 14%
Number of Slices containing only related logic: 1,120 out of 1,120 100%
Number of Slices containing unrelated logic: 0 out of 1,120 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 1,884 out of 15,360 12%
Number used as logic: 1,532
Number used as a route-thru: 160
Total Number 4 input LUTs: 1,964 out of 15,360 12%
Number used as logic: 1,605
Number used as a route-thru: 167
Number used for 32x1 RAMs: 192
(Two LUTs used per 32x1 RAM)
Number of bonded IOBs: 89 out of 173 51%
Number of bonded IOBs: 116 out of 173 67%
IOB Flip Flops: 14
Number of GCLKs: 3 out of 8 37%
Total equivalent gate count for design: 40,005
Additional JTAG gate count for IOBs: 4,272
Peak Memory Usage: 441 MB
Total equivalent gate count for design: 40,343
Additional JTAG gate count for IOBs: 5,568
Peak Memory Usage: 173 MB
NOTES:
@@ -74,48 +77,52 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network slideswitch<7> has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 26
WARNING:LIT:243 - Logical network slideswitch<7>_IBUF has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 6
more times for the following (max. 5 shown):
slideswitch<6>,
slideswitch<5>,
slideswitch<4>,
button<2>,
button<1>
slideswitch<6>_IBUF,
slideswitch<5>_IBUF,
slideswitch<4>_IBUF,
button<2>_IBUF,
button<1>_IBUF
To see the details of these warning messages, please use the -detail switch.
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_clk/clk_BUFG" (output signal=clk) has a mix of clock
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_clk/clk_BUFG" (output signal=clk) has a mix of clock
and non-clock loads. The non-clock loads are:
Pin D of clk
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol
"physical_group_io/tt/baud_rate_generator/rx_baud_clk/io/tt/baud_rate_generat
or/rx_baud_clk_BUFG" (output signal=io/tt/baud_rate_generator/rx_baud_clk)
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol
"physical_group_io/tt/baud_rate_generator/rx_baud_clk/io/tt/baud_rate_generat
or/rx_baud_clk_BUFG" (output signal=io/tt/baud_rate_generator/rx_baud_clk)
has a mix of clock and non-clock loads. The non-clock loads are:
Pin D of io/tt/baud_rate_generator/rx_baud_clk
WARNING:Pack:266 - The function generator cpu/_mux0009<4>129 failed to merge
with F5 multiplexer cpu/_mux0009<7>73_SW11_f5. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator cpu/_mux0009<4>129 failed to merge
with F5 multiplexer cpu/_mux0009<8>73_SW11_f5. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator cpu/_mux0009<4>129 failed to merge
with F5 multiplexer cpu/_mux0009<6>73_SW1. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ram_rd is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <slideswitch<4>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<5>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<6>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <slideswitch<7>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<0>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <button<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
BUFG symbol "clk_BUFG" (output signal=clk),
BUFG symbol "io/tt/baud_rate_generator/rx_baud_clk_BUFG" (output
BUFG symbol "io/tt/baud_rate_generator/rx_baud_clk_BUFG" (output
signal=io/tt/baud_rate_generator/rx_baud_clk),
BUFGP symbol "sysclk_BUFGP" (output signal=sysclk_BUFGP)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.
Section 4 - Removed Logic Summary
---------------------------------
@@ -129,7 +136,7 @@ TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
@@ -139,55 +146,82 @@ Section 6 - IOB Properties
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| button<0> | IOB | INPUT | LVCMOS25 | | | | | |
| button<1> | IOB | INPUT | LVCMOS25 | | | | | |
| button<2> | IOB | INPUT | LVCMOS25 | | | | | |
| button<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| ide_cs<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_cs<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_da<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_da<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_da<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_data_bus<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<8> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<9> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<10> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<11> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_data_bus<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_data_bus<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_data_bus<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_dior | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_diow | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| ide_cs<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_cs<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_da<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_da<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_da<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_data_bus<0> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<1> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<2> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<3> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<4> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<5> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<6> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<7> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
| ide_data_bus<8> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<9> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<10> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<11> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
| ide_data_bus<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_data_bus<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_data_bus<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_data_bus<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_dior | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| ide_diow | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| led<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| led<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| led<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| led<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| led<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| led<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| led<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| led<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| rs232_rxd | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| rs232_txd | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg_an<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg_an<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg_an<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sevenseg_an<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| slideswitch<0> | IOB | INPUT | LVCMOS25 | | | | | |
| slideswitch<1> | IOB | INPUT | LVCMOS25 | | | | | |
| slideswitch<2> | IOB | INPUT | LVCMOS25 | | | | | |
| slideswitch<3> | IOB | INPUT | LVCMOS25 | | | | | |
| sram1_ce_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<8> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<9> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<10> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<11> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram1_io<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram1_lb_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram1_ub_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| slideswitch<4> | IOB | INPUT | LVCMOS25 | | | | | |
| slideswitch<5> | IOB | INPUT | LVCMOS25 | | | | | |
| slideswitch<6> | IOB | INPUT | LVCMOS25 | | | | | |
| slideswitch<7> | IOB | INPUT | LVCMOS25 | | | | | |
| sram1_ce_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram1_io<0> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<1> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<2> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<3> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<4> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<5> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<6> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<7> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<8> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<9> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<10> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<11> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
| sram1_io<12> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram1_io<13> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram1_io<14> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram1_io<15> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram1_lb_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram1_ub_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram2_ce_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram2_io<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram2_io<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
@@ -207,26 +241,26 @@ Section 6 - IOB Properties
| sram2_io<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram2_lb_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram2_ub_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_oe_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_we_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sram_a<0> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<1> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<2> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<3> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<4> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<5> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<6> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<7> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<8> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<9> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<10> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<11> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<12> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<13> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<14> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<15> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<16> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_a<17> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_oe_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sram_we_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
| sysclk | IOB | INPUT | LVCMOS25 | | | | | |
+------------------------------------------------------------------------------------------------------------------------+

2
xilinx/pdp8/top_map.ncd
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2
xilinx/pdp8/top_map.ngm
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File diff suppressed because one or more lines are too long

292
xilinx/pdp8/top_pad.csv
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@@ -1,7 +1,7 @@
#Release 8.2i - par I.31
#Release 8.2.03i - par I.34
#Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
#Fri Apr 16 08:17:39 2010
#Fri Apr 23 22:48:26 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
@@ -21,120 +21,120 @@
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,DCI Value,IO Register,Signal Integrity,
A1,,,GND,,,,,,,,,,,,,
A2,,,TDI,,,,,,,,,,,,,
A3,slideswitch<1>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
A4,,DIFFM,IO_L01P_0/VRN_0,UNUSED,,0,,,,,,,,,,
A5,,IOB,IO,UNUSED,,0,,,,,,,,,,
A3,ide_data_bus<13>,IOB,IO/VREF_0,TRISTATE,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
A4,ide_data_bus<14>,IOB,IO_L01P_0/VRN_0,TRISTATE,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
A5,ide_data_bus<15>,IOB,IO,TRISTATE,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
A6,,,VCCAUX,,,,,,,,2.5,,,,,
A7,,IOB,IO,UNUSED,,0,,,,,,,,,,
A8,,DIFFM,IO_L32P_0/GCLK6,UNUSED,,0,,,,,,,,,,
A9,,IOB,IO,UNUSED,,1,,,,,,,,,,
A10,,DIFFS,IO_L31N_1/VREF_1,UNUSED,,1,,,,,,,,,,
A8,ide_diow,IOB,IO_L32P_0/GCLK6,OUTPUT,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
A9,ide_cs<0>,IOB,IO,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
A10,ide_cs<1>,IOB,IO_L31N_1/VREF_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
A11,,,VCCAUX,,,,,,,,2.5,,,,,
A12,,IOB,IO,UNUSED,,1,,,,,,,,,,
A13,,DIFFS,IO_L10N_1/VREF_1,UNUSED,,1,,,,,,,,,,
A14,,DIFFS,IO_L01N_1/VRP_1,UNUSED,,1,,,,,,,,,,
A15,,,TDO,,,,,,,,,,,,,
A16,,,GND,,,,,,,,,,,,,
B1,,DIFFM,IO_L01P_7/VRN_7,UNUSED,,7,,,,,,,,,,
B1,sram1_io<7>,IOB,IO_L01P_7/VRN_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
B2,,,GND,,,,,,,,,,,,,
B3,,,PROG_B,,,,,,,,,,,,,
B4,,DIFFS,IO_L01N_0/VRP_0,UNUSED,,0,,,,,,,,,,
B5,ide_da<0>,IOB,IO_L25P_0,OUTPUT,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE,
B4,ide_data_bus<1>,IOB,IO_L01N_0/VRP_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
B5,ide_data_bus<0>,IOB,IO_L25P_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
B6,,DIFFM,IO_L28P_0,UNUSED,,0,,,,,,,,,,
B7,,DIFFM,IO_L30P_0,UNUSED,,0,,,,,,,,,,
B8,,DIFFS,IO_L32N_0/GCLK7,UNUSED,,0,,,,,,,,,,
B9,,,GND,,,,,,,,,,,,,
B10,sram1_io<15>,IOB,IO_L31P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
B11,sram1_io<12>,IOB,IO_L29N_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
B12,,DIFFS,IO_L27N_1,UNUSED,,1,,,,,,,,,,
B13,,DIFFM,IO_L10P_1,UNUSED,,1,,,,,,,,,,
B14,,DIFFM,IO_L01P_1/VRN_1,UNUSED,,1,,,,,,,,,,
B10,ide_dior,IOB,IO_L31P_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
B11,,DIFFS,IO_L29N_1,UNUSED,,1,,,,,,,,,,
B12,ide_da<0>,IOB,IO_L27N_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
B13,ide_da<1>,IOB,IO_L10P_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
B14,ide_da<2>,IOB,IO_L01P_1/VRN_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
B15,,,GND,,,,,,,,,,,,,
B16,,DIFFS,IO_L01N_2/VRP_2,UNUSED,,2,,,,,,,,,,
C1,,DIFFS,IO_L01N_7/VRP_7,UNUSED,,7,,,,,,,,,,
C2,sram2_io<9>,IOB,IO_L16N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
C3,sram2_lb_n,IOB,IO_L16P_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
C1,sram1_io<6>,IOB,IO_L01N_7/VRP_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
C2,sram1_io<5>,IOB,IO_L16N_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
C3,sram2_io<12>,IOB,IO_L16P_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
C4,,,HSWAP_EN,,,,,,,,,,,,,
C5,slideswitch<3>,IOB,IO_L25N_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
C6,,DIFFS,IO_L28N_0,UNUSED,,0,,,,,,,,,,
C7,,DIFFS,IO_L30N_0,UNUSED,,0,,,,,,,,,,
C8,,DIFFM,IO_L31P_0/VREF_0,UNUSED,,0,,,,,,,,,,
C9,sysclk,IOB,IO_L32N_1/GCLK5,INPUT,LVCMOS25,1,,,,NONE,,,,NO,NONE,
C5,ide_data_bus<8>,IOB,IO_L25N_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
C6,ide_data_bus<9>,IOB,IO_L28N_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
C7,ide_data_bus<10>,IOB,IO_L30N_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
C8,ide_data_bus<11>,IOB,IO_L31P_0/VREF_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
C9,ide_data_bus<12>,IOB,IO_L32N_1/GCLK5,TRISTATE,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
C10,,IOB,IO,UNUSED,,1,,,,,,,,,,
C11,sram1_io<13>,IOB,IO_L29P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
C11,,DIFFM,IO_L29P_1,UNUSED,,1,,,,,,,,,,
C12,,DIFFM,IO_L27P_1,UNUSED,,1,,,,,,,,,,
C13,,,TMS,,,,,,,,,,,,,
C14,,,TCK,,,,,,,,,,,,,
C15,,DIFFS,IO_L16N_2,UNUSED,,2,,,,,,,,,,
C16,,DIFFM,IO_L01P_2/VRN_2,UNUSED,,2,,,,,,,,,,
D1,sram2_ub_n,IOB,IO_L17N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
D2,sram2_io<8>,IOB,IO_L17P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
D3,sram1_ub_n,IOB,IO_L19P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
D1,sram2_io<7>,IOB,IO_L17N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
D2,sram2_io<8>,IOB,IO_L17P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
D3,sram1_io<8>,IOB,IO_L19P_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
D4,,,VCCINT,,,,,,,,1.2,,,,,
D5,slideswitch<0>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
D6,slideswitch<2>,IOB,IO_L27P_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
D7,,DIFFM,IO_L29P_0,UNUSED,,0,,,,,,,,,,
D8,,DIFFS,IO_L31N_0,UNUSED,,0,,,,,,,,,,
D9,sram_a<17>,IOB,IO_L32P_1/GCLK4,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
D10,,DIFFS,IO_L30N_1,UNUSED,,1,,,,,,,,,,
D5,ide_data_bus<7>,IOB,IO/VREF_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
D6,ide_data_bus<6>,IOB,IO_L27P_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
D7,ide_data_bus<4>,IOB,IO_L29P_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
D8,ide_data_bus<3>,IOB,IO_L31N_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
D9,,DIFFM,IO_L32P_1/GCLK4,UNUSED,,1,,,,,,,,,,
D10,ide_data_bus<2>,IOB,IO_L30N_1,BIDIR,LVTTL,1,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
D11,,DIFFS,IO_L28N_1,UNUSED,,1,,,,,,,,,,
D12,,IOB,IO/VREF_1,UNUSED,,1,,,,,,,,,,
D13,,,VCCINT,,,,,,,,1.2,,,,,
D14,,DIFFM,IO_L16P_2,UNUSED,,2,,,,,,,,,,
D14,sevenseg_an<0>,IOB,IO_L16P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
D15,,DIFFS,IO_L17N_2,UNUSED,,2,,,,,,,,,,
D16,,DIFFM,IO_L17P_2/VREF_2,UNUSED,,2,,,,,,,,,,
E1,sram2_io<12>,IOB,IO_L20N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E2,sram2_io<10>,IOB,IO_L20P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E3,sram2_io<11>,IOB,IO_L19N_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E4,sram2_io<14>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E1,sram2_io<6>,IOB,IO_L20N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
E2,sram2_io<9>,IOB,IO_L20P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
E3,sram_a<8>,IOB,IO_L19N_7/VREF_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
E4,sram_a<9>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
E5,,,VCCINT,,,,,,,,1.2,,,,,
E6,,DIFFS,IO_L27N_0,UNUSED,,0,,,,,,,,,,
E7,,DIFFS,IO_L29N_0,UNUSED,,0,,,,,,,,,,
E8,,,VCCO_0,,,0,,,,,2.50,,,,,
E9,,,VCCO_1,,,1,,,,,2.50,,,,,
E10,sram1_io<14>,IOB,IO_L30P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
E7,ide_data_bus<5>,IOB,IO_L29N_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
E8,,,VCCO_0,,,0,,,,,3.30,,,,,
E9,,,VCCO_1,,,1,,,,,3.30,,,,,
E10,,DIFFM,IO_L30P_1,UNUSED,,1,,,,,,,,,,
E11,,DIFFM,IO_L28P_1,UNUSED,,1,,,,,,,,,,
E12,,,VCCINT,,,,,,,,1.2,,,,,
E13,,DIFFS,IO_L19N_2,UNUSED,,2,,,,,,,,,,
E14,,DIFFM,IO_L19P_2,UNUSED,,2,,,,,,,,,,
E13,sevenseg_an<3>,IOB,IO_L19N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
E14,sevenseg<7>,IOB,IO_L19P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
E15,,DIFFS,IO_L20N_2,UNUSED,,2,,,,,,,,,,
E16,,DIFFM,IO_L20P_2,UNUSED,,2,,,,,,,,,,
F1,,,VCCAUX,,,,,,,,2.5,,,,,
F2,sram2_io<15>,IOB,IO_L22N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F3,sram_a<15>,IOB,IO_L22P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F4,sram2_io<13>,IOB,IO_L21N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F5,,DIFFM,IO_L23P_7,UNUSED,,7,,,,,,,,,,
F2,sram1_io<10>,IOB,IO_L22N_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
F3,sram_a<6>,IOB,IO_L22P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
F4,sram_a<7>,IOB,IO_L21N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
F5,sram2_io<11>,IOB,IO_L23P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
F6,,,GND,,,,,,,,,,,,,
F7,,,VCCO_0,,,0,,,,,2.50,,,,,
F8,,,VCCO_0,,,0,,,,,2.50,,,,,
F9,,,VCCO_1,,,1,,,,,2.50,,,,,
F10,,,VCCO_1,,,1,,,,,2.50,,,,,
F7,,,VCCO_0,,,0,,,,,3.30,,,,,
F8,,,VCCO_0,,,0,,,,,3.30,,,,,
F9,,,VCCO_1,,,1,,,,,3.30,,,,,
F10,,,VCCO_1,,,1,,,,,3.30,,,,,
F11,,,GND,,,,,,,,,,,,,
F12,,DIFFS,IO_L21N_2,UNUSED,,2,,,,,,,,,,
F13,,DIFFM,IO_L21P_2,UNUSED,,2,,,,,,,,,,
F14,,DIFFS,IO_L22N_2,UNUSED,,2,,,,,,,,,,
F12,slideswitch<0>,IOB,IO_L21N_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
F13,sevenseg<2>,IOB,IO_L21P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
F14,sevenseg_an<2>,IOB,IO_L22N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
F15,,DIFFM,IO_L22P_2,UNUSED,,2,,,,,,,,,,
F16,,,VCCAUX,,,,,,,,2.5,,,,,
G1,ide_data_bus<2>,IOB,IO_L40P_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
G2,ide_data_bus<7>,IOB,IO,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
G3,ide_diow,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G4,ide_dior,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G5,sram_a<16>,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G1,sram2_io<10>,IOB,IO_L40P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
G2,sram2_io<5>,IOB,IO,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
G3,sram_we_n,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
G4,sram_a<5>,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
G5,sram_a<10>,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
G6,,,VCCO_7,,,7,,,,,2.50,,,,,
G7,,,GND,,,,,,,,,,,,,
G8,,,GND,,,,,,,,,,,,,
G9,,,GND,,,,,,,,,,,,,
G10,,,GND,,,,,,,,,,,,,
G11,,,VCCO_2,,,2,,,,,2.50,,,,,
G12,,DIFFS,IO_L23N_2/VREF_2,UNUSED,,2,,,,,,,,,,
G13,,DIFFM,IO_L23P_2,UNUSED,,2,,,,,,,,,,
G14,,DIFFS,IO_L24N_2,UNUSED,,2,,,,,,,,,,
G15,rs232_txd,IOB,IO_L24P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
G12,slideswitch<1>,IOB,IO_L23N_2/VREF_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
G13,sevenseg<6>,IOB,IO_L23P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
G14,sevenseg_an<1>,IOB,IO_L24N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
G15,,DIFFM,IO_L24P_2,UNUSED,,2,,,,,,,,,,
G16,,DIFFM,IO,UNUSED,,2,,,,,,,,,,
H1,ide_data_bus<4>,IOB,IO_L40N_7/VREF_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
H1,sram1_io<11>,IOB,IO_L40N_7/VREF_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
H2,,,GND,,,,,,,,,,,,,
H3,ide_data_bus<5>,IOB,IO_L39N_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
H4,button<3>,IOB,IO_L39P_7,INPUT,LVCMOS25,7,,,,IFD,,,,YES,NONE,
H3,sram_a<11>,IOB,IO_L39N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
H4,sram_a<12>,IOB,IO_L39P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
H5,,,VCCO_7,,,7,,,,,2.50,,,,,
H6,,,VCCO_7,,,7,,,,,2.50,,,,,
H7,,,GND,,,,,,,,,,,,,
@@ -143,14 +143,14 @@ H9,,,GND,,,,,,,,,,,,,
H10,,,GND,,,,,,,,,,,,,
H11,,,VCCO_2,,,2,,,,,2.50,,,,,
H12,,,VCCO_2,,,2,,,,,2.50,,,,,
H13,,DIFFS,IO_L39N_2,UNUSED,,2,,,,,,,,,,
H14,sram_oe_n,IOB,IO_L39P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H15,sram_we_n,IOB,IO_L40N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H16,sram_a<7>,IOB,IO_L40P_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
J1,ide_data_bus<0>,IOB,IO_L40P_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J2,ide_data_bus<3>,IOB,IO_L40N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J3,ide_data_bus<10>,IOB,IO_L39P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J4,ide_data_bus<1>,IOB,IO_L39N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
H13,slideswitch<3>,IOB,IO_L39N_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
H14,slideswitch<2>,IOB,IO_L39P_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
H15,,DIFFS,IO_L40N_2,UNUSED,,2,,,,,,,,,,
H16,,DIFFM,IO_L40P_2/VREF_2,UNUSED,,2,,,,,,,,,,
J1,sram2_io<4>,IOB,IO_L40P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
J2,sram1_io<12>,IOB,IO_L40N_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
J3,sram_a<14>,IOB,IO_L39P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
J4,sram_a<13>,IOB,IO_L39N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
J5,,,VCCO_6,,,6,,,,,2.50,,,,,
J6,,,VCCO_6,,,6,,,,,2.50,,,,,
J7,,,GND,,,,,,,,,,,,,
@@ -159,120 +159,120 @@ J9,,,GND,,,,,,,,,,,,,
J10,,,GND,,,,,,,,,,,,,
J11,,,VCCO_3,,,3,,,,,2.50,,,,,
J12,,,VCCO_3,,,3,,,,,2.50,,,,,
J13,sram1_io<3>,IOB,IO_L39P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
J14,sram1_io<4>,IOB,IO_L39N_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
J13,slideswitch<5>,IOB,IO_L39P_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
J14,slideswitch<4>,IOB,IO_L39N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
J15,,,GND,,,,,,,,,,,,,
J16,sram_a<0>,IOB,IO_L40N_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K1,ide_data_bus<11>,IOB,IO,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
K2,ide_data_bus<9>,IOB,IO_L24P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
K3,ide_data_bus<8>,IOB,IO_L24N_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
K4,ide_cs<0>,IOB,IO_L23P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
K5,ide_data_bus<6>,IOB,IO_L23N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J16,,DIFFS,IO_L40N_3/VREF_3,UNUSED,,3,,,,,,,,,,
K1,sram2_io<3>,IOB,IO,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
K2,sram2_io<13>,IOB,IO_L24P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
K3,sram_a<15>,IOB,IO_L24N_6/VREF_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
K4,sram_oe_n,IOB,IO_L23P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
K5,sram_a<16>,IOB,IO_L23N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
K6,,,VCCO_6,,,6,,,,,2.50,,,,,
K7,,,GND,,,,,,,,,,,,,
K8,,,GND,,,,,,,,,,,,,
K9,,,GND,,,,,,,,,,,,,
K10,,,GND,,,,,,,,,,,,,
K11,,,VCCO_3,,,3,,,,,2.50,,,,,
K12,sram_a<13>,IOB,IO_L23N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K13,sram1_io<6>,IOB,IO_L24P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
K14,sram_a<14>,IOB,IO_L24N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K15,sram1_io<5>,IOB,IO,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
K16,sram_a<3>,IOB,IO_L40P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K12,led<0>,IOB,IO_L23N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
K13,slideswitch<7>,IOB,IO_L24P_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
K14,slideswitch<6>,IOB,IO_L24N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
K15,,DIFFS,IO,UNUSED,,3,,,,,,,,,,
K16,,DIFFM,IO_L40P_3,UNUSED,,3,,,,,,,,,,
L1,,,VCCAUX,,,,,,,,2.5,,,,,
L2,ide_data_bus<12>,IOB,IO_L22P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L3,ide_data_bus<14>,IOB,IO_L22N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L4,ide_data_bus<15>,IOB,IO_L21P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L5,ide_data_bus<13>,IOB,IO_L21N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L2,sram1_io<13>,IOB,IO_L22P_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
L3,sram_a<17>,IOB,IO_L22N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
L4,sram_a<4>,IOB,IO_L21P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
L5,sram_a<0>,IOB,IO_L21N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
L6,,,GND,,,,,,,,,,,,,
L7,,,VCCO_5,,,5,,,,,2.50,,,,,
L8,,,VCCO_5,,,5,,,,,2.50,,,,,
L9,,,VCCO_4,,,4,,,,,2.50,,,,,
L10,,,VCCO_4,,,4,,,,,2.50,,,,,
L11,,,GND,,,,,,,,,,,,,
L12,sram_a<10>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L13,sram_a<11>,IOB,IO_L21N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L14,sram_a<9>,IOB,IO_L22P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L15,sram_a<8>,IOB,IO_L22N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L12,led<2>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
L13,button<2>,IOB,IO_L21N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
L14,button<3>,IOB,IO_L22P_3,INPUT,LVCMOS25,3,,,,IFD,,LOCATED,,YES,NONE,
L15,,DIFFS,IO_L22N_3,UNUSED,,3,,,,,,,,,,
L16,,,VCCAUX,,,,,,,,2.5,,,,,
M1,sram2_io<6>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M2,sram2_io<5>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M3,sram2_io<4>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M4,sram2_io<3>,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M1,sram2_io<14>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
M2,sram2_io<2>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
M3,sram_a<3>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
M4,sram_a<2>,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
M5,,,VCCINT,,,,,,,,1.2,,,,,
M6,,DIFFM,IO_L28P_5/D7,UNUSED,,5,,,,,,,,,,
M7,,DIFFM,IO_L30P_5,UNUSED,,5,,,,,,,,,,
M8,,,VCCO_5,,,5,,,,,2.50,,,,,
M9,,,VCCO_4,,,4,,,,,2.50,,,,,
M10,,DIFFS,IO_L29N_4,UNUSED,,4,,,,,,,,,,
M11,sram_a<2>,IOB,IO_L27N_4/DIN/D0,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
M11,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,,,
M12,,,VCCINT,,,,,,,,1.2,,,,,
M13,sram_a<5>,IOB,IO_L21P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
M14,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,,,
M15,sram_a<12>,IOB,IO_L20P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
M16,sram_a<6>,IOB,IO_L20N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
N1,sram2_io<2>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N2,sram2_io<1>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N3,sram2_io<0>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M13,button<0>,IOB,IO_L21P_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
M14,button<1>,IOB,IO_L19N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
M15,,DIFFM,IO_L20P_3,UNUSED,,3,,,,,,,,,,
M16,,DIFFS,IO_L20N_3,UNUSED,,3,,,,,,,,,,
N1,sram2_io<15>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N2,sram2_io<1>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N3,sram_a<1>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
N4,,,VCCINT,,,,,,,,1.2,,,,,
N5,,IOB,IO,UNUSED,,5,,,,,,,,,,
N5,sram2_ce_n,IOB,IO,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N6,,DIFFS,IO_L28N_5/D6,UNUSED,,5,,,,,,,,,,
N7,,DIFFS,IO_L30N_5,UNUSED,,5,,,,,,,,,,
N8,sram1_io<0>,IOB,IO_L32P_5/GCLK2,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
N9,sram1_io<8>,IOB,IO_L31N_4/INIT_B,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
N7,sram1_io<0>,IOB,IO_L30N_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
N8,,DIFFM,IO_L32P_5/GCLK2,UNUSED,,5,,,,,,,,,,
N9,,DIFFS,IO_L31N_4/INIT_B,UNUSED,,4,,,,,,,,,,
N10,,DIFFM,IO_L29P_4,UNUSED,,4,,,,,,,,,,
N11,rs232_rxd,IOB,IO_L27P_4/D1,INPUT,LVCMOS25,4,,,,IFD,,,,YES,NONE,
N12,sram1_io<9>,IOB,IO/VREF_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
N11,,DIFFM,IO_L27P_4/D1,UNUSED,,4,,,,,,,,,,
N12,led<5>,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N13,,,VCCINT,,,,,,,,1.2,,,,,
N14,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,,,
N15,,DIFFM,IO_L17P_3/VREF_3,UNUSED,,3,,,,,,,,,,
N16,,DIFFS,IO_L17N_3,UNUSED,,3,,,,,,,,,,
P1,sram2_ce_n,IOB,IO_L01P_6/VRN_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
P2,sram1_lb_n,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N14,led<3>,IOB,IO_L19P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N15,sevenseg<5>,IOB,IO_L17P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
N16,sevenseg<1>,IOB,IO_L17N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P1,sram1_io<14>,IOB,IO_L01P_6/VRN_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
P2,sram2_io<0>,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P3,,,M0,,,,,,,,,,,,,
P4,,,M2,,,,,,,,,,,,,
P5,ide_cs<1>,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
P6,,DIFFM,IO_L29P_5/VREF_5,UNUSED,,5,,,,,,,,,,
P7,,IOB,IO,UNUSED,,5,,,,,,,,,,
P8,sram1_io<1>,IOB,IO_L32N_5/GCLK3,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
P9,sram_a<4>,IOB,IO_L31P_4/DOUT/BUSY,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
P5,sram2_lb_n,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P6,sram1_lb_n,IOB,IO_L29P_5/VREF_5,OUTPUT,LVCMOS25,5,12,FAST,NONE**,,,LOCATED,,NO,NONE,
P7,sram1_ce_n,IOB,IO,OUTPUT,LVCMOS25,5,12,FAST,NONE**,,,LOCATED,,NO,NONE,
P8,sram1_io<9>,IOB,IO_L32N_5/GCLK3,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
P9,,DIFFM,IO_L31P_4/DOUT/BUSY,UNUSED,,4,,,,,,,,,,
P10,,DIFFS,IO_L30N_4/D2,UNUSED,,4,,,,,,,,,,
P11,,DIFFS,IO_L28N_4,UNUSED,,4,,,,,,,,,,
P12,,DIFFS,IO_L25N_4,UNUSED,,4,,,,,,,,,,
P13,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,,
P14,,DIFFM,IO_L16P_3,UNUSED,,3,,,,,,,,,,
P15,,DIFFS,IO_L16N_3,UNUSED,,3,,,,,,,,,,
P16,,DIFFS,IO_L01N_3/VRP_3,UNUSED,,3,,,,,,,,,,
R1,,DIFFS,IO_L01N_6/VRP_6,UNUSED,,6,,,,,,,,,,
P11,led<7>,IOB,IO_L28N_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P12,led<6>,IOB,IO_L25N_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P13,led<4>,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P14,led<1>,IOB,IO_L16P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P15,sevenseg<4>,IOB,IO_L16N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
P16,sevenseg<0>,IOB,IO_L01N_3/VRP_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
R1,sram1_io<15>,IOB,IO_L01N_6/VRP_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
R2,,,GND,,,,,,,,,,,,,
R3,,DIFFM,IO_L01P_5/CS_B,UNUSED,,5,,,,,,,,,,
R4,sram2_io<7>,IOB,IO_L10P_5/VRN_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
R5,ide_da<1>,IOB,IO_L27N_5/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
R6,,DIFFS,IO_L29N_5,UNUSED,,5,,,,,,,,,,
R4,sram2_ub_n,IOB,IO_L10P_5/VRN_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
R5,sram1_io<4>,IOB,IO_L27N_5/VREF_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
R6,sram1_io<2>,IOB,IO_L29N_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
R7,,DIFFM,IO_L31P_5/D5,UNUSED,,5,,,,,,,,,,
R8,,,GND,,,,,,,,,,,,,
R9,sram1_io<11>,IOB,IO_L32N_4/GCLK1,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
R9,,DIFFS,IO_L32N_4/GCLK1,UNUSED,,4,,,,,,,,,,
R10,,DIFFM,IO_L30P_4/D3,UNUSED,,4,,,,,,,,,,
R11,,DIFFM,IO_L28P_4,UNUSED,,4,,,,,,,,,,
R12,,DIFFM,IO_L25P_4,UNUSED,,4,,,,,,,,,,
R13,,DIFFS,IO_L01N_4/VRP_4,UNUSED,,4,,,,,,,,,,
R13,rs232_txd,IOB,IO_L01N_4/VRP_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
R14,,,DONE,,,,,,,,,,,,,
R15,,,GND,,,,,,,,,,,,,
R16,,DIFFM,IO_L01P_3/VRN_3,UNUSED,,3,,,,,,,,,,
R16,sevenseg<3>,IOB,IO_L01P_3/VRN_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
T1,,,GND,,,,,,,,,,,,,
T2,,,M1,,,,,,,,,,,,,
T3,,DIFFS,IO_L01N_5/RDWR_B,UNUSED,,5,,,,,,,,,,
T4,,DIFFS,IO_L10N_5/VRP_5,UNUSED,,5,,,,,,,,,,
T5,ide_da<2>,IOB,IO,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
T4,sram1_ub_n,IOB,IO_L10N_5/VRP_5,OUTPUT,LVCMOS25,5,12,FAST,NONE**,,,LOCATED,,NO,NONE,
T5,sram1_io<3>,IOB,IO,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
T6,,,VCCAUX,,,,,,,,2.5,,,,,
T7,,DIFFS,IO_L31N_5/D4,UNUSED,,5,,,,,,,,,,
T8,sram1_io<2>,IOB,IO/VREF_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
T9,sram1_io<7>,IOB,IO_L32P_4/GCLK0,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
T10,sram1_ce_n,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
T8,sram1_io<1>,IOB,IO/VREF_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
T9,sysclk,IOB,IO_L32P_4/GCLK0,INPUT,LVCMOS25,4,,,,NONE,,LOCATED,,NO,NONE,
T10,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,,
T11,,,VCCAUX,,,,,,,,2.5,,,,,
T12,sram_a<1>,IOB,IO,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
T13,,DIFFM,IO_L01P_4/VRN_4,UNUSED,,4,,,,,,,,,,
T14,sram1_io<10>,IOB,IO,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
T12,,IOB,IO,UNUSED,,4,,,,,,,,,,
T13,rs232_rxd,IOB,IO_L01P_4/VRN_4,INPUT,LVCMOS25,4,,,,IFD,,LOCATED,,YES,NONE,
T14,,DIFFS,IO,UNUSED,,4,,,,,,,,,,
T15,,,CCLK,,,,,,,,,,,,,
T16,,,GND,,,,,,,,,,,,,
1 #Release 8.2i - par I.31 #Release 8.2.03i - par I.34
2 #Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
3 #Fri Apr 16 08:17:39 2010 #Fri Apr 23 22:48:26 2010
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
21 A2,,,TDI,,,,,,,,,,,,,
22 A3,slideswitch<1>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE, A3,ide_data_bus<13>,IOB,IO/VREF_0,TRISTATE,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
23 A4,,DIFFM,IO_L01P_0/VRN_0,UNUSED,,0,,,,,,,,,, A4,ide_data_bus<14>,IOB,IO_L01P_0/VRN_0,TRISTATE,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
24 A5,,IOB,IO,UNUSED,,0,,,,,,,,,, A5,ide_data_bus<15>,IOB,IO,TRISTATE,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
25 A6,,,VCCAUX,,,,,,,,2.5,,,,,
26 A7,,IOB,IO,UNUSED,,0,,,,,,,,,,
27 A8,,DIFFM,IO_L32P_0/GCLK6,UNUSED,,0,,,,,,,,,, A8,ide_diow,IOB,IO_L32P_0/GCLK6,OUTPUT,LVTTL,0,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
28 A9,,IOB,IO,UNUSED,,1,,,,,,,,,, A9,ide_cs<0>,IOB,IO,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
29 A10,,DIFFS,IO_L31N_1/VREF_1,UNUSED,,1,,,,,,,,,, A10,ide_cs<1>,IOB,IO_L31N_1/VREF_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
30 A11,,,VCCAUX,,,,,,,,2.5,,,,,
31 A12,,IOB,IO,UNUSED,,1,,,,,,,,,,
32 A13,,DIFFS,IO_L10N_1/VREF_1,UNUSED,,1,,,,,,,,,,
33 A14,,DIFFS,IO_L01N_1/VRP_1,UNUSED,,1,,,,,,,,,,
34 A15,,,TDO,,,,,,,,,,,,,
35 A16,,,GND,,,,,,,,,,,,,
36 B1,,DIFFM,IO_L01P_7/VRN_7,UNUSED,,7,,,,,,,,,, B1,sram1_io<7>,IOB,IO_L01P_7/VRN_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
37 B2,,,GND,,,,,,,,,,,,,
38 B3,,,PROG_B,,,,,,,,,,,,,
39 B4,,DIFFS,IO_L01N_0/VRP_0,UNUSED,,0,,,,,,,,,, B4,ide_data_bus<1>,IOB,IO_L01N_0/VRP_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
40 B5,ide_da<0>,IOB,IO_L25P_0,OUTPUT,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE, B5,ide_data_bus<0>,IOB,IO_L25P_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
41 B6,,DIFFM,IO_L28P_0,UNUSED,,0,,,,,,,,,,
42 B7,,DIFFM,IO_L30P_0,UNUSED,,0,,,,,,,,,,
43 B8,,DIFFS,IO_L32N_0/GCLK7,UNUSED,,0,,,,,,,,,,
44 B9,,,GND,,,,,,,,,,,,,
45 B10,sram1_io<15>,IOB,IO_L31P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, B10,ide_dior,IOB,IO_L31P_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
46 B11,sram1_io<12>,IOB,IO_L29N_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, B11,,DIFFS,IO_L29N_1,UNUSED,,1,,,,,,,,,,
47 B12,,DIFFS,IO_L27N_1,UNUSED,,1,,,,,,,,,, B12,ide_da<0>,IOB,IO_L27N_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
48 B13,,DIFFM,IO_L10P_1,UNUSED,,1,,,,,,,,,, B13,ide_da<1>,IOB,IO_L10P_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
49 B14,,DIFFM,IO_L01P_1/VRN_1,UNUSED,,1,,,,,,,,,, B14,ide_da<2>,IOB,IO_L01P_1/VRN_1,OUTPUT,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
50 B15,,,GND,,,,,,,,,,,,,
51 B16,,DIFFS,IO_L01N_2/VRP_2,UNUSED,,2,,,,,,,,,,
52 C1,,DIFFS,IO_L01N_7/VRP_7,UNUSED,,7,,,,,,,,,, C1,sram1_io<6>,IOB,IO_L01N_7/VRP_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
53 C2,sram2_io<9>,IOB,IO_L16N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, C2,sram1_io<5>,IOB,IO_L16N_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
54 C3,sram2_lb_n,IOB,IO_L16P_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, C3,sram2_io<12>,IOB,IO_L16P_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
55 C4,,,HSWAP_EN,,,,,,,,,,,,,
56 C5,slideswitch<3>,IOB,IO_L25N_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE, C5,ide_data_bus<8>,IOB,IO_L25N_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
57 C6,,DIFFS,IO_L28N_0,UNUSED,,0,,,,,,,,,, C6,ide_data_bus<9>,IOB,IO_L28N_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
58 C7,,DIFFS,IO_L30N_0,UNUSED,,0,,,,,,,,,, C7,ide_data_bus<10>,IOB,IO_L30N_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
59 C8,,DIFFM,IO_L31P_0/VREF_0,UNUSED,,0,,,,,,,,,, C8,ide_data_bus<11>,IOB,IO_L31P_0/VREF_0,BIDIR,LVTTL,0,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
60 C9,sysclk,IOB,IO_L32N_1/GCLK5,INPUT,LVCMOS25,1,,,,NONE,,,,NO,NONE, C9,ide_data_bus<12>,IOB,IO_L32N_1/GCLK5,TRISTATE,LVTTL,1,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
61 C10,,IOB,IO,UNUSED,,1,,,,,,,,,,
62 C11,sram1_io<13>,IOB,IO_L29P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, C11,,DIFFM,IO_L29P_1,UNUSED,,1,,,,,,,,,,
63 C12,,DIFFM,IO_L27P_1,UNUSED,,1,,,,,,,,,,
64 C13,,,TMS,,,,,,,,,,,,,
65 C14,,,TCK,,,,,,,,,,,,,
66 C15,,DIFFS,IO_L16N_2,UNUSED,,2,,,,,,,,,,
67 C16,,DIFFM,IO_L01P_2/VRN_2,UNUSED,,2,,,,,,,,,,
68 D1,sram2_ub_n,IOB,IO_L17N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, D1,sram2_io<7>,IOB,IO_L17N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
69 D2,sram2_io<8>,IOB,IO_L17P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, D2,sram2_io<8>,IOB,IO_L17P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
70 D3,sram1_ub_n,IOB,IO_L19P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, D3,sram1_io<8>,IOB,IO_L19P_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
71 D4,,,VCCINT,,,,,,,,1.2,,,,,
72 D5,slideswitch<0>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE, D5,ide_data_bus<7>,IOB,IO/VREF_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
73 D6,slideswitch<2>,IOB,IO_L27P_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE, D6,ide_data_bus<6>,IOB,IO_L27P_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
74 D7,,DIFFM,IO_L29P_0,UNUSED,,0,,,,,,,,,, D7,ide_data_bus<4>,IOB,IO_L29P_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
75 D8,,DIFFS,IO_L31N_0,UNUSED,,0,,,,,,,,,, D8,ide_data_bus<3>,IOB,IO_L31N_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
76 D9,sram_a<17>,IOB,IO_L32P_1/GCLK4,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, D9,,DIFFM,IO_L32P_1/GCLK4,UNUSED,,1,,,,,,,,,,
77 D10,,DIFFS,IO_L30N_1,UNUSED,,1,,,,,,,,,, D10,ide_data_bus<2>,IOB,IO_L30N_1,BIDIR,LVTTL,1,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
78 D11,,DIFFS,IO_L28N_1,UNUSED,,1,,,,,,,,,,
79 D12,,IOB,IO/VREF_1,UNUSED,,1,,,,,,,,,,
80 D13,,,VCCINT,,,,,,,,1.2,,,,,
81 D14,,DIFFM,IO_L16P_2,UNUSED,,2,,,,,,,,,, D14,sevenseg_an<0>,IOB,IO_L16P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
82 D15,,DIFFS,IO_L17N_2,UNUSED,,2,,,,,,,,,,
83 D16,,DIFFM,IO_L17P_2/VREF_2,UNUSED,,2,,,,,,,,,,
84 E1,sram2_io<12>,IOB,IO_L20N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, E1,sram2_io<6>,IOB,IO_L20N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
85 E2,sram2_io<10>,IOB,IO_L20P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, E2,sram2_io<9>,IOB,IO_L20P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
86 E3,sram2_io<11>,IOB,IO_L19N_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, E3,sram_a<8>,IOB,IO_L19N_7/VREF_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
87 E4,sram2_io<14>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, E4,sram_a<9>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
88 E5,,,VCCINT,,,,,,,,1.2,,,,,
89 E6,,DIFFS,IO_L27N_0,UNUSED,,0,,,,,,,,,,
90 E7,,DIFFS,IO_L29N_0,UNUSED,,0,,,,,,,,,, E7,ide_data_bus<5>,IOB,IO_L29N_0,BIDIR,LVTTL,0,24,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
91 E8,,,VCCO_0,,,0,,,,,2.50,,,,, E8,,,VCCO_0,,,0,,,,,3.30,,,,,
92 E9,,,VCCO_1,,,1,,,,,2.50,,,,, E9,,,VCCO_1,,,1,,,,,3.30,,,,,
93 E10,sram1_io<14>,IOB,IO_L30P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, E10,,DIFFM,IO_L30P_1,UNUSED,,1,,,,,,,,,,
94 E11,,DIFFM,IO_L28P_1,UNUSED,,1,,,,,,,,,,
95 E12,,,VCCINT,,,,,,,,1.2,,,,,
96 E13,,DIFFS,IO_L19N_2,UNUSED,,2,,,,,,,,,, E13,sevenseg_an<3>,IOB,IO_L19N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
97 E14,,DIFFM,IO_L19P_2,UNUSED,,2,,,,,,,,,, E14,sevenseg<7>,IOB,IO_L19P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
98 E15,,DIFFS,IO_L20N_2,UNUSED,,2,,,,,,,,,,
99 E16,,DIFFM,IO_L20P_2,UNUSED,,2,,,,,,,,,,
100 F1,,,VCCAUX,,,,,,,,2.5,,,,,
101 F2,sram2_io<15>,IOB,IO_L22N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, F2,sram1_io<10>,IOB,IO_L22N_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
102 F3,sram_a<15>,IOB,IO_L22P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, F3,sram_a<6>,IOB,IO_L22P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
103 F4,sram2_io<13>,IOB,IO_L21N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, F4,sram_a<7>,IOB,IO_L21N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
104 F5,,DIFFM,IO_L23P_7,UNUSED,,7,,,,,,,,,, F5,sram2_io<11>,IOB,IO_L23P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
105 F6,,,GND,,,,,,,,,,,,,
106 F7,,,VCCO_0,,,0,,,,,2.50,,,,, F7,,,VCCO_0,,,0,,,,,3.30,,,,,
107 F8,,,VCCO_0,,,0,,,,,2.50,,,,, F8,,,VCCO_0,,,0,,,,,3.30,,,,,
108 F9,,,VCCO_1,,,1,,,,,2.50,,,,, F9,,,VCCO_1,,,1,,,,,3.30,,,,,
109 F10,,,VCCO_1,,,1,,,,,2.50,,,,, F10,,,VCCO_1,,,1,,,,,3.30,,,,,
110 F11,,,GND,,,,,,,,,,,,,
111 F12,,DIFFS,IO_L21N_2,UNUSED,,2,,,,,,,,,, F12,slideswitch<0>,IOB,IO_L21N_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
112 F13,,DIFFM,IO_L21P_2,UNUSED,,2,,,,,,,,,, F13,sevenseg<2>,IOB,IO_L21P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
113 F14,,DIFFS,IO_L22N_2,UNUSED,,2,,,,,,,,,, F14,sevenseg_an<2>,IOB,IO_L22N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
114 F15,,DIFFM,IO_L22P_2,UNUSED,,2,,,,,,,,,,
115 F16,,,VCCAUX,,,,,,,,2.5,,,,,
116 G1,ide_data_bus<2>,IOB,IO_L40P_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE, G1,sram2_io<10>,IOB,IO_L40P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
117 G2,ide_data_bus<7>,IOB,IO,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE, G2,sram2_io<5>,IOB,IO,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
118 G3,ide_diow,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, G3,sram_we_n,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
119 G4,ide_dior,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, G4,sram_a<5>,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
120 G5,sram_a<16>,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, G5,sram_a<10>,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
121 G6,,,VCCO_7,,,7,,,,,2.50,,,,,
122 G7,,,GND,,,,,,,,,,,,,
123 G8,,,GND,,,,,,,,,,,,,
124 G9,,,GND,,,,,,,,,,,,,
125 G10,,,GND,,,,,,,,,,,,,
126 G11,,,VCCO_2,,,2,,,,,2.50,,,,,
127 G12,,DIFFS,IO_L23N_2/VREF_2,UNUSED,,2,,,,,,,,,, G12,slideswitch<1>,IOB,IO_L23N_2/VREF_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
128 G13,,DIFFM,IO_L23P_2,UNUSED,,2,,,,,,,,,, G13,sevenseg<6>,IOB,IO_L23P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
129 G14,,DIFFS,IO_L24N_2,UNUSED,,2,,,,,,,,,, G14,sevenseg_an<1>,IOB,IO_L24N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
130 G15,rs232_txd,IOB,IO_L24P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, G15,,DIFFM,IO_L24P_2,UNUSED,,2,,,,,,,,,,
131 G16,,DIFFM,IO,UNUSED,,2,,,,,,,,,,
132 H1,ide_data_bus<4>,IOB,IO_L40N_7/VREF_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE, H1,sram1_io<11>,IOB,IO_L40N_7/VREF_7,BIDIR,LVCMOS25,7,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
133 H2,,,GND,,,,,,,,,,,,,
134 H3,ide_data_bus<5>,IOB,IO_L39N_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE, H3,sram_a<11>,IOB,IO_L39N_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
135 H4,button<3>,IOB,IO_L39P_7,INPUT,LVCMOS25,7,,,,IFD,,,,YES,NONE, H4,sram_a<12>,IOB,IO_L39P_7,OUTPUT,LVCMOS25,7,12,FAST,NONE**,,,LOCATED,,NO,NONE,
136 H5,,,VCCO_7,,,7,,,,,2.50,,,,,
137 H6,,,VCCO_7,,,7,,,,,2.50,,,,,
138 H7,,,GND,,,,,,,,,,,,,
139 H8,,,GND,,,,,,,,,,,,,
140 H9,,,GND,,,,,,,,,,,,,
143 H12,,,VCCO_2,,,2,,,,,2.50,,,,,
144 H13,,DIFFS,IO_L39N_2,UNUSED,,2,,,,,,,,,, H13,slideswitch<3>,IOB,IO_L39N_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
145 H14,sram_oe_n,IOB,IO_L39P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, H14,slideswitch<2>,IOB,IO_L39P_2,INPUT,LVCMOS25,2,,,,NONE,,LOCATED,,NO,NONE,
146 H15,sram_we_n,IOB,IO_L40N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, H15,,DIFFS,IO_L40N_2,UNUSED,,2,,,,,,,,,,
147 H16,sram_a<7>,IOB,IO_L40P_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, H16,,DIFFM,IO_L40P_2/VREF_2,UNUSED,,2,,,,,,,,,,
148 J1,ide_data_bus<0>,IOB,IO_L40P_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, J1,sram2_io<4>,IOB,IO_L40P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
149 J2,ide_data_bus<3>,IOB,IO_L40N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, J2,sram1_io<12>,IOB,IO_L40N_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
150 J3,ide_data_bus<10>,IOB,IO_L39P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, J3,sram_a<14>,IOB,IO_L39P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
151 J4,ide_data_bus<1>,IOB,IO_L39N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, J4,sram_a<13>,IOB,IO_L39N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
152 J5,,,VCCO_6,,,6,,,,,2.50,,,,,
153 J6,,,VCCO_6,,,6,,,,,2.50,,,,,
154 J7,,,GND,,,,,,,,,,,,,
155 J8,,,GND,,,,,,,,,,,,,
156 J9,,,GND,,,,,,,,,,,,,
159 J12,,,VCCO_3,,,3,,,,,2.50,,,,,
160 J13,sram1_io<3>,IOB,IO_L39P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE, J13,slideswitch<5>,IOB,IO_L39P_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
161 J14,sram1_io<4>,IOB,IO_L39N_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE, J14,slideswitch<4>,IOB,IO_L39N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
162 J15,,,GND,,,,,,,,,,,,,
163 J16,sram_a<0>,IOB,IO_L40N_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, J16,,DIFFS,IO_L40N_3/VREF_3,UNUSED,,3,,,,,,,,,,
164 K1,ide_data_bus<11>,IOB,IO,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, K1,sram2_io<3>,IOB,IO,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
165 K2,ide_data_bus<9>,IOB,IO_L24P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, K2,sram2_io<13>,IOB,IO_L24P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
166 K3,ide_data_bus<8>,IOB,IO_L24N_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, K3,sram_a<15>,IOB,IO_L24N_6/VREF_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
167 K4,ide_cs<0>,IOB,IO_L23P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, K4,sram_oe_n,IOB,IO_L23P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
168 K5,ide_data_bus<6>,IOB,IO_L23N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE, K5,sram_a<16>,IOB,IO_L23N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
169 K6,,,VCCO_6,,,6,,,,,2.50,,,,,
170 K7,,,GND,,,,,,,,,,,,,
171 K8,,,GND,,,,,,,,,,,,,
172 K9,,,GND,,,,,,,,,,,,,
173 K10,,,GND,,,,,,,,,,,,,
174 K11,,,VCCO_3,,,3,,,,,2.50,,,,,
175 K12,sram_a<13>,IOB,IO_L23N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, K12,led<0>,IOB,IO_L23N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
176 K13,sram1_io<6>,IOB,IO_L24P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE, K13,slideswitch<7>,IOB,IO_L24P_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
177 K14,sram_a<14>,IOB,IO_L24N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, K14,slideswitch<6>,IOB,IO_L24N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
178 K15,sram1_io<5>,IOB,IO,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE, K15,,DIFFS,IO,UNUSED,,3,,,,,,,,,,
179 K16,sram_a<3>,IOB,IO_L40P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, K16,,DIFFM,IO_L40P_3,UNUSED,,3,,,,,,,,,,
180 L1,,,VCCAUX,,,,,,,,2.5,,,,,
181 L2,ide_data_bus<12>,IOB,IO_L22P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L2,sram1_io<13>,IOB,IO_L22P_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
182 L3,ide_data_bus<14>,IOB,IO_L22N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L3,sram_a<17>,IOB,IO_L22N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
183 L4,ide_data_bus<15>,IOB,IO_L21P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L4,sram_a<4>,IOB,IO_L21P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
184 L5,ide_data_bus<13>,IOB,IO_L21N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L5,sram_a<0>,IOB,IO_L21N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
185 L6,,,GND,,,,,,,,,,,,,
186 L7,,,VCCO_5,,,5,,,,,2.50,,,,,
187 L8,,,VCCO_5,,,5,,,,,2.50,,,,,
188 L9,,,VCCO_4,,,4,,,,,2.50,,,,,
189 L10,,,VCCO_4,,,4,,,,,2.50,,,,,
190 L11,,,GND,,,,,,,,,,,,,
191 L12,sram_a<10>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, L12,led<2>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
192 L13,sram_a<11>,IOB,IO_L21N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, L13,button<2>,IOB,IO_L21N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
193 L14,sram_a<9>,IOB,IO_L22P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, L14,button<3>,IOB,IO_L22P_3,INPUT,LVCMOS25,3,,,,IFD,,LOCATED,,YES,NONE,
194 L15,sram_a<8>,IOB,IO_L22N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, L15,,DIFFS,IO_L22N_3,UNUSED,,3,,,,,,,,,,
195 L16,,,VCCAUX,,,,,,,,2.5,,,,,
196 M1,sram2_io<6>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M1,sram2_io<14>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
197 M2,sram2_io<5>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M2,sram2_io<2>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
198 M3,sram2_io<4>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M3,sram_a<3>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
199 M4,sram2_io<3>,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M4,sram_a<2>,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
200 M5,,,VCCINT,,,,,,,,1.2,,,,,
201 M6,,DIFFM,IO_L28P_5/D7,UNUSED,,5,,,,,,,,,,
202 M7,,DIFFM,IO_L30P_5,UNUSED,,5,,,,,,,,,,
203 M8,,,VCCO_5,,,5,,,,,2.50,,,,,
204 M9,,,VCCO_4,,,4,,,,,2.50,,,,,
205 M10,,DIFFS,IO_L29N_4,UNUSED,,4,,,,,,,,,,
206 M11,sram_a<2>,IOB,IO_L27N_4/DIN/D0,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE, M11,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,,,
207 M12,,,VCCINT,,,,,,,,1.2,,,,,
208 M13,sram_a<5>,IOB,IO_L21P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, M13,button<0>,IOB,IO_L21P_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
209 M14,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,,, M14,button<1>,IOB,IO_L19N_3,INPUT,LVCMOS25,3,,,,NONE,,LOCATED,,NO,NONE,
210 M15,sram_a<12>,IOB,IO_L20P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, M15,,DIFFM,IO_L20P_3,UNUSED,,3,,,,,,,,,,
211 M16,sram_a<6>,IOB,IO_L20N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, M16,,DIFFS,IO_L20N_3,UNUSED,,3,,,,,,,,,,
212 N1,sram2_io<2>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, N1,sram2_io<15>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
213 N2,sram2_io<1>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, N2,sram2_io<1>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
214 N3,sram2_io<0>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, N3,sram_a<1>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
215 N4,,,VCCINT,,,,,,,,1.2,,,,,
216 N5,,IOB,IO,UNUSED,,5,,,,,,,,,, N5,sram2_ce_n,IOB,IO,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
217 N6,,DIFFS,IO_L28N_5/D6,UNUSED,,5,,,,,,,,,,
218 N7,,DIFFS,IO_L30N_5,UNUSED,,5,,,,,,,,,, N7,sram1_io<0>,IOB,IO_L30N_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
219 N8,sram1_io<0>,IOB,IO_L32P_5/GCLK2,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE, N8,,DIFFM,IO_L32P_5/GCLK2,UNUSED,,5,,,,,,,,,,
220 N9,sram1_io<8>,IOB,IO_L31N_4/INIT_B,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE, N9,,DIFFS,IO_L31N_4/INIT_B,UNUSED,,4,,,,,,,,,,
221 N10,,DIFFM,IO_L29P_4,UNUSED,,4,,,,,,,,,,
222 N11,rs232_rxd,IOB,IO_L27P_4/D1,INPUT,LVCMOS25,4,,,,IFD,,,,YES,NONE, N11,,DIFFM,IO_L27P_4/D1,UNUSED,,4,,,,,,,,,,
223 N12,sram1_io<9>,IOB,IO/VREF_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE, N12,led<5>,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
224 N13,,,VCCINT,,,,,,,,1.2,,,,,
225 N14,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,,, N14,led<3>,IOB,IO_L19P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
226 N15,,DIFFM,IO_L17P_3/VREF_3,UNUSED,,3,,,,,,,,,, N15,sevenseg<5>,IOB,IO_L17P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
227 N16,,DIFFS,IO_L17N_3,UNUSED,,3,,,,,,,,,, N16,sevenseg<1>,IOB,IO_L17N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
228 P1,sram2_ce_n,IOB,IO_L01P_6/VRN_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, P1,sram1_io<14>,IOB,IO_L01P_6/VRN_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
229 P2,sram1_lb_n,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, P2,sram2_io<0>,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
230 P3,,,M0,,,,,,,,,,,,,
231 P4,,,M2,,,,,,,,,,,,,
232 P5,ide_cs<1>,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, P5,sram2_lb_n,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
233 P6,,DIFFM,IO_L29P_5/VREF_5,UNUSED,,5,,,,,,,,,, P6,sram1_lb_n,IOB,IO_L29P_5/VREF_5,OUTPUT,LVCMOS25,5,12,FAST,NONE**,,,LOCATED,,NO,NONE,
234 P7,,IOB,IO,UNUSED,,5,,,,,,,,,, P7,sram1_ce_n,IOB,IO,OUTPUT,LVCMOS25,5,12,FAST,NONE**,,,LOCATED,,NO,NONE,
235 P8,sram1_io<1>,IOB,IO_L32N_5/GCLK3,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE, P8,sram1_io<9>,IOB,IO_L32N_5/GCLK3,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
236 P9,sram_a<4>,IOB,IO_L31P_4/DOUT/BUSY,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE, P9,,DIFFM,IO_L31P_4/DOUT/BUSY,UNUSED,,4,,,,,,,,,,
237 P10,,DIFFS,IO_L30N_4/D2,UNUSED,,4,,,,,,,,,,
238 P11,,DIFFS,IO_L28N_4,UNUSED,,4,,,,,,,,,, P11,led<7>,IOB,IO_L28N_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
239 P12,,DIFFS,IO_L25N_4,UNUSED,,4,,,,,,,,,, P12,led<6>,IOB,IO_L25N_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
240 P13,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,, P13,led<4>,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
241 P14,,DIFFM,IO_L16P_3,UNUSED,,3,,,,,,,,,, P14,led<1>,IOB,IO_L16P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
242 P15,,DIFFS,IO_L16N_3,UNUSED,,3,,,,,,,,,, P15,sevenseg<4>,IOB,IO_L16N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
243 P16,,DIFFS,IO_L01N_3/VRP_3,UNUSED,,3,,,,,,,,,, P16,sevenseg<0>,IOB,IO_L01N_3/VRP_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
244 R1,,DIFFS,IO_L01N_6/VRP_6,UNUSED,,6,,,,,,,,,, R1,sram1_io<15>,IOB,IO_L01N_6/VRP_6,TRISTATE,LVCMOS25,6,12,FAST,NONE**,,,LOCATED,,NO,NONE,
245 R2,,,GND,,,,,,,,,,,,,
246 R3,,DIFFM,IO_L01P_5/CS_B,UNUSED,,5,,,,,,,,,,
247 R4,sram2_io<7>,IOB,IO_L10P_5/VRN_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, R4,sram2_ub_n,IOB,IO_L10P_5/VRN_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
248 R5,ide_da<1>,IOB,IO_L27N_5/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, R5,sram1_io<4>,IOB,IO_L27N_5/VREF_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
249 R6,,DIFFS,IO_L29N_5,UNUSED,,5,,,,,,,,,, R6,sram1_io<2>,IOB,IO_L29N_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
250 R7,,DIFFM,IO_L31P_5/D5,UNUSED,,5,,,,,,,,,,
251 R8,,,GND,,,,,,,,,,,,,
252 R9,sram1_io<11>,IOB,IO_L32N_4/GCLK1,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE, R9,,DIFFS,IO_L32N_4/GCLK1,UNUSED,,4,,,,,,,,,,
253 R10,,DIFFM,IO_L30P_4/D3,UNUSED,,4,,,,,,,,,,
254 R11,,DIFFM,IO_L28P_4,UNUSED,,4,,,,,,,,,,
255 R12,,DIFFM,IO_L25P_4,UNUSED,,4,,,,,,,,,,
256 R13,,DIFFS,IO_L01N_4/VRP_4,UNUSED,,4,,,,,,,,,, R13,rs232_txd,IOB,IO_L01N_4/VRP_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
257 R14,,,DONE,,,,,,,,,,,,,
258 R15,,,GND,,,,,,,,,,,,,
259 R16,,DIFFM,IO_L01P_3/VRN_3,UNUSED,,3,,,,,,,,,, R16,sevenseg<3>,IOB,IO_L01P_3/VRN_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE,
260 T1,,,GND,,,,,,,,,,,,,
261 T2,,,M1,,,,,,,,,,,,,
262 T3,,DIFFS,IO_L01N_5/RDWR_B,UNUSED,,5,,,,,,,,,,
263 T4,,DIFFS,IO_L10N_5/VRP_5,UNUSED,,5,,,,,,,,,, T4,sram1_ub_n,IOB,IO_L10N_5/VRP_5,OUTPUT,LVCMOS25,5,12,FAST,NONE**,,,LOCATED,,NO,NONE,
264 T5,ide_da<2>,IOB,IO,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, T5,sram1_io<3>,IOB,IO,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
265 T6,,,VCCAUX,,,,,,,,2.5,,,,,
266 T7,,DIFFS,IO_L31N_5/D4,UNUSED,,5,,,,,,,,,,
267 T8,sram1_io<2>,IOB,IO/VREF_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE, T8,sram1_io<1>,IOB,IO/VREF_5,BIDIR,LVCMOS25,5,12,FAST,NONE**,NONE,,LOCATED,,NO,NONE,
268 T9,sram1_io<7>,IOB,IO_L32P_4/GCLK0,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE, T9,sysclk,IOB,IO_L32P_4/GCLK0,INPUT,LVCMOS25,4,,,,NONE,,LOCATED,,NO,NONE,
269 T10,sram1_ce_n,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE, T10,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,,
270 T11,,,VCCAUX,,,,,,,,2.5,,,,,
271 T12,sram_a<1>,IOB,IO,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE, T12,,IOB,IO,UNUSED,,4,,,,,,,,,,
272 T13,,DIFFM,IO_L01P_4/VRN_4,UNUSED,,4,,,,,,,,,, T13,rs232_rxd,IOB,IO_L01P_4/VRN_4,INPUT,LVCMOS25,4,,,,IFD,,LOCATED,,YES,NONE,
273 T14,sram1_io<10>,IOB,IO,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE, T14,,DIFFS,IO,UNUSED,,4,,,,,,,,,,
274 T15,,,CCLK,,,,,,,,,,,,,
275 T16,,,GND,,,,,,,,,,,,,
276 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
277 #
278 #* Default value.

292
xilinx/pdp8/top_pad.txt
View File

@@ -1,7 +1,7 @@
Release 8.2i - par I.31
Release 8.2.03i - par I.34
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Fri Apr 16 08:17:40 2010
Fri Apr 23 22:48:26 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@@ -22,120 +22,120 @@ Pinout by Pin Number:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | | |
|A2 | | |TDI | | | | | | | | | | | | |
|A3 |slideswitch<1> |IOB |IO/VREF_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|A4 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | | |
|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A3 |ide_data_bus<13>|IOB |IO/VREF_0 |TRISTATE |LVTTL |0 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|A4 |ide_data_bus<14>|IOB |IO_L01P_0/VRN_0 |TRISTATE |LVTTL |0 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|A5 |ide_data_bus<15>|IOB |IO |TRISTATE |LVTTL |0 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|A6 | | |VCCAUX | | | | | | | |2.5 | | | | |
|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A8 | |DIFFM |IO_L32P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |
|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A10 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | | |
|A8 |ide_diow |IOB |IO_L32P_0/GCLK6 |OUTPUT |LVTTL |0 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|A9 |ide_cs<0> |IOB |IO |OUTPUT |LVTTL |1 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|A10 |ide_cs<1> |IOB |IO_L31N_1/VREF_1 |OUTPUT |LVTTL |1 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|A11 | | |VCCAUX | | | | | | | |2.5 | | | | |
|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | | |
|A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | | |
|A15 | | |TDO | | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | | |
|B1 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | | |
|B1 |sram1_io<7> |IOB |IO_L01P_7/VRN_7 |BIDIR |LVCMOS25 |7 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|B2 | | |GND | | | | | | | | | | | | |
|B3 | | |PROG_B | | | | | | | | | | | | |
|B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | | |
|B5 |ide_da<0> |IOB |IO_L25P_0 |OUTPUT |LVCMOS25 |0 |12 |SLOW |NONE** | | | | |NO |NONE |
|B4 |ide_data_bus<1> |IOB |IO_L01N_0/VRP_0 |BIDIR |LVTTL |0 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|B5 |ide_data_bus<0> |IOB |IO_L25P_0 |BIDIR |LVTTL |0 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|B6 | |DIFFM |IO_L28P_0 |UNUSED | |0 | | | | | | | | | |
|B7 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | | |
|B8 | |DIFFS |IO_L32N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |
|B9 | | |GND | | | | | | | | | | | | |
|B10 |sram1_io<15> |IOB |IO_L31P_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|B11 |sram1_io<12> |IOB |IO_L29N_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | | |
|B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | | |
|B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | | |
|B10 |ide_dior |IOB |IO_L31P_1 |OUTPUT |LVTTL |1 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|B11 | |DIFFS |IO_L29N_1 |UNUSED | |1 | | | | | | | | | |
|B12 |ide_da<0> |IOB |IO_L27N_1 |OUTPUT |LVTTL |1 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|B13 |ide_da<1> |IOB |IO_L10P_1 |OUTPUT |LVTTL |1 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|B14 |ide_da<2> |IOB |IO_L01P_1/VRN_1 |OUTPUT |LVTTL |1 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|B15 | | |GND | | | | | | | | | | | | |
|B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | | |
|C1 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | | |
|C2 |sram2_io<9> |IOB |IO_L16N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|C3 |sram2_lb_n |IOB |IO_L16P_7/VREF_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|C1 |sram1_io<6> |IOB |IO_L01N_7/VRP_7 |BIDIR |LVCMOS25 |7 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|C2 |sram1_io<5> |IOB |IO_L16N_7 |BIDIR |LVCMOS25 |7 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|C3 |sram2_io<12> |IOB |IO_L16P_7/VREF_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|C4 | | |HSWAP_EN | | | | | | | | | | | | |
|C5 |slideswitch<3> |IOB |IO_L25N_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|C6 | |DIFFS |IO_L28N_0 |UNUSED | |0 | | | | | | | | | |
|C7 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | | |
|C8 | |DIFFM |IO_L31P_0/VREF_0 |UNUSED | |0 | | | | | | | | | |
|C9 |sysclk |IOB |IO_L32N_1/GCLK5 |INPUT |LVCMOS25 |1 | | | |NONE | | | |NO |NONE |
|C5 |ide_data_bus<8> |IOB |IO_L25N_0 |BIDIR |LVTTL |0 |12 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|C6 |ide_data_bus<9> |IOB |IO_L28N_0 |BIDIR |LVTTL |0 |12 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|C7 |ide_data_bus<10>|IOB |IO_L30N_0 |BIDIR |LVTTL |0 |12 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|C8 |ide_data_bus<11>|IOB |IO_L31P_0/VREF_0 |BIDIR |LVTTL |0 |12 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|C9 |ide_data_bus<12>|IOB |IO_L32N_1/GCLK5 |TRISTATE |LVTTL |1 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|C11 |sram1_io<13> |IOB |IO_L29P_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|C11 | |DIFFM |IO_L29P_1 |UNUSED | |1 | | | | | | | | | |
|C12 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | | |
|C13 | | |TMS | | | | | | | | | | | | |
|C14 | | |TCK | | | | | | | | | | | | |
|C15 | |DIFFS |IO_L16N_2 |UNUSED | |2 | | | | | | | | | |
|C16 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | | |
|D1 |sram2_ub_n |IOB |IO_L17N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|D2 |sram2_io<8> |IOB |IO_L17P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|D3 |sram1_ub_n |IOB |IO_L19P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|D1 |sram2_io<7> |IOB |IO_L17N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|D2 |sram2_io<8> |IOB |IO_L17P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|D3 |sram1_io<8> |IOB |IO_L19P_7 |BIDIR |LVCMOS25 |7 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|D4 | | |VCCINT | | | | | | | |1.2 | | | | |
|D5 |slideswitch<0> |IOB |IO/VREF_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|D6 |slideswitch<2> |IOB |IO_L27P_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|D7 | |DIFFM |IO_L29P_0 |UNUSED | |0 | | | | | | | | | |
|D8 | |DIFFS |IO_L31N_0 |UNUSED | |0 | | | | | | | | | |
|D9 |sram_a<17> |IOB |IO_L32P_1/GCLK4 |OUTPUT |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|D10 | |DIFFS |IO_L30N_1 |UNUSED | |1 | | | | | | | | | |
|D5 |ide_data_bus<7> |IOB |IO/VREF_0 |BIDIR |LVTTL |0 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|D6 |ide_data_bus<6> |IOB |IO_L27P_0 |BIDIR |LVTTL |0 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|D7 |ide_data_bus<4> |IOB |IO_L29P_0 |BIDIR |LVTTL |0 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|D8 |ide_data_bus<3> |IOB |IO_L31N_0 |BIDIR |LVTTL |0 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|D9 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | | |
|D10 |ide_data_bus<2> |IOB |IO_L30N_1 |BIDIR |LVTTL |1 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|D11 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | | |
|D12 | |IOB |IO/VREF_1 |UNUSED | |1 | | | | | | | | | |
|D13 | | |VCCINT | | | | | | | |1.2 | | | | |
|D14 | |DIFFM |IO_L16P_2 |UNUSED | |2 | | | | | | | | | |
|D14 |sevenseg_an<0> |IOB |IO_L16P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|D15 | |DIFFS |IO_L17N_2 |UNUSED | |2 | | | | | | | | | |
|D16 | |DIFFM |IO_L17P_2/VREF_2 |UNUSED | |2 | | | | | | | | | |
|E1 |sram2_io<12> |IOB |IO_L20N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E2 |sram2_io<10> |IOB |IO_L20P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E3 |sram2_io<11> |IOB |IO_L19N_7/VREF_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E4 |sram2_io<14> |IOB |IO_L21P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E1 |sram2_io<6> |IOB |IO_L20N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|E2 |sram2_io<9> |IOB |IO_L20P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|E3 |sram_a<8> |IOB |IO_L19N_7/VREF_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|E4 |sram_a<9> |IOB |IO_L21P_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|E5 | | |VCCINT | | | | | | | |1.2 | | | | |
|E6 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | | |
|E7 | |DIFFS |IO_L29N_0 |UNUSED | |0 | | | | | | | | | |
|E8 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|E9 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |
|E10 |sram1_io<14> |IOB |IO_L30P_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|E7 |ide_data_bus<5> |IOB |IO_L29N_0 |BIDIR |LVTTL |0 |24 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|E8 | | |VCCO_0 | | |0 | | | | |3.30 | | | | |
|E9 | | |VCCO_1 | | |1 | | | | |3.30 | | | | |
|E10 | |DIFFM |IO_L30P_1 |UNUSED | |1 | | | | | | | | | |
|E11 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | | |
|E12 | | |VCCINT | | | | | | | |1.2 | | | | |
|E13 | |DIFFS |IO_L19N_2 |UNUSED | |2 | | | | | | | | | |
|E14 | |DIFFM |IO_L19P_2 |UNUSED | |2 | | | | | | | | | |
|E13 |sevenseg_an<3> |IOB |IO_L19N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|E14 |sevenseg<7> |IOB |IO_L19P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|E15 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | | |
|E16 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | | |
|F1 | | |VCCAUX | | | | | | | |2.5 | | | | |
|F2 |sram2_io<15> |IOB |IO_L22N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F3 |sram_a<15> |IOB |IO_L22P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F4 |sram2_io<13> |IOB |IO_L21N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F5 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | | |
|F2 |sram1_io<10> |IOB |IO_L22N_7 |BIDIR |LVCMOS25 |7 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|F3 |sram_a<6> |IOB |IO_L22P_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|F4 |sram_a<7> |IOB |IO_L21N_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|F5 |sram2_io<11> |IOB |IO_L23P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|F6 | | |GND | | | | | | | | | | | | |
|F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|F8 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|F9 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |
|F10 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |
|F7 | | |VCCO_0 | | |0 | | | | |3.30 | | | | |
|F8 | | |VCCO_0 | | |0 | | | | |3.30 | | | | |
|F9 | | |VCCO_1 | | |1 | | | | |3.30 | | | | |
|F10 | | |VCCO_1 | | |1 | | | | |3.30 | | | | |
|F11 | | |GND | | | | | | | | | | | | |
|F12 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | | |
|F13 | |DIFFM |IO_L21P_2 |UNUSED | |2 | | | | | | | | | |
|F14 | |DIFFS |IO_L22N_2 |UNUSED | |2 | | | | | | | | | |
|F12 |slideswitch<0> |IOB |IO_L21N_2 |INPUT |LVCMOS25 |2 | | | |NONE | |LOCATED | |NO |NONE |
|F13 |sevenseg<2> |IOB |IO_L21P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|F14 |sevenseg_an<2> |IOB |IO_L22N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|F15 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | | |
|F16 | | |VCCAUX | | | | | | | |2.5 | | | | |
|G1 |ide_data_bus<2> |IOB |IO_L40P_7 |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|G2 |ide_data_bus<7> |IOB |IO |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|G3 |ide_diow |IOB |IO_L24N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G4 |ide_dior |IOB |IO_L24P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G5 |sram_a<16> |IOB |IO_L23N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G1 |sram2_io<10> |IOB |IO_L40P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|G2 |sram2_io<5> |IOB |IO |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|G3 |sram_we_n |IOB |IO_L24N_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|G4 |sram_a<5> |IOB |IO_L24P_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|G5 |sram_a<10> |IOB |IO_L23N_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|G6 | | |VCCO_7 | | |7 | | | | |2.50 | | | | |
|G7 | | |GND | | | | | | | | | | | | |
|G8 | | |GND | | | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | | |
|G10 | | |GND | | | | | | | | | | | | |
|G11 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|G12 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | | |
|G13 | |DIFFM |IO_L23P_2 |UNUSED | |2 | | | | | | | | | |
|G14 | |DIFFS |IO_L24N_2 |UNUSED | |2 | | | | | | | | | |
|G15 |rs232_txd |IOB |IO_L24P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|G12 |slideswitch<1> |IOB |IO_L23N_2/VREF_2 |INPUT |LVCMOS25 |2 | | | |NONE | |LOCATED | |NO |NONE |
|G13 |sevenseg<6> |IOB |IO_L23P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|G14 |sevenseg_an<1> |IOB |IO_L24N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|G15 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | | |
|G16 | |DIFFM |IO |UNUSED | |2 | | | | | | | | | |
|H1 |ide_data_bus<4> |IOB |IO_L40N_7/VREF_7 |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|H1 |sram1_io<11> |IOB |IO_L40N_7/VREF_7 |BIDIR |LVCMOS25 |7 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|H2 | | |GND | | | | | | | | | | | | |
|H3 |ide_data_bus<5> |IOB |IO_L39N_7 |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|H4 |button<3> |IOB |IO_L39P_7 |INPUT |LVCMOS25 |7 | | | |IFD | | | |YES |NONE |
|H3 |sram_a<11> |IOB |IO_L39N_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|H4 |sram_a<12> |IOB |IO_L39P_7 |OUTPUT |LVCMOS25 |7 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|H5 | | |VCCO_7 | | |7 | | | | |2.50 | | | | |
|H6 | | |VCCO_7 | | |7 | | | | |2.50 | | | | |
|H7 | | |GND | | | | | | | | | | | | |
@@ -144,14 +144,14 @@ Pinout by Pin Number:
|H10 | | |GND | | | | | | | | | | | | |
|H11 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|H12 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|H13 | |DIFFS |IO_L39N_2 |UNUSED | |2 | | | | | | | | | |
|H14 |sram_oe_n |IOB |IO_L39P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H15 |sram_we_n |IOB |IO_L40N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H16 |sram_a<7> |IOB |IO_L40P_2/VREF_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|J1 |ide_data_bus<0> |IOB |IO_L40P_6/VREF_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J2 |ide_data_bus<3> |IOB |IO_L40N_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J3 |ide_data_bus<10>|IOB |IO_L39P_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J4 |ide_data_bus<1> |IOB |IO_L39N_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|H13 |slideswitch<3> |IOB |IO_L39N_2 |INPUT |LVCMOS25 |2 | | | |NONE | |LOCATED | |NO |NONE |
|H14 |slideswitch<2> |IOB |IO_L39P_2 |INPUT |LVCMOS25 |2 | | | |NONE | |LOCATED | |NO |NONE |
|H15 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | | |
|H16 | |DIFFM |IO_L40P_2/VREF_2 |UNUSED | |2 | | | | | | | | | |
|J1 |sram2_io<4> |IOB |IO_L40P_6/VREF_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|J2 |sram1_io<12> |IOB |IO_L40N_6 |TRISTATE |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|J3 |sram_a<14> |IOB |IO_L39P_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|J4 |sram_a<13> |IOB |IO_L39N_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|J5 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|J6 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|J7 | | |GND | | | | | | | | | | | | |
@@ -160,120 +160,120 @@ Pinout by Pin Number:
|J10 | | |GND | | | | | | | | | | | | |
|J11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|J12 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|J13 |sram1_io<3> |IOB |IO_L39P_3 |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|J14 |sram1_io<4> |IOB |IO_L39N_3 |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|J13 |slideswitch<5> |IOB |IO_L39P_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|J14 |slideswitch<4> |IOB |IO_L39N_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|J15 | | |GND | | | | | | | | | | | | |
|J16 |sram_a<0> |IOB |IO_L40N_3/VREF_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K1 |ide_data_bus<11>|IOB |IO |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|K2 |ide_data_bus<9> |IOB |IO_L24P_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|K3 |ide_data_bus<8> |IOB |IO_L24N_6/VREF_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|K4 |ide_cs<0> |IOB |IO_L23P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|K5 |ide_data_bus<6> |IOB |IO_L23N_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J16 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | | |
|K1 |sram2_io<3> |IOB |IO |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|K2 |sram2_io<13> |IOB |IO_L24P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|K3 |sram_a<15> |IOB |IO_L24N_6/VREF_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|K4 |sram_oe_n |IOB |IO_L23P_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|K5 |sram_a<16> |IOB |IO_L23N_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|K6 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|K7 | | |GND | | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | | |
|K10 | | |GND | | | | | | | | | | | | |
|K11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|K12 |sram_a<13> |IOB |IO_L23N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K13 |sram1_io<6> |IOB |IO_L24P_3 |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|K14 |sram_a<14> |IOB |IO_L24N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K15 |sram1_io<5> |IOB |IO |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|K16 |sram_a<3> |IOB |IO_L40P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K12 |led<0> |IOB |IO_L23N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|K13 |slideswitch<7> |IOB |IO_L24P_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|K14 |slideswitch<6> |IOB |IO_L24N_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|K15 | |DIFFS |IO |UNUSED | |3 | | | | | | | | | |
|K16 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | | |
|L1 | | |VCCAUX | | | | | | | |2.5 | | | | |
|L2 |ide_data_bus<12>|IOB |IO_L22P_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L3 |ide_data_bus<14>|IOB |IO_L22N_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L4 |ide_data_bus<15>|IOB |IO_L21P_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L5 |ide_data_bus<13>|IOB |IO_L21N_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L2 |sram1_io<13> |IOB |IO_L22P_6 |TRISTATE |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|L3 |sram_a<17> |IOB |IO_L22N_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|L4 |sram_a<4> |IOB |IO_L21P_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|L5 |sram_a<0> |IOB |IO_L21N_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|L6 | | |GND | | | | | | | | | | | | |
|L7 | | |VCCO_5 | | |5 | | | | |2.50 | | | | |
|L8 | | |VCCO_5 | | |5 | | | | |2.50 | | | | |
|L9 | | |VCCO_4 | | |4 | | | | |2.50 | | | | |
|L10 | | |VCCO_4 | | |4 | | | | |2.50 | | | | |
|L11 | | |GND | | | | | | | | | | | | |
|L12 |sram_a<10> |IOB |IO_L23P_3/VREF_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L13 |sram_a<11> |IOB |IO_L21N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L14 |sram_a<9> |IOB |IO_L22P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L15 |sram_a<8> |IOB |IO_L22N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L12 |led<2> |IOB |IO_L23P_3/VREF_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|L13 |button<2> |IOB |IO_L21N_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|L14 |button<3> |IOB |IO_L22P_3 |INPUT |LVCMOS25 |3 | | | |IFD | |LOCATED | |YES |NONE |
|L15 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | | |
|L16 | | |VCCAUX | | | | | | | |2.5 | | | | |
|M1 |sram2_io<6> |IOB |IO_L20P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M2 |sram2_io<5> |IOB |IO_L20N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M3 |sram2_io<4> |IOB |IO_L19P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M4 |sram2_io<3> |IOB |IO_L19N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M1 |sram2_io<14> |IOB |IO_L20P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|M2 |sram2_io<2> |IOB |IO_L20N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|M3 |sram_a<3> |IOB |IO_L19P_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|M4 |sram_a<2> |IOB |IO_L19N_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|M5 | | |VCCINT | | | | | | | |1.2 | | | | |
|M6 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | | |
|M7 | |DIFFM |IO_L30P_5 |UNUSED | |5 | | | | | | | | | |
|M8 | | |VCCO_5 | | |5 | | | | |2.50 | | | | |
|M9 | | |VCCO_4 | | |4 | | | | |2.50 | | | | |
|M10 | |DIFFS |IO_L29N_4 |UNUSED | |4 | | | | | | | | | |
|M11 |sram_a<2> |IOB |IO_L27N_4/DIN/D0 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |1.2 | | | | |
|M13 |sram_a<5> |IOB |IO_L21P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|M14 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | | |
|M15 |sram_a<12> |IOB |IO_L20P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|M16 |sram_a<6> |IOB |IO_L20N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|N1 |sram2_io<2> |IOB |IO_L17P_6/VREF_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N2 |sram2_io<1> |IOB |IO_L17N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N3 |sram2_io<0> |IOB |IO_L16P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M13 |button<0> |IOB |IO_L21P_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|M14 |button<1> |IOB |IO_L19N_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|M15 | |DIFFM |IO_L20P_3 |UNUSED | |3 | | | | | | | | | |
|M16 | |DIFFS |IO_L20N_3 |UNUSED | |3 | | | | | | | | | |
|N1 |sram2_io<15> |IOB |IO_L17P_6/VREF_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N2 |sram2_io<1> |IOB |IO_L17N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N3 |sram_a<1> |IOB |IO_L16P_6 |OUTPUT |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|N4 | | |VCCINT | | | | | | | |1.2 | | | | |
|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|N5 |sram2_ce_n |IOB |IO |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N6 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | | |
|N7 | |DIFFS |IO_L30N_5 |UNUSED | |5 | | | | | | | | | |
|N8 |sram1_io<0> |IOB |IO_L32P_5/GCLK2 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|N9 |sram1_io<8> |IOB |IO_L31N_4/INIT_B |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|N7 |sram1_io<0> |IOB |IO_L30N_5 |BIDIR |LVCMOS25 |5 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|N8 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | | |
|N9 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | | |
|N10 | |DIFFM |IO_L29P_4 |UNUSED | |4 | | | | | | | | | |
|N11 |rs232_rxd |IOB |IO_L27P_4/D1 |INPUT |LVCMOS25 |4 | | | |IFD | | | |YES |NONE |
|N12 |sram1_io<9> |IOB |IO/VREF_4 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|N11 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | | |
|N12 |led<5> |IOB |IO/VREF_4 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N13 | | |VCCINT | | | | | | | |1.2 | | | | |
|N14 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | | |
|N15 | |DIFFM |IO_L17P_3/VREF_3 |UNUSED | |3 | | | | | | | | | |
|N16 | |DIFFS |IO_L17N_3 |UNUSED | |3 | | | | | | | | | |
|P1 |sram2_ce_n |IOB |IO_L01P_6/VRN_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|P2 |sram1_lb_n |IOB |IO_L16N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N14 |led<3> |IOB |IO_L19P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N15 |sevenseg<5> |IOB |IO_L17P_3/VREF_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|N16 |sevenseg<1> |IOB |IO_L17N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P1 |sram1_io<14> |IOB |IO_L01P_6/VRN_6 |TRISTATE |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|P2 |sram2_io<0> |IOB |IO_L16N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P3 | | |M0 | | | | | | | | | | | | |
|P4 | | |M2 | | | | | | | | | | | | |
|P5 |ide_cs<1> |IOB |IO_L27P_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|P6 | |DIFFM |IO_L29P_5/VREF_5 |UNUSED | |5 | | | | | | | | | |
|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|P8 |sram1_io<1> |IOB |IO_L32N_5/GCLK3 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|P9 |sram_a<4> |IOB |IO_L31P_4/DOUT/BUSY|OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|P5 |sram2_lb_n |IOB |IO_L27P_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P6 |sram1_lb_n |IOB |IO_L29P_5/VREF_5 |OUTPUT |LVCMOS25 |5 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|P7 |sram1_ce_n |IOB |IO |OUTPUT |LVCMOS25 |5 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|P8 |sram1_io<9> |IOB |IO_L32N_5/GCLK3 |BIDIR |LVCMOS25 |5 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|P9 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | | |
|P10 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | | |
|P11 | |DIFFS |IO_L28N_4 |UNUSED | |4 | | | | | | | | | |
|P12 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | | |
|P13 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | |
|P14 | |DIFFM |IO_L16P_3 |UNUSED | |3 | | | | | | | | | |
|P15 | |DIFFS |IO_L16N_3 |UNUSED | |3 | | | | | | | | | |
|P16 | |DIFFS |IO_L01N_3/VRP_3 |UNUSED | |3 | | | | | | | | | |
|R1 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | | |
|P11 |led<7> |IOB |IO_L28N_4 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P12 |led<6> |IOB |IO_L25N_4 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P13 |led<4> |IOB |IO/VREF_4 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P14 |led<1> |IOB |IO_L16P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P15 |sevenseg<4> |IOB |IO_L16N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|P16 |sevenseg<0> |IOB |IO_L01N_3/VRP_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|R1 |sram1_io<15> |IOB |IO_L01N_6/VRP_6 |TRISTATE |LVCMOS25 |6 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|R2 | | |GND | | | | | | | | | | | | |
|R3 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | | |
|R4 |sram2_io<7> |IOB |IO_L10P_5/VRN_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|R5 |ide_da<1> |IOB |IO_L27N_5/VREF_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|R6 | |DIFFS |IO_L29N_5 |UNUSED | |5 | | | | | | | | | |
|R4 |sram2_ub_n |IOB |IO_L10P_5/VRN_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|R5 |sram1_io<4> |IOB |IO_L27N_5/VREF_5 |BIDIR |LVCMOS25 |5 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|R6 |sram1_io<2> |IOB |IO_L29N_5 |BIDIR |LVCMOS25 |5 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|R7 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | | |
|R8 | | |GND | | | | | | | | | | | | |
|R9 |sram1_io<11> |IOB |IO_L32N_4/GCLK1 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|R9 | |DIFFS |IO_L32N_4/GCLK1 |UNUSED | |4 | | | | | | | | | |
|R10 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | | |
|R11 | |DIFFM |IO_L28P_4 |UNUSED | |4 | | | | | | | | | |
|R12 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | | |
|R13 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | | |
|R13 |rs232_txd |IOB |IO_L01N_4/VRP_4 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|R14 | | |DONE | | | | | | | | | | | | |
|R15 | | |GND | | | | | | | | | | | | |
|R16 | |DIFFM |IO_L01P_3/VRN_3 |UNUSED | |3 | | | | | | | | | |
|R16 |sevenseg<3> |IOB |IO_L01P_3/VRN_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|T1 | | |GND | | | | | | | | | | | | |
|T2 | | |M1 | | | | | | | | | | | | |
|T3 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | | |
|T4 | |DIFFS |IO_L10N_5/VRP_5 |UNUSED | |5 | | | | | | | | | |
|T5 |ide_da<2> |IOB |IO |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|T4 |sram1_ub_n |IOB |IO_L10N_5/VRP_5 |OUTPUT |LVCMOS25 |5 |12 |FAST |NONE** | | |LOCATED | |NO |NONE |
|T5 |sram1_io<3> |IOB |IO |BIDIR |LVCMOS25 |5 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|T6 | | |VCCAUX | | | | | | | |2.5 | | | | |
|T7 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | | |
|T8 |sram1_io<2> |IOB |IO/VREF_5 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|T9 |sram1_io<7> |IOB |IO_L32P_4/GCLK0 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|T10 |sram1_ce_n |IOB |IO/VREF_4 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|T8 |sram1_io<1> |IOB |IO/VREF_5 |BIDIR |LVCMOS25 |5 |12 |FAST |NONE** |NONE | |LOCATED | |NO |NONE |
|T9 |sysclk |IOB |IO_L32P_4/GCLK0 |INPUT |LVCMOS25 |4 | | | |NONE | |LOCATED | |NO |NONE |
|T10 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | |
|T11 | | |VCCAUX | | | | | | | |2.5 | | | | |
|T12 |sram_a<1> |IOB |IO |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|T13 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | | |
|T14 |sram1_io<10> |IOB |IO |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|T12 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|T13 |rs232_rxd |IOB |IO_L01P_4/VRN_4 |INPUT |LVCMOS25 |4 | | | |IFD | |LOCATED | |YES |NONE |
|T14 | |DIFFS |IO |UNUSED | |4 | | | | | | | | | |
|T15 | | |CCLK | | | | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

2
xilinx/pdp8/top_prev_built.ngd
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File diff suppressed because one or more lines are too long

60
xilinx/pdp8/top_summary.html
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@@ -19,13 +19,13 @@
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s1000-5ft256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>48 Warnings</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>68 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 8.2i</TD>
<TD>ISE 8.2.03i</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
<TD>Fri Apr 16 08:19:50 2010</TD>
<TD>Fri Apr 23 22:48:46 2010</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
@@ -37,53 +37,65 @@
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>519</TD>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number Slice Registers</B></TD>
<TD ALIGN=RIGHT>493</TD>
<TD ALIGN=RIGHT>15,360</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>481</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>12</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>1,532</TD>
<TD ALIGN=RIGHT>1,605</TD>
<TD ALIGN=RIGHT>15,360</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD ALIGN=RIGHT>10%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>1,120</TD>
<TD ALIGN=RIGHT>7,680</TD>
<TD ALIGN=RIGHT>14%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>1,120</TD>
<TD ALIGN=RIGHT>1,120</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>1,120</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>1,884</TD>
<TD ALIGN=RIGHT>1,964</TD>
<TD ALIGN=RIGHT>15,360</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as logic</TD>
<TD ALIGN=RIGHT>1,532</TD>
<TD ALIGN=RIGHT>1,605</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as a route-thru</TD>
<TD ALIGN=RIGHT>160</TD>
<TD ALIGN=RIGHT>167</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
@@ -95,9 +107,9 @@
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='top_map.mrp?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>89</TD>
<TD ALIGN=RIGHT>116</TD>
<TD ALIGN=RIGHT>173</TD>
<TD ALIGN=RIGHT>51%</TD>
<TD ALIGN=RIGHT>67%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
@@ -113,13 +125,13 @@
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total equivalent gate count for design</B></TD>
<TD ALIGN=RIGHT>40,005</TD>
<TD ALIGN=RIGHT>40,343</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Additional JTAG gate count for IOBs</TD>
<TD ALIGN=RIGHT>4,272</TD>
<TD ALIGN=RIGHT>5,568</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
@@ -150,12 +162,12 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:15:48 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>36 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>15 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:15:54 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:16:11 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>7 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:17:42 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>5 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:17:51 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:19:47 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Apr 23 22:47:31 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>33 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>13 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Apr 23 22:47:39 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Apr 23 22:47:49 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>12 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Apr 23 22:48:27 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>15 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Fri Apr 23 22:48:33 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Apr 23 22:48:45 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>8 Warnings</A></TD><TD ALIGN=LEFT>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>

860
xilinx/pdp8/top_usage.xml
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6
xilinx/pdp8/xst/dump.xst/top.prj/ntrc.scr
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@@ -1,3 +1,3 @@
set -xsthdpdir ./xst/
set -checkcmdline no
run -ifn top.prj -ifmt mixed -ofn top -ofmt NGC -p xc3s1000-5-ft256 -top top -opt_mode Speed -opt_level 1 -iuc NO -lso top.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 -crit Speed -power 1 -mapstyle lut -fsm_encoding Auto -t XILINX -addsub_extract yes
set -xsthdpdir ./xst\
set -checkcmdline no
run -ifn top.prj -ifmt mixed -ofn top -ofmt NGC -p xc3s1000-5-ft256 -top top -opt_mode Speed -opt_level 1 -iuc NO -lso top.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 -crit Speed -power 1 -mapstyle lut -fsm_encoding Auto -t XILINX -addsub_extract yes

29
xilinx/pdp8/xst/work/hdllib.ref
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@@ -1,13 +1,16 @@
MO ide_disk NULL ../../rtl/ide_disk.v vlg10/ide__disk.bin 1271420062
MO pdp8_io NULL ../../rtl/pdp8_io.v vlg2F/pdp8__io.bin 1271420062
MO brg NULL ../../rtl/brg.v vlg33/brg.bin 1271420062
MO pdp8_kw NULL ../../rtl/pdp8_kw.v vlg41/pdp8__kw.bin 1271420062
MO pdp8_rf NULL ../../rtl/pdp8_rf.v vlg53/pdp8__rf.bin 1271420062
MO pdp8_tt NULL ../../rtl/pdp8_tt.v vlg6B/pdp8__tt.bin 1271420062
MO debounce NULL ../../rtl/debounce.v vlg1D/debounce.bin 1271420062
MO top NULL ../../rtl/top.v vlg6F/top.bin 1271420062
MO ram_256x12 NULL ../../rtl/ram_256x12.v vlg37/ram__256x12.bin 1271420061
MO pdp8 NULL ../../rtl/pdp8.v vlg5C/pdp8.bin 1271420062
MO ide NULL ../../rtl/ide.v vlg1A/ide.bin 1271420061
MO pdp8_ram NULL ../../rtl/pdp8_ram.v vlg73/pdp8__ram.bin 1271420062
MO uart NULL ../../rtl/uart.v vlg48/uart.bin 1271420061
MO ide_disk NULL ../../rtl/ide_disk.v vlg10/ide__disk.bin 1272077203
MO bootrom NULL ../../rtl/bootrom.v vlg4A/bootrom.bin 1272077203
MO display NULL ../../rtl/display.v vlg1E/display.bin 1272077203
MO pdp8_io NULL ../../rtl/pdp8_io.v vlg2F/pdp8__io.bin 1272077203
MO brg NULL ../../rtl/brg.v vlg33/brg.bin 1272077203
MO pdp8_kw NULL ../../rtl/pdp8_kw.v vlg41/pdp8__kw.bin 1272077203
MO pdp8_rf NULL ../../rtl/pdp8_rf.v vlg53/pdp8__rf.bin 1272077203
MO pdp8_tt NULL ../../rtl/pdp8_tt.v vlg6B/pdp8__tt.bin 1272077203
MO debounce NULL ../../rtl/debounce.v vlg1D/debounce.bin 1272077203
MO top NULL ../../rtl/top.v vlg6F/top.bin 1272077203
MO ram_256x12 NULL ../../rtl/ram_256x12.v vlg37/ram__256x12.bin 1272077203
MO pdp8 NULL ../../rtl/pdp8.v vlg5C/pdp8.bin 1272077203
MO ide NULL ../../rtl/ide.v vlg1A/ide.bin 1272077203
MO sevensegdecode NULL ../../rtl/sevensegdecode.v vlg28/sevensegdecode.bin 1272077203
MO pdp8_ram NULL ../../rtl/pdp8_ram.v vlg73/pdp8__ram.bin 1272077203
MO uart NULL ../../rtl/uart.v vlg48/uart.bin 1272077203

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xilinx/pdp8/xst/work/vlg10/ide__disk.bin
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xilinx/pdp8/xst/work/vlg73/pdp8__ram.bin
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