243 lines
11 KiB
Plaintext
243 lines
11 KiB
Plaintext
Release 8.2.03i par I.34
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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LATITUDE:: Fri Apr 23 22:47:52 2010
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par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
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Constraints file: top.pcf.
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Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
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"top" is an NCD, version 3.1, device xc3s1000, package ft256, speed -5
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
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the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
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balance between the fastest runtime and best performance, set the effort level to "med".
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Device speed data version: "PRODUCTION 1.39 2006-08-18".
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Device Utilization Summary:
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Number of BUFGMUXs 3 out of 8 37%
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Number of External IOBs 116 out of 173 67%
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Number of LOCed IOBs 116 out of 116 100%
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Number of Slices 1120 out of 7680 14%
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Number of SLICEMs 96 out of 3840 2%
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Overall effort level (-ol): Standard
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Router effort level (-rl): Standard
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WARNING:Par:288 - The signal slideswitch<4>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal slideswitch<5>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal slideswitch<6>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal slideswitch<7>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal button<0>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal button<1>_IBUF has no load. PAR will not attempt to route this signal.
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WARNING:Par:288 - The signal button<2>_IBUF has no load. PAR will not attempt to route this signal.
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Starting Placer
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Phase 1.1
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Phase 1.1 (Checksum:98cb0b) REAL time: 4 secs
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Phase 2.7
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Phase 2.7 (Checksum:1312cfe) REAL time: 5 secs
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Phase 3.31
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Phase 3.31 (Checksum:1c9c37d) REAL time: 5 secs
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Phase 4.2
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.
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Phase 4.2 (Checksum:26259fc) REAL time: 7 secs
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Phase 5.8
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.........................................................
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..........................................................
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.........
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.......
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.......
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....
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Phase 5.8 (Checksum:b6bb50) REAL time: 15 secs
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Phase 6.5
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Phase 6.5 (Checksum:39386fa) REAL time: 15 secs
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Phase 7.18
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Phase 7.18 (Checksum:42c1d79) REAL time: 25 secs
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Phase 8.5
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 25 secs
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Writing design to file top.ncd
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Total REAL time to Placer completion: 26 secs
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Total CPU time to Placer completion: 25 secs
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Starting Router
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Phase 1: 8578 unrouted; REAL time: 26 secs
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Phase 2: 8072 unrouted; REAL time: 26 secs
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Phase 3: 2222 unrouted; REAL time: 27 secs
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Phase 4: 2222 unrouted; (56101) REAL time: 28 secs
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Phase 5: 2251 unrouted; (0) REAL time: 28 secs
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Phase 6: 0 unrouted; (0) REAL time: 31 secs
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Phase 7: 0 unrouted; (0) REAL time: 32 secs
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WARNING:Route:447 - CLK Net:ram_rd may have excessive skew because
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16 NON-CLK pins failed to route using a CLK template.
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WARNING:Route:447 - CLK Net:io/kw/kw_src_clk may have excessive skew because
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6 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
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WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/tx_baud_clk may have excessive skew because
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1 NON-CLK pins failed to route using a CLK template.
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WARNING:Route:447 - CLK Net:show_pc/aclk may have excessive skew because
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2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
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WARNING:Route:447 - CLK Net:reset_sw/slowclk may have excessive skew because
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1 NON-CLK pins failed to route using a CLK template.
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WARNING:Route:447 - CLK Net:clk may have excessive skew because
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1 NON-CLK pins failed to route using a CLK template.
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WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/rx_baud_clk may have excessive skew because
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1 NON-CLK pins failed to route using a CLK template.
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Total REAL time to Router completion: 32 secs
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Total CPU time to Router completion: 31 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| clk | BUFGMUX7| No | 377 | 0.372 | 0.987 |
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+---------------------+--------------+------+------+------------+-------------+
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| sysclk_BUFGP | BUFGMUX0| No | 47 | 0.198 | 0.837 |
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+---------------------+--------------+------+------+------------+-------------+
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|io/tt/baud_rate_gene | | | | | |
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| rator/rx_baud_clk | BUFGMUX2| No | 24 | 0.206 | 0.873 |
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+---------------------+--------------+------+------+------------+-------------+
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| io/kw/kw_src_clk | Local| | 7 | 0.913 | 1.831 |
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+---------------------+--------------+------+------+------------+-------------+
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| ram_rd | Local| | 27 | 0.072 | 2.050 |
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+---------------------+--------------+------+------+------------+-------------+
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| reset_sw/slowclk | Local| | 8 | 0.426 | 3.122 |
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+---------------------+--------------+------+------+------------+-------------+
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|io/tt/baud_rate_gene | | | | | |
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| rator/tx_baud_clk | Local| | 10 | 0.011 | 1.999 |
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+---------------------+--------------+------+------+------------+-------------+
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| show_pc/aclk | Local| | 3 | 0.593 | 1.538 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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The Delay Summary Report
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The AVERAGE CONNECTION DELAY for this design is: 1.144
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The MAXIMUM PIN DELAY IS: 4.815
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 4.456
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Listing Pin Delays by value: (nsec)
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d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
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--------- --------- --------- --------- --------- ---------
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4547 2799 845 329 19 0
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Timing Score: 0
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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Constraint | Requested | Actual | Logic | Absolute |Number of
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| | | Levels | Slack |errors
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | N/A | 11.651ns | 7 | N/A | N/A
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net io/ | N/A | 4.230ns | 3 | N/A | N/A
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kw/kw_src_clk | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net sys | N/A | 4.720ns | 2 | N/A | N/A
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clk_BUFGP | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net ram | N/A | 2.171ns | 1 | N/A | N/A
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_rd | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net io/ | N/A | 5.007ns | 2 | N/A | N/A
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tt/baud_rate_generator/rx_baud_clk | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net res | N/A | 2.836ns | 0 | N/A | N/A
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et_sw/slowclk | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net io/ | N/A | 4.343ns | 2 | N/A | N/A
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tt/baud_rate_generator/tx_baud_clk | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net sho | N/A | 2.638ns | 1 | N/A | N/A
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w_pc/aclk | | | | |
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
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constraint does not cover any paths or that it has no requested value.
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Generating Pad Report.
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All signals are completely routed.
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WARNING:Par:284 - There are 7 sourceless or loadless signals in this design. This design will not pass the DRC check run
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by Bitgen.
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Total REAL time to PAR completion: 34 secs
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Total CPU time to PAR completion: 33 secs
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Peak Memory Usage: 178 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 15
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Number of info messages: 1
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Writing design to file top.ncd
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PAR done!
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